1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2005, 2011 Freescale Semiconductor, Inc.
5 * Author: Shlomi Gridish <gridish@freescale.com>
7 * Description: UCC ethernet driver -- PHY handling
9 * Based on 8260_io/fcc_enet.c
14 #define MII_end ((u32)-2)
15 #define MII_read ((u32)-1)
17 #define MIIMIND_BUSY 0x00000001
18 #define MIIMIND_NOTVALID 0x00000004
20 #define UGETH_AN_TIMEOUT 2000
22 /* Cicada Extended Control Register 1 */
23 #define MII_CIS8201_EXT_CON1 0x17
24 #define MII_CIS8201_EXTCON1_INIT 0x0000
26 /* Cicada Interrupt Mask Register */
27 #define MII_CIS8201_IMASK 0x19
28 #define MII_CIS8201_IMASK_IEN 0x8000
29 #define MII_CIS8201_IMASK_SPEED 0x4000
30 #define MII_CIS8201_IMASK_LINK 0x2000
31 #define MII_CIS8201_IMASK_DUPLEX 0x1000
32 #define MII_CIS8201_IMASK_MASK 0xf000
34 /* Cicada Interrupt Status Register */
35 #define MII_CIS8201_ISTAT 0x1a
36 #define MII_CIS8201_ISTAT_STATUS 0x8000
37 #define MII_CIS8201_ISTAT_SPEED 0x4000
38 #define MII_CIS8201_ISTAT_LINK 0x2000
39 #define MII_CIS8201_ISTAT_DUPLEX 0x1000
41 /* Cicada Auxiliary Control/Status Register */
42 #define MII_CIS8201_AUX_CONSTAT 0x1c
43 #define MII_CIS8201_AUXCONSTAT_INIT 0x0004
44 #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
45 #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
46 #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
47 #define MII_CIS8201_AUXCONSTAT_100 0x0008
49 /* 88E1011 PHY Status Register */
50 #define MII_M1011_PHY_SPEC_STATUS 0x11
51 #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
52 #define MII_M1011_PHY_SPEC_STATUS_100 0x4000
53 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
54 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
55 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
56 #define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
58 #define MII_M1011_IEVENT 0x13
59 #define MII_M1011_IEVENT_CLEAR 0x0000
61 #define MII_M1011_IMASK 0x12
62 #define MII_M1011_IMASK_INIT 0x6400
63 #define MII_M1011_IMASK_CLEAR 0x0000
65 /* 88E1111 PHY Register */
66 #define MII_M1111_PHY_EXT_CR 0x14
67 #define MII_M1111_RX_DELAY 0x80
68 #define MII_M1111_TX_DELAY 0x2
69 #define MII_M1111_PHY_EXT_SR 0x1b
70 #define MII_M1111_HWCFG_MODE_MASK 0xf
71 #define MII_M1111_HWCFG_MODE_RGMII 0xb
73 #define MII_DM9161_SCR 0x10
74 #define MII_DM9161_SCR_INIT 0x0610
75 #define MII_DM9161_SCR_RMII_INIT 0x0710
77 /* DM9161 Specified Configuration and Status Register */
78 #define MII_DM9161_SCSR 0x11
79 #define MII_DM9161_SCSR_100F 0x8000
80 #define MII_DM9161_SCSR_100H 0x4000
81 #define MII_DM9161_SCSR_10F 0x2000
82 #define MII_DM9161_SCSR_10H 0x1000
84 /* DM9161 Interrupt Register */
85 #define MII_DM9161_INTR 0x15
86 #define MII_DM9161_INTR_PEND 0x8000
87 #define MII_DM9161_INTR_DPLX_MASK 0x0800
88 #define MII_DM9161_INTR_SPD_MASK 0x0400
89 #define MII_DM9161_INTR_LINK_MASK 0x0200
90 #define MII_DM9161_INTR_MASK 0x0100
91 #define MII_DM9161_INTR_DPLX_CHANGE 0x0010
92 #define MII_DM9161_INTR_SPD_CHANGE 0x0008
93 #define MII_DM9161_INTR_LINK_CHANGE 0x0004
94 #define MII_DM9161_INTR_INIT 0x0000
95 #define MII_DM9161_INTR_STOP \
96 (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
97 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
99 /* DM9161 10BT Configuration/Status */
100 #define MII_DM9161_10BTCSR 0x12
101 #define MII_DM9161_10BTCSR_INIT 0x7800
103 #define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
104 SUPPORTED_10baseT_Full | \
105 SUPPORTED_100baseT_Half | \
106 SUPPORTED_100baseT_Full | \
107 SUPPORTED_Autoneg | \
111 #define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
112 SUPPORTED_1000baseT_Half | \
113 SUPPORTED_1000baseT_Full)
115 #define MII_READ_COMMAND 0x00000001
117 #define MII_INTERRUPT_DISABLED 0x0
118 #define MII_INTERRUPT_ENABLED 0x1
121 #define SPEED_100 100
122 #define SPEED_1000 1000
124 /* Duplex, half or full. */
125 #define DUPLEX_HALF 0x00
126 #define DUPLEX_FULL 0x01
128 /* Indicates what features are supported by the interface. */
129 #define SUPPORTED_10baseT_Half (1 << 0)
130 #define SUPPORTED_10baseT_Full (1 << 1)
131 #define SUPPORTED_100baseT_Half (1 << 2)
132 #define SUPPORTED_100baseT_Full (1 << 3)
133 #define SUPPORTED_1000baseT_Half (1 << 4)
134 #define SUPPORTED_1000baseT_Full (1 << 5)
135 #define SUPPORTED_Autoneg (1 << 6)
136 #define SUPPORTED_TP (1 << 7)
137 #define SUPPORTED_AUI (1 << 8)
138 #define SUPPORTED_MII (1 << 9)
139 #define SUPPORTED_FIBRE (1 << 10)
140 #define SUPPORTED_BNC (1 << 11)
141 #define SUPPORTED_10000baseT_Full (1 << 12)
143 #define ADVERTISED_10baseT_Half (1 << 0)
144 #define ADVERTISED_10baseT_Full (1 << 1)
145 #define ADVERTISED_100baseT_Half (1 << 2)
146 #define ADVERTISED_100baseT_Full (1 << 3)
147 #define ADVERTISED_1000baseT_Half (1 << 4)
148 #define ADVERTISED_1000baseT_Full (1 << 5)
149 #define ADVERTISED_Autoneg (1 << 6)
150 #define ADVERTISED_TP (1 << 7)
151 #define ADVERTISED_AUI (1 << 8)
152 #define ADVERTISED_MII (1 << 9)
153 #define ADVERTISED_FIBRE (1 << 10)
154 #define ADVERTISED_BNC (1 << 11)
155 #define ADVERTISED_10000baseT_Full (1 << 12)
157 /* Taken from mii_if_info and sungem_phy.h */
158 struct uec_mii_info {
159 /* Information about the PHY type */
160 /* And management functions */
161 struct phy_info *phyinfo;
163 struct eth_device *dev;
165 /* forced speed & duplex (no autoneg)
166 * partner speed & duplex & pause (autoneg)
172 /* The most recently read link state */
175 /* Enabled Interrupts */
182 /* private data pointer */
183 /* For use by PHYs to maintain extra state */
186 /* Provided by ethernet driver */
187 int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
188 void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
192 /* struct phy_info: a structure which defines attributes for a PHY
194 * id will contain a number which represents the PHY. During
195 * startup, the driver will poll the PHY to find out what its
196 * UID--as defined by registers 2 and 3--is. The 32-bit result
197 * gotten from the PHY will be ANDed with phy_id_mask to
198 * discard any bits which may change based on revision numbers
199 * unimportant to functionality
201 * There are 6 commands which take a ugeth_mii_info structure.
202 * Each PHY must declare config_aneg, and read_status.
207 unsigned int phy_id_mask;
210 /* Called to initialize the PHY */
211 int (*init) (struct uec_mii_info * mii_info);
213 /* Called to suspend the PHY for power */
214 int (*suspend) (struct uec_mii_info * mii_info);
216 /* Reconfigures autonegotiation (or disables it) */
217 int (*config_aneg) (struct uec_mii_info * mii_info);
219 /* Determines the negotiated speed and duplex */
220 int (*read_status) (struct uec_mii_info * mii_info);
222 /* Clears any pending interrupts */
223 int (*ack_interrupt) (struct uec_mii_info * mii_info);
225 /* Enables or disables interrupts */
226 int (*config_intr) (struct uec_mii_info * mii_info);
228 /* Clears up any memory if needed */
229 void (*close) (struct uec_mii_info * mii_info);
232 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
233 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
235 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
236 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
237 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
239 #endif /* __UEC_PHY_H__ */