2 * Copyright (C) 2005 Freescale Semiconductor, Inc.
4 * Author: Shlomi Gridish
6 * Description: UCC GETH Driver -- PHY handling
8 * Based on 8260_io/fcc_enet.c
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
20 #include "asm/errno.h"
21 #include "asm/immap_qe.h"
29 #define ugphy_printk(format, arg...) \
30 printf(format "\n", ## arg)
32 #define ugphy_dbg(format, arg...) \
33 ugphy_printk(format , ## arg)
34 #define ugphy_err(format, arg...) \
35 ugphy_printk(format , ## arg)
36 #define ugphy_info(format, arg...) \
37 ugphy_printk(format , ## arg)
38 #define ugphy_warn(format, arg...) \
39 ugphy_printk(format , ## arg)
41 #ifdef UEC_VERBOSE_DEBUG
42 #define ugphy_vdbg ugphy_dbg
44 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
45 #endif /* UEC_VERBOSE_DEBUG */
47 /*--------------------------------------------------------------------+
48 * Fixed PHY (PHY-less) support for Ethernet Ports.
50 * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
51 *--------------------------------------------------------------------*/
54 * Some boards do not have a PHY for each ethernet port. These ports are known
55 * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
56 * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
57 * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
58 * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
59 * speed and duplex should be for the port.
61 * Example board header configuration file:
62 * #define CONFIG_FIXED_PHY 0xFFFFFFFF
63 * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
65 * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
66 * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
67 * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
68 * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
70 * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
71 * {name, speed, duplex},
73 * #define CONFIG_SYS_FIXED_PHY_PORTS \
74 * CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
75 * CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
78 #ifndef CONFIG_FIXED_PHY
79 #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
82 #ifndef CONFIG_SYS_FIXED_PHY_PORTS
83 #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
86 struct fixed_phy_port {
87 char name[NAMESIZE]; /* ethernet port name */
88 unsigned int speed; /* specified speed 10,100 or 1000 */
89 unsigned int duplex; /* specified duplex FULL or HALF */
92 static const struct fixed_phy_port fixed_phy_port[] = {
93 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
96 /*--------------------------------------------------------------------+
97 * BitBang MII support for ethernet ports
99 * Based from MPC8560ADS implementation
100 *--------------------------------------------------------------------*/
102 * Example board header file to define bitbang ethernet ports:
104 * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
105 * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
107 #ifndef CONFIG_SYS_BITBANG_PHY_PORTS
108 #define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
111 #if defined(CONFIG_BITBANGMII)
112 static const char *bitbang_phy_port[] = {
113 CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
115 #endif /* CONFIG_BITBANGMII */
117 static void config_genmii_advert (struct uec_mii_info *mii_info);
118 static void genmii_setup_forced (struct uec_mii_info *mii_info);
119 static void genmii_restart_aneg (struct uec_mii_info *mii_info);
120 static int gbit_config_aneg (struct uec_mii_info *mii_info);
121 static int genmii_config_aneg (struct uec_mii_info *mii_info);
122 static int genmii_update_link (struct uec_mii_info *mii_info);
123 static int genmii_read_status (struct uec_mii_info *mii_info);
124 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
125 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
127 /* Write value to the PHY for this device to the register at regnum, */
128 /* waiting until the write is done before it returns. All PHY */
129 /* configuration has to be done through the TSEC1 MIIM regs */
130 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
132 uec_private_t *ugeth = (uec_private_t *) dev->priv;
134 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
138 #if defined(CONFIG_BITBANGMII)
141 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
142 if (strncmp(dev->name, bitbang_phy_port[i],
143 sizeof(dev->name)) == 0) {
144 (void)bb_miiphy_write(NULL, mii_id, regnum, value);
148 #endif /* CONFIG_BITBANGMII */
150 ug_regs = ugeth->uec_mii_regs;
152 /* Stop the MII management read cycle */
153 out_be32 (&ug_regs->miimcom, 0);
154 /* Setting up the MII Mangement Address Register */
155 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
156 out_be32 (&ug_regs->miimadd, tmp_reg);
158 /* Setting up the MII Mangement Control Register with the value */
159 out_be32 (&ug_regs->miimcon, (u32) value);
162 /* Wait till MII management write is complete */
163 while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
166 /* Reads from register regnum in the PHY for device dev, */
167 /* returning the value. Clears miimcom first. All PHY */
168 /* configuration has to be done through the TSEC1 MIIM regs */
169 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
171 uec_private_t *ugeth = (uec_private_t *) dev->priv;
173 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
178 #if defined(CONFIG_BITBANGMII)
181 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
182 if (strncmp(dev->name, bitbang_phy_port[i],
183 sizeof(dev->name)) == 0) {
184 (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
188 #endif /* CONFIG_BITBANGMII */
190 ug_regs = ugeth->uec_mii_regs;
192 /* Setting up the MII Mangement Address Register */
193 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
194 out_be32 (&ug_regs->miimadd, tmp_reg);
196 /* clear MII management command cycle */
197 out_be32 (&ug_regs->miimcom, 0);
200 /* Perform an MII management read cycle */
201 out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
203 /* Wait till MII management write is complete */
204 while ((in_be32 (&ug_regs->miimind)) &
205 (MIIMIND_NOT_VALID | MIIMIND_BUSY));
207 /* Read MII management status */
208 value = (u16) in_be32 (&ug_regs->miimstat);
211 ("read wrong value : mii_id %d,mii_reg %d, base %08x",
212 mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
217 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
219 if (mii_info->phyinfo->ack_interrupt)
220 mii_info->phyinfo->ack_interrupt (mii_info);
223 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
226 mii_info->interrupts = interrupts;
227 if (mii_info->phyinfo->config_intr)
228 mii_info->phyinfo->config_intr (mii_info);
231 /* Writes MII_ADVERTISE with the appropriate values, after
232 * sanitizing advertise to make sure only supported features
235 static void config_genmii_advert (struct uec_mii_info *mii_info)
240 /* Only allow advertising what this PHY supports */
241 mii_info->advertising &= mii_info->phyinfo->features;
242 advertise = mii_info->advertising;
244 /* Setup standard advertisement */
245 adv = phy_read (mii_info, PHY_ANAR);
246 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
247 if (advertise & ADVERTISED_10baseT_Half)
248 adv |= ADVERTISE_10HALF;
249 if (advertise & ADVERTISED_10baseT_Full)
250 adv |= ADVERTISE_10FULL;
251 if (advertise & ADVERTISED_100baseT_Half)
252 adv |= ADVERTISE_100HALF;
253 if (advertise & ADVERTISED_100baseT_Full)
254 adv |= ADVERTISE_100FULL;
255 phy_write (mii_info, PHY_ANAR, adv);
258 static void genmii_setup_forced (struct uec_mii_info *mii_info)
261 u32 features = mii_info->phyinfo->features;
263 ctrl = phy_read (mii_info, PHY_BMCR);
265 ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
266 PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
267 ctrl |= PHY_BMCR_RESET;
269 switch (mii_info->speed) {
271 if (features & (SUPPORTED_1000baseT_Half
272 | SUPPORTED_1000baseT_Full)) {
273 ctrl |= PHY_BMCR_1000_MBPS;
276 mii_info->speed = SPEED_100;
278 if (features & (SUPPORTED_100baseT_Half
279 | SUPPORTED_100baseT_Full)) {
280 ctrl |= PHY_BMCR_100_MBPS;
283 mii_info->speed = SPEED_10;
285 if (features & (SUPPORTED_10baseT_Half
286 | SUPPORTED_10baseT_Full))
288 default: /* Unsupported speed! */
289 ugphy_err ("%s: Bad speed!", mii_info->dev->name);
293 phy_write (mii_info, PHY_BMCR, ctrl);
296 /* Enable and Restart Autonegotiation */
297 static void genmii_restart_aneg (struct uec_mii_info *mii_info)
301 ctl = phy_read (mii_info, PHY_BMCR);
302 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
303 phy_write (mii_info, PHY_BMCR, ctl);
306 static int gbit_config_aneg (struct uec_mii_info *mii_info)
311 if (mii_info->autoneg) {
312 /* Configure the ADVERTISE register */
313 config_genmii_advert (mii_info);
314 advertise = mii_info->advertising;
316 adv = phy_read (mii_info, MII_1000BASETCONTROL);
317 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
318 MII_1000BASETCONTROL_HALFDUPLEXCAP);
319 if (advertise & SUPPORTED_1000baseT_Half)
320 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
321 if (advertise & SUPPORTED_1000baseT_Full)
322 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
323 phy_write (mii_info, MII_1000BASETCONTROL, adv);
325 /* Start/Restart aneg */
326 genmii_restart_aneg (mii_info);
328 genmii_setup_forced (mii_info);
333 static int marvell_config_aneg (struct uec_mii_info *mii_info)
335 /* The Marvell PHY has an errata which requires
336 * that certain registers get written in order
337 * to restart autonegotiation */
338 phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
340 phy_write (mii_info, 0x1d, 0x1f);
341 phy_write (mii_info, 0x1e, 0x200c);
342 phy_write (mii_info, 0x1d, 0x5);
343 phy_write (mii_info, 0x1e, 0);
344 phy_write (mii_info, 0x1e, 0x100);
346 gbit_config_aneg (mii_info);
351 static int genmii_config_aneg (struct uec_mii_info *mii_info)
353 if (mii_info->autoneg) {
354 config_genmii_advert (mii_info);
355 genmii_restart_aneg (mii_info);
357 genmii_setup_forced (mii_info);
362 static int genmii_update_link (struct uec_mii_info *mii_info)
366 /* Status is read once to clear old link state */
367 phy_read (mii_info, PHY_BMSR);
370 * Wait if the link is up, and autonegotiation is in progress
371 * (ie - we're capable and it's not done)
373 status = phy_read(mii_info, PHY_BMSR);
374 if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE)
375 && !(status & PHY_BMSR_AUTN_COMP)) {
378 while (!(status & PHY_BMSR_AUTN_COMP)) {
382 if (i > UGETH_AN_TIMEOUT) {
388 udelay(1000); /* 1 ms */
389 status = phy_read(mii_info, PHY_BMSR);
393 if (status & PHY_BMSR_LS)
402 static int genmii_read_status (struct uec_mii_info *mii_info)
407 /* Update the link, but return if there
409 err = genmii_update_link (mii_info);
413 if (mii_info->autoneg) {
414 status = phy_read(mii_info, MII_1000BASETSTATUS);
416 if (status & (LPA_1000FULL | LPA_1000HALF)) {
417 mii_info->speed = SPEED_1000;
418 if (status & LPA_1000FULL)
419 mii_info->duplex = DUPLEX_FULL;
421 mii_info->duplex = DUPLEX_HALF;
423 status = phy_read(mii_info, PHY_ANLPAR);
425 if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
426 mii_info->duplex = DUPLEX_FULL;
428 mii_info->duplex = DUPLEX_HALF;
429 if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
430 mii_info->speed = SPEED_100;
432 mii_info->speed = SPEED_10;
436 /* On non-aneg, we assume what we put in BMCR is the speed,
437 * though magic-aneg shouldn't prevent this case from occurring
443 static int bcm_init(struct uec_mii_info *mii_info)
445 struct eth_device *edev = mii_info->dev;
446 uec_private_t *uec = edev->priv;
448 gbit_config_aneg(mii_info);
450 if ((uec->uec_info->enet_interface_type == RGMII_RXID) &&
451 (uec->uec_info->speed == 1000)) {
455 /* Wait for aneg to complete. */
457 val = phy_read(mii_info, PHY_BMSR);
458 while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
460 /* Set RDX clk delay. */
461 phy_write(mii_info, 0x18, 0x7 | (7 << 12));
463 val = phy_read(mii_info, 0x18);
464 /* Set RDX-RXC skew. */
466 val |= (7 | (7 << 12));
467 /* Write bits 14:0. */
469 phy_write(mii_info, 0x18, val);
475 static int marvell_init(struct uec_mii_info *mii_info)
477 struct eth_device *edev = mii_info->dev;
478 uec_private_t *uec = edev->priv;
479 enum enet_interface_type iface = uec->uec_info->enet_interface_type;
480 int speed = uec->uec_info->speed;
482 if ((speed == 1000) &&
483 (iface == RGMII_ID ||
484 iface == RGMII_RXID ||
485 iface == RGMII_TXID)) {
488 temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
489 if (iface == RGMII_ID) {
490 temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
491 } else if (iface == RGMII_RXID) {
492 temp &= ~MII_M1111_TX_DELAY;
493 temp |= MII_M1111_RX_DELAY;
494 } else if (iface == RGMII_TXID) {
495 temp &= ~MII_M1111_RX_DELAY;
496 temp |= MII_M1111_TX_DELAY;
498 phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
500 temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR);
501 temp &= ~MII_M1111_HWCFG_MODE_MASK;
502 temp |= MII_M1111_HWCFG_MODE_RGMII;
503 phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
505 phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
511 static int marvell_read_status (struct uec_mii_info *mii_info)
516 /* Update the link, but return if there
518 err = genmii_update_link (mii_info);
522 /* If the link is up, read the speed and duplex */
523 /* If we aren't autonegotiating, assume speeds
525 if (mii_info->autoneg && mii_info->link) {
528 status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
530 /* Get the duplexity */
531 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
532 mii_info->duplex = DUPLEX_FULL;
534 mii_info->duplex = DUPLEX_HALF;
537 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
539 case MII_M1011_PHY_SPEC_STATUS_1000:
540 mii_info->speed = SPEED_1000;
542 case MII_M1011_PHY_SPEC_STATUS_100:
543 mii_info->speed = SPEED_100;
546 mii_info->speed = SPEED_10;
555 static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
557 /* Clear the interrupts by reading the reg */
558 phy_read (mii_info, MII_M1011_IEVENT);
563 static int marvell_config_intr (struct uec_mii_info *mii_info)
565 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
566 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
568 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
573 static int dm9161_init (struct uec_mii_info *mii_info)
576 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
578 /* PHY and MAC connect */
579 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
582 phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
584 config_genmii_advert (mii_info);
585 /* Start/restart aneg */
586 genmii_config_aneg (mii_info);
591 static int dm9161_config_aneg (struct uec_mii_info *mii_info)
596 static int dm9161_read_status (struct uec_mii_info *mii_info)
601 /* Update the link, but return if there was an error */
602 err = genmii_update_link (mii_info);
605 /* If the link is up, read the speed and duplex
606 If we aren't autonegotiating assume speeds are as set */
607 if (mii_info->autoneg && mii_info->link) {
608 status = phy_read (mii_info, MII_DM9161_SCSR);
609 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
610 mii_info->speed = SPEED_100;
612 mii_info->speed = SPEED_10;
614 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
615 mii_info->duplex = DUPLEX_FULL;
617 mii_info->duplex = DUPLEX_HALF;
623 static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
625 /* Clear the interrupt by reading the reg */
626 phy_read (mii_info, MII_DM9161_INTR);
631 static int dm9161_config_intr (struct uec_mii_info *mii_info)
633 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
634 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
636 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
641 static void dm9161_close (struct uec_mii_info *mii_info)
645 static int fixed_phy_aneg (struct uec_mii_info *mii_info)
647 mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
651 static int fixed_phy_read_status (struct uec_mii_info *mii_info)
655 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
656 if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
657 strlen(mii_info->dev->name)) == 0) {
658 mii_info->speed = fixed_phy_port[i].speed;
659 mii_info->duplex = fixed_phy_port[i].duplex;
660 mii_info->link = 1; /* Link is always UP */
668 static int smsc_config_aneg (struct uec_mii_info *mii_info)
673 static int smsc_read_status (struct uec_mii_info *mii_info)
678 /* Update the link, but return if there
680 err = genmii_update_link (mii_info);
684 /* If the link is up, read the speed and duplex */
685 /* If we aren't autonegotiating, assume speeds
687 if (mii_info->autoneg && mii_info->link) {
690 status = phy_read (mii_info, 0x1f);
691 val = (status & 0x1c) >> 2;
695 mii_info->duplex = DUPLEX_HALF;
696 mii_info->speed = SPEED_10;
699 mii_info->duplex = DUPLEX_FULL;
700 mii_info->speed = SPEED_10;
703 mii_info->duplex = DUPLEX_HALF;
704 mii_info->speed = SPEED_100;
707 mii_info->duplex = DUPLEX_FULL;
708 mii_info->speed = SPEED_100;
717 static struct phy_info phy_info_dm9161 = {
718 .phy_id = 0x0181b880,
719 .phy_id_mask = 0x0ffffff0,
720 .name = "Davicom DM9161E",
722 .config_aneg = dm9161_config_aneg,
723 .read_status = dm9161_read_status,
724 .close = dm9161_close,
727 static struct phy_info phy_info_dm9161a = {
728 .phy_id = 0x0181b8a0,
729 .phy_id_mask = 0x0ffffff0,
730 .name = "Davicom DM9161A",
731 .features = MII_BASIC_FEATURES,
733 .config_aneg = dm9161_config_aneg,
734 .read_status = dm9161_read_status,
735 .ack_interrupt = dm9161_ack_interrupt,
736 .config_intr = dm9161_config_intr,
737 .close = dm9161_close,
740 static struct phy_info phy_info_marvell = {
741 .phy_id = 0x01410c00,
742 .phy_id_mask = 0xffffff00,
743 .name = "Marvell 88E11x1",
744 .features = MII_GBIT_FEATURES,
745 .init = &marvell_init,
746 .config_aneg = &marvell_config_aneg,
747 .read_status = &marvell_read_status,
748 .ack_interrupt = &marvell_ack_interrupt,
749 .config_intr = &marvell_config_intr,
752 static struct phy_info phy_info_bcm5481 = {
753 .phy_id = 0x0143bca0,
754 .phy_id_mask = 0xffffff0,
755 .name = "Broadcom 5481",
756 .features = MII_GBIT_FEATURES,
757 .read_status = genmii_read_status,
761 static struct phy_info phy_info_fixedphy = {
762 .phy_id = CONFIG_FIXED_PHY,
763 .phy_id_mask = CONFIG_FIXED_PHY,
765 .config_aneg = fixed_phy_aneg,
766 .read_status = fixed_phy_read_status,
769 static struct phy_info phy_info_smsclan8700 = {
770 .phy_id = 0x0007c0c0,
771 .phy_id_mask = 0xfffffff0,
772 .name = "SMSC LAN8700",
773 .features = MII_BASIC_FEATURES,
774 .config_aneg = smsc_config_aneg,
775 .read_status = smsc_read_status,
778 static struct phy_info phy_info_genmii = {
779 .phy_id = 0x00000000,
780 .phy_id_mask = 0x00000000,
781 .name = "Generic MII",
782 .features = MII_BASIC_FEATURES,
783 .config_aneg = genmii_config_aneg,
784 .read_status = genmii_read_status,
787 static struct phy_info *phy_info[] = {
792 &phy_info_smsclan8700,
798 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
800 return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
803 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
805 mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
808 /* Use the PHY ID registers to determine what type of PHY is attached
809 * to device dev. return a struct phy_info structure describing that PHY
811 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
816 struct phy_info *theInfo = NULL;
818 /* Grab the bits from PHYIR1, and put them in the upper half */
819 phy_reg = phy_read (mii_info, PHY_PHYIDR1);
820 phy_ID = (phy_reg & 0xffff) << 16;
822 /* Grab the bits from PHYIR2, and put them in the lower half */
823 phy_reg = phy_read (mii_info, PHY_PHYIDR2);
824 phy_ID |= (phy_reg & 0xffff);
826 /* loop through all the known PHY types, and find one that */
827 /* matches the ID we read from the PHY. */
828 for (i = 0; phy_info[i]; i++)
829 if (phy_info[i]->phy_id ==
830 (phy_ID & phy_info[i]->phy_id_mask)) {
831 theInfo = phy_info[i];
835 /* This shouldn't happen, as we have generic PHY support */
836 if (theInfo == NULL) {
837 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
840 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
846 void marvell_phy_interface_mode (struct eth_device *dev,
847 enet_interface_type_e type,
851 uec_private_t *uec = (uec_private_t *) dev->priv;
852 struct uec_mii_info *mii_info;
855 if (!uec->mii_info) {
856 printf ("%s: the PHY not initialized\n", __FUNCTION__);
859 mii_info = uec->mii_info;
863 phy_write (mii_info, 0x00, 0x9140);
864 phy_write (mii_info, 0x1d, 0x001f);
865 phy_write (mii_info, 0x1e, 0x200c);
866 phy_write (mii_info, 0x1d, 0x0005);
867 phy_write (mii_info, 0x1e, 0x0000);
868 phy_write (mii_info, 0x1e, 0x0100);
869 phy_write (mii_info, 0x09, 0x0e00);
870 phy_write (mii_info, 0x04, 0x01e1);
871 phy_write (mii_info, 0x00, 0x9140);
872 phy_write (mii_info, 0x00, 0x1000);
874 phy_write (mii_info, 0x00, 0x2900);
875 phy_write (mii_info, 0x14, 0x0cd2);
876 phy_write (mii_info, 0x00, 0xa100);
877 phy_write (mii_info, 0x09, 0x0000);
878 phy_write (mii_info, 0x1b, 0x800b);
879 phy_write (mii_info, 0x04, 0x05e1);
880 phy_write (mii_info, 0x00, 0xa100);
881 phy_write (mii_info, 0x00, 0x2100);
883 } else if (speed == 10) {
884 phy_write (mii_info, 0x14, 0x8e40);
885 phy_write (mii_info, 0x1b, 0x800b);
886 phy_write (mii_info, 0x14, 0x0c82);
887 phy_write (mii_info, 0x00, 0x8100);
892 /* handle 88e1111 rev.B2 erratum 5.6 */
893 if (mii_info->autoneg) {
894 status = phy_read (mii_info, PHY_BMCR);
895 phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
897 /* now the B2 will correctly report autoneg completion status */
900 void change_phy_interface_mode (struct eth_device *dev,
901 enet_interface_type_e type, int speed)
903 #ifdef CONFIG_PHY_MODE_NEED_CHANGE
904 marvell_phy_interface_mode (dev, type, speed);