2 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/fsl_enet.h>
30 #define MAX_TX_THREADS 8
31 #define MAX_RX_THREADS 8
32 #define MAX_TX_QUEUES 8
33 #define MAX_RX_QUEUES 8
34 #define MAX_PREFETCHED_BDS 4
35 #define MAX_IPH_OFFSET_ENTRY 8
36 #define MAX_ENET_INIT_PARAM_ENTRIES_RX 9
37 #define MAX_ENET_INIT_PARAM_ENTRIES_TX 8
39 /* UEC UPSMR (Protocol Specific Mode Register)
41 #define UPSMR_ECM 0x04000000 /* Enable CAM Miss */
42 #define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */
43 #define UPSMR_PRO 0x00400000 /* Promiscuous */
44 #define UPSMR_CAP 0x00200000 /* CAM polarity */
45 #define UPSMR_RSH 0x00100000 /* Receive Short Frames */
46 #define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */
47 #define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */
48 #define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */
49 #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
50 #define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */
51 #define UPSMR_CAM 0x00000400 /* CAM Address Matching */
52 #define UPSMR_BRO 0x00000200 /* Broadcast Address */
53 #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
54 #define UPSMR_SGMM 0x00000020 /* SGMII mode */
56 #define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
58 /* UEC MACCFG1 (MAC Configuration 1 Register)
60 #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
61 #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */
62 #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
63 #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
64 #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */
65 #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
67 #define MACCFG1_INIT_VALUE (0)
69 /* UEC MACCFG2 (MAC Configuration 2 Register)
71 #define MACCFG2_PREL 0x00007000
72 #define MACCFG2_PREL_SHIFT (31 - 19)
73 #define MACCFG2_PREL_MASK 0x0000f000
74 #define MACCFG2_SRP 0x00000080
75 #define MACCFG2_STP 0x00000040
76 #define MACCFG2_RESERVED_1 0x00000020 /* must be set */
77 #define MACCFG2_LC 0x00000010 /* Length Check */
78 #define MACCFG2_MPE 0x00000008
79 #define MACCFG2_FDX 0x00000001 /* Full Duplex */
80 #define MACCFG2_FDX_MASK 0x00000001
81 #define MACCFG2_PAD_CRC 0x00000004
82 #define MACCFG2_CRC_EN 0x00000002
83 #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
84 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
85 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
86 #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
87 #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
88 #define MACCFG2_INTERFACE_MODE_MASK 0x00000300
90 #define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
91 MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
95 #define UCCE_MPD 0x80000000
96 #define UCCE_SCAR 0x40000000
97 #define UCCE_GRA 0x20000000
98 #define UCCE_CBPR 0x10000000
99 #define UCCE_BSY 0x08000000
100 #define UCCE_RXC 0x04000000
101 #define UCCE_TXC 0x02000000
102 #define UCCE_TXE 0x01000000
103 #define UCCE_TXB7 0x00800000
104 #define UCCE_TXB6 0x00400000
105 #define UCCE_TXB5 0x00200000
106 #define UCCE_TXB4 0x00100000
107 #define UCCE_TXB3 0x00080000
108 #define UCCE_TXB2 0x00040000
109 #define UCCE_TXB1 0x00020000
110 #define UCCE_TXB0 0x00010000
111 #define UCCE_RXB7 0x00008000
112 #define UCCE_RXB6 0x00004000
113 #define UCCE_RXB5 0x00002000
114 #define UCCE_RXB4 0x00001000
115 #define UCCE_RXB3 0x00000800
116 #define UCCE_RXB2 0x00000400
117 #define UCCE_RXB1 0x00000200
118 #define UCCE_RXB0 0x00000100
119 #define UCCE_RXF7 0x00000080
120 #define UCCE_RXF6 0x00000040
121 #define UCCE_RXF5 0x00000020
122 #define UCCE_RXF4 0x00000010
123 #define UCCE_RXF3 0x00000008
124 #define UCCE_RXF2 0x00000004
125 #define UCCE_RXF1 0x00000002
126 #define UCCE_RXF0 0x00000001
128 #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
129 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
130 #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
131 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
132 #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
133 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
134 #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
135 UCCE_RXC | UCCE_TXC | UCCE_TXE)
137 /* UEC TEMODR Register
139 #define TEMODER_SCHEDULER_ENABLE 0x2000
140 #define TEMODER_IP_CHECKSUM_GENERATE 0x0400
141 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
142 #define TEMODER_RMON_STATISTICS 0x0100
143 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15)
145 #define TEMODER_INIT_VALUE 0xc000
147 /* UEC REMODR Register
149 #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
150 #define REMODER_RX_EXTENDED_FEATURES 0x80000000
151 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 )
152 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
153 #define REMODER_RX_QOS_MODE_SHIFT (31-15)
154 #define REMODER_RMON_STATISTICS 0x00001000
155 #define REMODER_RX_EXTENDED_FILTERING 0x00000800
156 #define REMODER_NUM_OF_QUEUES_SHIFT (31-23)
157 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
158 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
159 #define REMODER_IP_CHECKSUM_CHECK 0x00000002
160 #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
162 #define REMODER_INIT_VALUE 0
164 /* BMRx - Bus Mode Register */
166 #define BMR_BO_BE 0x10
167 #define BMR_DTB_SECONDARY_BUS 0x02
168 #define BMR_BDB_SECONDARY_BUS 0x01
171 #define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE)
173 /* UEC UCCS (Ethernet Status Register)
175 #define UCCS_BPR 0x02
176 #define UCCS_PAU 0x02
177 #define UCCS_MPD 0x01
179 /* UEC MIIMCFG (MII Management Configuration Register)
181 #define MIIMCFG_RESET_MANAGEMENT 0x80000000
182 #define MIIMCFG_NO_PREAMBLE 0x00000010
183 #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
184 #define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f
185 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
186 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
187 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
188 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
189 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
190 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
191 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
193 #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \
194 MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
196 /* UEC MIIMCOM (MII Management Command Register)
198 #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
199 #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
201 /* UEC MIIMADD (MII Management Address Register)
203 #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
204 #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
206 /* UEC MIIMCON (MII Management Control Register)
208 #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
209 #define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
211 /* UEC MIIMIND (MII Management Indicator Register)
213 #define MIIMIND_NOT_VALID 0x00000004
214 #define MIIMIND_SCAN 0x00000002
215 #define MIIMIND_BUSY 0x00000001
217 /* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
219 #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
220 #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
222 /* UEC UESCR (Ethernet Statistics Control Register)
224 #define UESCR_AUTOZ 0x8000
225 #define UESCR_CLRCNT 0x4000
226 #define UESCR_MAXCOV_SHIFT (15 - 7)
227 #define UESCR_SCOV_SHIFT (15 - 15)
229 /****** Tx data struct collection ******/
230 /* Tx thread data, each Tx thread has one this struct.
232 typedef struct uec_thread_data_tx {
234 } __attribute__ ((packed)) uec_thread_data_tx_t;
236 /* Tx thread parameter, each Tx thread has one this struct.
238 typedef struct uec_thread_tx_pram {
240 } __attribute__ ((packed)) uec_thread_tx_pram_t;
242 /* Send queue queue-descriptor, each Tx queue has one this QD
244 typedef struct uec_send_queue_qd {
245 u32 bd_ring_base; /* pointer to BD ring base address */
247 u32 last_bd_completed_address; /* last entry in BD ring */
249 } __attribute__ ((packed)) uec_send_queue_qd_t;
251 /* Send queue memory region */
252 typedef struct uec_send_queue_mem_region {
253 uec_send_queue_qd_t sqqd[MAX_TX_QUEUES];
254 } __attribute__ ((packed)) uec_send_queue_mem_region_t;
258 typedef struct uec_scheduler {
259 u16 cpucount0; /* CPU packet counter */
260 u16 cpucount1; /* CPU packet counter */
261 u16 cecount0; /* QE packet counter */
262 u16 cecount1; /* QE packet counter */
263 u16 cpucount2; /* CPU packet counter */
264 u16 cpucount3; /* CPU packet counter */
265 u16 cecount2; /* QE packet counter */
266 u16 cecount3; /* QE packet counter */
267 u16 cpucount4; /* CPU packet counter */
268 u16 cpucount5; /* CPU packet counter */
269 u16 cecount4; /* QE packet counter */
270 u16 cecount5; /* QE packet counter */
271 u16 cpucount6; /* CPU packet counter */
272 u16 cpucount7; /* CPU packet counter */
273 u16 cecount6; /* QE packet counter */
274 u16 cecount7; /* QE packet counter */
275 u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
276 u32 rtsrshadow; /* temporary variable handled by QE */
277 u32 time; /* temporary variable handled by QE */
278 u32 ttl; /* temporary variable handled by QE */
279 u32 mblinterval; /* max burst length interval */
280 u16 nortsrbytetime; /* normalized value of byte time in tsr units */
283 u8 strictpriorityq; /* Strict Priority Mask register */
284 u8 txasap; /* Transmit ASAP register */
285 u8 extrabw; /* Extra BandWidth register */
286 u8 oldwfqmask; /* temporary variable handled by QE */
287 u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
288 u32 minw; /* temporary variable handled by QE */
290 } __attribute__ ((packed)) uec_scheduler_t;
292 /* Tx firmware counters
294 typedef struct uec_tx_firmware_statistics_pram {
295 u32 sicoltx; /* single collision */
296 u32 mulcoltx; /* multiple collision */
297 u32 latecoltxfr; /* late collision */
298 u32 frabortduecol; /* frames aborted due to tx collision */
299 u32 frlostinmactxer; /* frames lost due to internal MAC error tx */
300 u32 carriersenseertx; /* carrier sense error */
301 u32 frtxok; /* frames transmitted OK */
302 u32 txfrexcessivedefer;
303 u32 txpkts256; /* total packets(including bad) 256~511 B */
304 u32 txpkts512; /* total packets(including bad) 512~1023B */
305 u32 txpkts1024; /* total packets(including bad) 1024~1518B */
306 u32 txpktsjumbo; /* total packets(including bad) >1024 */
307 } __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
309 /* Tx global parameter table
311 typedef struct uec_tx_global_pram {
315 u32 schedulerbasepointer;
318 u8 iphoffset[MAX_IPH_OFFSET_ENTRY];
322 } __attribute__ ((packed)) uec_tx_global_pram_t;
325 /****** Rx data struct collection ******/
326 /* Rx thread data, each Rx thread has one this struct.
328 typedef struct uec_thread_data_rx {
330 } __attribute__ ((packed)) uec_thread_data_rx_t;
332 /* Rx thread parameter, each Rx thread has one this struct.
334 typedef struct uec_thread_rx_pram {
336 } __attribute__ ((packed)) uec_thread_rx_pram_t;
338 /* Rx firmware counters
340 typedef struct uec_rx_firmware_statistics_pram {
341 u32 frrxfcser; /* frames with crc error */
342 u32 fraligner; /* frames with alignment error */
343 u32 inrangelenrxer; /* in range length error */
344 u32 outrangelenrxer; /* out of range length error */
345 u32 frtoolong; /* frame too long */
347 u32 verylongevent; /* very long event */
348 u32 symbolerror; /* symbol error */
349 u32 dropbsy; /* drop because of BD not ready */
351 u32 mismatchdrop; /* drop because of MAC filtering */
352 u32 underpkts; /* total frames less than 64 octets */
353 u32 pkts256; /* total frames(including bad)256~511 B */
354 u32 pkts512; /* total frames(including bad)512~1023 B */
355 u32 pkts1024; /* total frames(including bad)1024~1518 B */
356 u32 pktsjumbo; /* total frames(including bad) >1024 B */
358 u32 pausefr; /* pause frames */
363 } __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
365 /* Rx interrupt coalescing entry, each Rx queue has one this entry.
367 typedef struct uec_rx_interrupt_coalescing_entry {
370 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
372 typedef struct uec_rx_interrupt_coalescing_table {
373 uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES];
374 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
376 /* RxBD queue entry, each Rx queue has one this entry.
378 typedef struct uec_rx_bd_queues_entry {
379 u32 bdbaseptr; /* BD base pointer */
380 u32 bdptr; /* BD pointer */
381 u32 externalbdbaseptr; /* external BD base pointer */
382 u32 externalbdptr; /* external BD pointer */
383 } __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
385 /* Rx global paramter table
387 typedef struct uec_rx_global_pram {
388 u32 remoder; /* ethernet mode reg. */
389 u32 rqptr; /* base pointer to the Rx Queues */
394 u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
395 u32 rxrmonbaseptr; /* Rx RMON statistics base */
397 u32 intcoalescingptr; /* Interrupt coalescing table pointer */
401 u16 mrblr; /* max receive buffer length reg. */
402 u32 rbdqptr; /* RxBD parameter table description */
403 u16 mflr; /* max frame length reg. */
404 u16 minflr; /* min frame length reg. */
405 u16 maxd1; /* max dma1 length reg. */
406 u16 maxd2; /* max dma2 length reg. */
407 u32 ecamptr; /* external CAM address */
408 u32 l2qt; /* VLAN priority mapping table. */
409 u32 l3qt[0x8]; /* IP priority mapping table. */
410 u16 vlantype; /* vlan type */
411 u16 vlantci; /* default vlan tci */
412 u8 addressfiltering[64];/* address filtering data structure */
413 u32 exfGlobalParam; /* extended filtering global parameters */
414 u8 res6[0x100-0xC4]; /* Initialize to zero */
415 } __attribute__ ((packed)) uec_rx_global_pram_t;
417 #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
420 /****** UEC common ******/
421 /* UCC statistics - hardware counters
423 typedef struct uec_hardware_statistics {
439 } __attribute__ ((packed)) uec_hardware_statistics_t;
441 /* InitEnet command parameter
443 typedef struct uec_init_cmd_pram {
450 u8 largestexternallookupkeysize;
452 u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
453 u8 res2[0x38 - 0x30];
454 u32 txglobal; /* tx global */
455 u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
457 } __attribute__ ((packed)) uec_init_cmd_pram_t;
459 #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
460 #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
462 #define ENET_INIT_PARAM_RISC_MASK 0x0000003f
463 #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
464 #define ENET_INIT_PARAM_SNUM_MASK 0xff000000
465 #define ENET_INIT_PARAM_SNUM_SHIFT 24
467 #define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06
468 #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30
469 #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff
470 #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
471 #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
473 /* structure representing 82xx Address Filtering Enet Address in PRAM
475 typedef struct uec_82xx_enet_address {
477 u16 h; /* address (MSB) */
479 u16 l; /* address (LSB) */
480 } __attribute__ ((packed)) uec_82xx_enet_address_t;
482 /* structure representing 82xx Address Filtering PRAM
484 typedef struct uec_82xx_address_filtering_pram {
485 u32 iaddr_h; /* individual address filter, high */
486 u32 iaddr_l; /* individual address filter, low */
487 u32 gaddr_h; /* group address filter, high */
488 u32 gaddr_l; /* group address filter, low */
489 uec_82xx_enet_address_t taddr;
490 uec_82xx_enet_address_t paddr[4];
492 } __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
496 typedef struct buffer_descriptor {
500 } __attribute__ ((packed)) qe_bd_t, *p_bd_t;
502 #define SIZEOFBD sizeof(qe_bd_t)
506 #define BD_WRAP 0x2000
507 #define BD_INT 0x1000
508 #define BD_LAST 0x0800
509 #define BD_CLEAN 0x3000
513 #define TxBD_READY 0x8000
514 #define TxBD_PADCRC 0x4000
515 #define TxBD_WRAP BD_WRAP
516 #define TxBD_INT BD_INT
517 #define TxBD_LAST BD_LAST
518 #define TxBD_TXCRC 0x0400
519 #define TxBD_DEF 0x0200
520 #define TxBD_PP 0x0100
521 #define TxBD_LC 0x0080
522 #define TxBD_RL 0x0040
523 #define TxBD_RC 0x003C
524 #define TxBD_UNDERRUN 0x0002
525 #define TxBD_TRUNC 0x0001
527 #define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC)
531 #define RxBD_EMPTY 0x8000
532 #define RxBD_OWNER 0x4000
533 #define RxBD_WRAP BD_WRAP
534 #define RxBD_INT BD_INT
535 #define RxBD_LAST BD_LAST
536 #define RxBD_FIRST 0x0400
537 #define RxBD_CMR 0x0200
538 #define RxBD_MISS 0x0100
539 #define RxBD_BCAST 0x0080
540 #define RxBD_MCAST 0x0040
541 #define RxBD_LG 0x0020
542 #define RxBD_NO 0x0010
543 #define RxBD_SHORT 0x0008
544 #define RxBD_CRCERR 0x0004
545 #define RxBD_OVERRUN 0x0002
546 #define RxBD_IPCH 0x0001
548 #define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \
549 RxBD_CRCERR | RxBD_OVERRUN)
553 #define BD_STATUS(_bd) (((p_bd_t)(_bd))->status)
554 #define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val)
555 #define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len)
556 #define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val)
557 #define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0)
558 #define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data)
559 #define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data))
560 #define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data))
561 #define BD_ADVANCE(_bd,_status,_base) \
562 (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
566 typedef struct uec_rx_prefetched_bds {
567 qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
568 } __attribute__ ((packed)) uec_rx_prefetched_bds_t;
572 #define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
573 #define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
574 #define UEC_THREAD_RX_PRAM_ALIGNMENT 128
575 #define UEC_THREAD_TX_PRAM_ALIGNMENT 64
576 #define UEC_THREAD_DATA_ALIGNMENT 256
577 #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
578 #define UEC_SCHEDULER_ALIGNMENT 4
579 #define UEC_TX_STATISTICS_ALIGNMENT 4
580 #define UEC_RX_STATISTICS_ALIGNMENT 4
581 #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4
582 #define UEC_RX_BD_QUEUES_ALIGNMENT 8
583 #define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128
584 #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4
585 #define UEC_RX_BD_RING_ALIGNMENT 32
586 #define UEC_TX_BD_RING_ALIGNMENT 32
587 #define UEC_MRBLR_ALIGNMENT 128
588 #define UEC_RX_BD_RING_SIZE_ALIGNMENT 4
589 #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
590 #define UEC_RX_DATA_BUF_ALIGNMENT 64
592 #define UEC_VLAN_PRIORITY_MAX 8
593 #define UEC_IP_PRIORITY_MAX 64
594 #define UEC_TX_VTAG_TABLE_ENTRY_MAX 8
595 #define UEC_RX_BD_RING_SIZE_MIN 8
596 #define UEC_TX_BD_RING_SIZE_MIN 2
600 typedef enum enet_speed {
601 ENET_SPEED_10BT, /* 10 Base T */
602 ENET_SPEED_100BT, /* 100 Base T */
603 ENET_SPEED_1000BT /* 1000 Base T */
606 /* Ethernet Address Type.
608 typedef enum enet_addr_type {
609 ENET_ADDR_TYPE_INDIVIDUAL,
610 ENET_ADDR_TYPE_GROUP,
611 ENET_ADDR_TYPE_BROADCAST
614 /* TBI / MII Set Register
616 typedef enum enet_tbi_mii_reg {
617 ENET_TBI_MII_CR = 0x00,
618 ENET_TBI_MII_SR = 0x01,
619 ENET_TBI_MII_ANA = 0x04,
620 ENET_TBI_MII_ANLPBPA = 0x05,
621 ENET_TBI_MII_ANEX = 0x06,
622 ENET_TBI_MII_ANNPT = 0x07,
623 ENET_TBI_MII_ANLPANP = 0x08,
624 ENET_TBI_MII_EXST = 0x0F,
625 ENET_TBI_MII_JD = 0x10,
626 ENET_TBI_MII_TBICON = 0x11
627 } enet_tbi_mii_reg_e;
629 /* TBI MDIO register bit fields*/
630 #define TBICON_CLK_SELECT 0x0020
631 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
632 #define TBIANA_SYMMETRIC_PAUSE 0x0080
633 #define TBIANA_HALF_DUPLEX 0x0040
634 #define TBIANA_FULL_DUPLEX 0x0020
635 #define TBICR_PHY_RESET 0x8000
636 #define TBICR_ANEG_ENABLE 0x1000
637 #define TBICR_RESTART_ANEG 0x0200
638 #define TBICR_FULL_DUPLEX 0x0100
639 #define TBICR_SPEED1_SET 0x0040
641 #define TBIANA_SETTINGS ( \
642 TBIANA_ASYMMETRIC_PAUSE \
643 | TBIANA_SYMMETRIC_PAUSE \
644 | TBIANA_FULL_DUPLEX \
647 #define TBICR_SETTINGS ( \
649 | TBICR_ANEG_ENABLE \
650 | TBICR_FULL_DUPLEX \
654 /* UEC number of threads
656 typedef enum uec_num_of_threads {
657 UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */
658 UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */
659 UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */
660 UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */
661 UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
662 } uec_num_of_threads_e;
664 /* UEC initialization info struct
666 #define STD_UEC_INFO(num) \
669 .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
670 .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
671 .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
672 .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
674 .num_threads_tx = UEC_NUM_OF_THREADS_1, \
675 .num_threads_rx = UEC_NUM_OF_THREADS_1, \
676 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
677 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
678 .tx_bd_ring_len = 16, \
679 .rx_bd_ring_len = 16, \
680 .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
681 .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
682 .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
685 typedef struct uec_info {
686 ucc_fast_info_t uf_info;
687 uec_num_of_threads_e num_threads_tx;
688 uec_num_of_threads_e num_threads_rx;
689 unsigned int risc_tx;
690 unsigned int risc_rx;
694 enum fsl_phy_enet_if enet_interface_type;
698 /* UEC driver initialized info
700 #define MAX_RXBUF_LEN 1536
701 #define MAX_FRAME_LEN 1518
702 #define MIN_FRAME_LEN 64
703 #define MAX_DMA1_LEN 1520
704 #define MAX_DMA2_LEN 1520
706 /* UEC driver private struct
708 typedef struct uec_private {
709 uec_info_t *uec_info;
710 ucc_fast_private_t *uccf;
711 struct eth_device *dev;
713 uec_mii_t *uec_mii_regs;
714 /* enet init command parameter */
715 uec_init_cmd_pram_t *p_init_enet_param;
716 u32 init_enet_param_offset;
717 /* Rx and Tx paramter */
718 uec_rx_global_pram_t *p_rx_glbl_pram;
719 u32 rx_glbl_pram_offset;
720 uec_tx_global_pram_t *p_tx_glbl_pram;
721 u32 tx_glbl_pram_offset;
722 uec_send_queue_mem_region_t *p_send_q_mem_reg;
723 u32 send_q_mem_reg_offset;
724 uec_thread_data_tx_t *p_thread_data_tx;
725 u32 thread_dat_tx_offset;
726 uec_thread_data_rx_t *p_thread_data_rx;
727 u32 thread_dat_rx_offset;
728 uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl;
729 u32 rx_bd_qs_tbl_offset;
732 u32 tx_bd_ring_offset;
734 u32 rx_bd_ring_offset;
737 volatile qe_bd_t *txBd;
738 volatile qe_bd_t *rxBd;
742 int grace_stopped_tx;
743 int grace_stopped_rx;
746 struct uec_mii_info *mii_info;
752 int uec_initialize(bd_t *bis, uec_info_t *uec_info);
753 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num);
754 int uec_standard_init(bd_t *bis);
755 #endif /* __UEC_H__ */