drivers/qe/uec.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
   4  *
   5  * Dave Liu <daveliu@freescale.com>
   6  * based on source code of Shlomi Gridish
   7  */
   8
   9 #ifndef __UEC_H__
  10 #define __UEC_H__
  11
  12 #include "uccf.h"
  13 #include <fsl_qe.h>
  14 #include <phy.h>
  15
  16 #define MAX_TX_THREADS                          8
  17 #define MAX_RX_THREADS                          8
  18 #define MAX_TX_QUEUES                           8
  19 #define MAX_RX_QUEUES                           8
  20 #define MAX_PREFETCHED_BDS                      4
  21 #define MAX_IPH_OFFSET_ENTRY                    8
  22 #define MAX_ENET_INIT_PARAM_ENTRIES_RX          9
  23 #define MAX_ENET_INIT_PARAM_ENTRIES_TX          8
  24
  25 /* UEC UPSMR (Protocol Specific Mode Register)
  26  */
  27 #define UPSMR_ECM       0x04000000 /* Enable CAM Miss               */
  28 #define UPSMR_HSE       0x02000000 /* Hardware Statistics Enable    */
  29 #define UPSMR_PRO       0x00400000 /* Promiscuous                   */
  30 #define UPSMR_CAP       0x00200000 /* CAM polarity                  */
  31 #define UPSMR_RSH       0x00100000 /* Receive Short Frames          */
  32 #define UPSMR_RPM       0x00080000 /* Reduced Pin Mode interfaces   */
  33 #define UPSMR_R10M      0x00040000 /* RGMII/RMII 10 Mode            */
  34 #define UPSMR_RLPB      0x00020000 /* RMII Loopback Mode            */
  35 #define UPSMR_TBIM      0x00010000 /* Ten-bit Interface Mode        */
  36 #define UPSMR_RMM       0x00001000 /* RMII/RGMII Mode               */
  37 #define UPSMR_CAM       0x00000400 /* CAM Address Matching          */
  38 #define UPSMR_BRO       0x00000200 /* Broadcast Address             */
  39 #define UPSMR_RES1      0x00002000 /* Reserved feild - must be 1    */
  40 #define UPSMR_SGMM      0x00000020 /* SGMII mode    */
  41
  42 #define UPSMR_INIT_VALUE        (UPSMR_HSE | UPSMR_RES1)
  43
  44 /* UEC MACCFG1 (MAC Configuration 1 Register)
  45  */
  46 #define MACCFG1_FLOW_RX                 0x00000020 /* Flow Control Rx */
  47 #define MACCFG1_FLOW_TX                 0x00000010 /* Flow Control Tx */
  48 #define MACCFG1_ENABLE_SYNCHED_RX       0x00000008 /* Enable Rx Sync  */
  49 #define MACCFG1_ENABLE_RX               0x00000004 /* Enable Rx       */
  50 #define MACCFG1_ENABLE_SYNCHED_TX       0x00000002 /* Enable Tx Sync  */
  51 #define MACCFG1_ENABLE_TX               0x00000001 /* Enable Tx       */
  52
  53 #define MACCFG1_INIT_VALUE              (0)
  54
  55 /* UEC MACCFG2 (MAC Configuration 2 Register)
  56  */
  57 #define MACCFG2_PREL                            0x00007000
  58 #define MACCFG2_PREL_SHIFT                      (31 - 19)
  59 #define MACCFG2_PREL_MASK                       0x0000f000
  60 #define MACCFG2_SRP                             0x00000080
  61 #define MACCFG2_STP                             0x00000040
  62 #define MACCFG2_RESERVED_1                      0x00000020 /* must be set  */
  63 #define MACCFG2_LC                              0x00000010 /* Length Check */
  64 #define MACCFG2_MPE                             0x00000008
  65 #define MACCFG2_FDX                             0x00000001 /* Full Duplex  */
  66 #define MACCFG2_FDX_MASK                        0x00000001
  67 #define MACCFG2_PAD_CRC                         0x00000004
  68 #define MACCFG2_CRC_EN                          0x00000002
  69 #define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000
  70 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002
  71 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
  72 #define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100
  73 #define MACCFG2_INTERFACE_MODE_BYTE             0x00000200
  74 #define MACCFG2_INTERFACE_MODE_MASK             0x00000300
  75
  76 #define MACCFG2_INIT_VALUE      (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
  77                                  MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
  78
  79 /* UEC Event Register
  80 */
  81 #define UCCE_MPD                                0x80000000
  82 #define UCCE_SCAR                               0x40000000
  83 #define UCCE_GRA                                0x20000000
  84 #define UCCE_CBPR                               0x10000000
  85 #define UCCE_BSY                                0x08000000
  86 #define UCCE_RXC                                0x04000000
  87 #define UCCE_TXC                                0x02000000
  88 #define UCCE_TXE                                0x01000000
  89 #define UCCE_TXB7                               0x00800000
  90 #define UCCE_TXB6                               0x00400000
  91 #define UCCE_TXB5                               0x00200000
  92 #define UCCE_TXB4                               0x00100000
  93 #define UCCE_TXB3                               0x00080000
  94 #define UCCE_TXB2                               0x00040000
  95 #define UCCE_TXB1                               0x00020000
  96 #define UCCE_TXB0                               0x00010000
  97 #define UCCE_RXB7                               0x00008000
  98 #define UCCE_RXB6                               0x00004000
  99 #define UCCE_RXB5                               0x00002000
 100 #define UCCE_RXB4                               0x00001000
 101 #define UCCE_RXB3                               0x00000800
 102 #define UCCE_RXB2                               0x00000400
 103 #define UCCE_RXB1                               0x00000200
 104 #define UCCE_RXB0                               0x00000100
 105 #define UCCE_RXF7                               0x00000080
 106 #define UCCE_RXF6                               0x00000040
 107 #define UCCE_RXF5                               0x00000020
 108 #define UCCE_RXF4                               0x00000010
 109 #define UCCE_RXF3                               0x00000008
 110 #define UCCE_RXF2                               0x00000004
 111 #define UCCE_RXF1                               0x00000002
 112 #define UCCE_RXF0                               0x00000001
 113
 114 #define UCCE_TXB        (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
 115                          UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
 116 #define UCCE_RXB        (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
 117                          UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
 118 #define UCCE_RXF        (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
 119                          UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
 120 #define UCCE_OTHER      (UCCE_SCAR | UCCE_GRA  | UCCE_CBPR | UCCE_BSY  | \
 121                          UCCE_RXC  | UCCE_TXC  | UCCE_TXE)
 122
 123 /* UEC TEMODR Register
 124 */
 125 #define TEMODER_SCHEDULER_ENABLE                0x2000
 126 #define TEMODER_IP_CHECKSUM_GENERATE            0x0400
 127 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200
 128 #define TEMODER_RMON_STATISTICS                 0x0100
 129 #define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15)
 130
 131 #define TEMODER_INIT_VALUE                      0xc000
 132
 133 /* UEC REMODR Register
 134 */
 135 #define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000
 136 #define REMODER_RX_EXTENDED_FEATURES            0x80000000
 137 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 )
 138 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
 139 #define REMODER_RX_QOS_MODE_SHIFT               (31-15)
 140 #define REMODER_RMON_STATISTICS                 0x00001000
 141 #define REMODER_RX_EXTENDED_FILTERING           0x00000800
 142 #define REMODER_NUM_OF_QUEUES_SHIFT             (31-23)
 143 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008
 144 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004
 145 #define REMODER_IP_CHECKSUM_CHECK               0x00000002
 146 #define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001
 147
 148 #define REMODER_INIT_VALUE                      0
 149
 150 /* BMRx - Bus Mode Register */
 151 #define BMR_GLB                                 0x20
 152 #define BMR_BO_BE                               0x10
 153 #define BMR_DTB_SECONDARY_BUS                   0x02
 154 #define BMR_BDB_SECONDARY_BUS                   0x01
 155
 156 #define BMR_SHIFT                               24
 157 #define BMR_INIT_VALUE                          (BMR_GLB | BMR_BO_BE)
 158
 159 /* UEC UCCS (Ethernet Status Register)
 160  */
 161 #define UCCS_BPR                                0x02
 162 #define UCCS_PAU                                0x02
 163 #define UCCS_MPD                                0x01
 164
 165 /* UEC MIIMCFG (MII Management Configuration Register)
 166  */
 167 #define MIIMCFG_RESET_MANAGEMENT                0x80000000
 168 #define MIIMCFG_NO_PREAMBLE                     0x00000010
 169 #define MIIMCFG_CLOCK_DIVIDE_SHIFT              (31 - 31)
 170 #define MIIMCFG_CLOCK_DIVIDE_MASK               0x0000000f
 171 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4    0x00000001
 172 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6    0x00000002
 173 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8    0x00000003
 174 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10   0x00000004
 175 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14   0x00000005
 176 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20   0x00000006
 177 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28   0x00000007
 178
 179 #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE       \
 180         MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
 181
 182 /* UEC MIIMCOM (MII Management Command Register)
 183  */
 184 #define MIIMCOM_SCAN_CYCLE                      0x00000002 /* Scan cycle */
 185 #define MIIMCOM_READ_CYCLE                      0x00000001 /* Read cycle */
 186
 187 /* UEC MIIMADD (MII Management Address Register)
 188  */
 189 #define MIIMADD_PHY_ADDRESS_SHIFT               (31 - 23)
 190 #define MIIMADD_PHY_REGISTER_SHIFT              (31 - 31)
 191
 192 /* UEC MIIMCON (MII Management Control Register)
 193  */
 194 #define MIIMCON_PHY_CONTROL_SHIFT               (31 - 31)
 195 #define MIIMCON_PHY_STATUS_SHIFT                (31 - 31)
 196
 197 /* UEC MIIMIND (MII Management Indicator Register)
 198  */
 199 #define MIIMIND_NOT_VALID                       0x00000004
 200 #define MIIMIND_SCAN                            0x00000002
 201 #define MIIMIND_BUSY                            0x00000001
 202
 203 /* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
 204  */
 205 #define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)
 206 #define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f
 207
 208 /* UEC UESCR (Ethernet Statistics Control Register)
 209  */
 210 #define UESCR_AUTOZ                             0x8000
 211 #define UESCR_CLRCNT                            0x4000
 212 #define UESCR_MAXCOV_SHIFT                      (15 -  7)
 213 #define UESCR_SCOV_SHIFT                        (15 - 15)
 214
 215 /****** Tx data struct collection ******/
 216 /* Tx thread data, each Tx thread has one this struct.
 217 */
 218 typedef struct uec_thread_data_tx {
 219         u8   res0[136];
 220 } __attribute__ ((packed)) uec_thread_data_tx_t;
 221
 222 /* Tx thread parameter, each Tx thread has one this struct.
 223 */
 224 typedef struct uec_thread_tx_pram {
 225         u8   res0[64];
 226 } __attribute__ ((packed)) uec_thread_tx_pram_t;
 227
 228 /* Send queue queue-descriptor, each Tx queue has one this QD
 229 */
 230 typedef struct uec_send_queue_qd {
 231         u32    bd_ring_base; /* pointer to BD ring base address */
 232         u8     res0[0x8];
 233         u32    last_bd_completed_address; /* last entry in BD ring */
 234         u8     res1[0x30];
 235 } __attribute__ ((packed)) uec_send_queue_qd_t;
 236
 237 /* Send queue memory region */
 238 typedef struct uec_send_queue_mem_region {
 239         uec_send_queue_qd_t   sqqd[MAX_TX_QUEUES];
 240 } __attribute__ ((packed)) uec_send_queue_mem_region_t;
 241
 242 /* Scheduler struct
 243 */
 244 typedef struct uec_scheduler {
 245         u16  cpucount0;        /* CPU packet counter */
 246         u16  cpucount1;        /* CPU packet counter */
 247         u16  cecount0;         /* QE  packet counter */
 248         u16  cecount1;         /* QE  packet counter */
 249         u16  cpucount2;        /* CPU packet counter */
 250         u16  cpucount3;        /* CPU packet counter */
 251         u16  cecount2;         /* QE  packet counter */
 252         u16  cecount3;         /* QE  packet counter */
 253         u16  cpucount4;        /* CPU packet counter */
 254         u16  cpucount5;        /* CPU packet counter */
 255         u16  cecount4;         /* QE  packet counter */
 256         u16  cecount5;         /* QE  packet counter */
 257         u16  cpucount6;        /* CPU packet counter */
 258         u16  cpucount7;        /* CPU packet counter */
 259         u16  cecount6;         /* QE  packet counter */
 260         u16  cecount7;         /* QE  packet counter */
 261         u32  weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
 262         u32  rtsrshadow;       /* temporary variable handled by QE */
 263         u32  time;             /* temporary variable handled by QE */
 264         u32  ttl;              /* temporary variable handled by QE */
 265         u32  mblinterval;      /* max burst length interval        */
 266         u16  nortsrbytetime;   /* normalized value of byte time in tsr units */
 267         u8   fracsiz;
 268         u8   res0[1];
 269         u8   strictpriorityq;  /* Strict Priority Mask register */
 270         u8   txasap;           /* Transmit ASAP register        */
 271         u8   extrabw;          /* Extra BandWidth register      */
 272         u8   oldwfqmask;       /* temporary variable handled by QE */
 273         u8   weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
 274         u32  minw;             /* temporary variable handled by QE */
 275         u8   res1[0x70-0x64];
 276 } __attribute__ ((packed)) uec_scheduler_t;
 277
 278 /* Tx firmware counters
 279 */
 280 typedef struct uec_tx_firmware_statistics_pram {
 281         u32  sicoltx;            /* single collision */
 282         u32  mulcoltx;           /* multiple collision */
 283         u32  latecoltxfr;        /* late collision */
 284         u32  frabortduecol;      /* frames aborted due to tx collision */
 285         u32  frlostinmactxer;    /* frames lost due to internal MAC error tx */
 286         u32  carriersenseertx;   /* carrier sense error */
 287         u32  frtxok;             /* frames transmitted OK */
 288         u32  txfrexcessivedefer;
 289         u32  txpkts256;          /* total packets(including bad) 256~511 B */
 290         u32  txpkts512;          /* total packets(including bad) 512~1023B */
 291         u32  txpkts1024;         /* total packets(including bad) 1024~1518B */
 292         u32  txpktsjumbo;        /* total packets(including bad)  >1024 */
 293 } __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
 294
 295 /* Tx global parameter table
 296 */
 297 typedef struct uec_tx_global_pram {
 298         u16  temoder;
 299         u8   res0[0x38-0x02];
 300         u32  sqptr;
 301         u32  schedulerbasepointer;
 302         u32  txrmonbaseptr;
 303         u32  tstate;
 304         u8   iphoffset[MAX_IPH_OFFSET_ENTRY];
 305         u32  vtagtable[0x8];
 306         u32  tqptr;
 307         u8   res2[0x80-0x74];
 308 } __attribute__ ((packed)) uec_tx_global_pram_t;
 309
 310
 311 /****** Rx data struct collection ******/
 312 /* Rx thread data, each Rx thread has one this struct.
 313 */
 314 typedef struct uec_thread_data_rx {
 315         u8   res0[40];
 316 } __attribute__ ((packed)) uec_thread_data_rx_t;
 317
 318 /* Rx thread parameter, each Rx thread has one this struct.
 319 */
 320 typedef struct uec_thread_rx_pram {
 321         u8   res0[128];
 322 } __attribute__ ((packed)) uec_thread_rx_pram_t;
 323
 324 /* Rx firmware counters
 325 */
 326 typedef struct uec_rx_firmware_statistics_pram {
 327         u32   frrxfcser;         /* frames with crc error */
 328         u32   fraligner;         /* frames with alignment error */
 329         u32   inrangelenrxer;    /* in range length error */
 330         u32   outrangelenrxer;   /* out of range length error */
 331         u32   frtoolong;         /* frame too long */
 332         u32   runt;              /* runt */
 333         u32   verylongevent;     /* very long event */
 334         u32   symbolerror;       /* symbol error */
 335         u32   dropbsy;           /* drop because of BD not ready */
 336         u8    res0[0x8];
 337         u32   mismatchdrop;      /* drop because of MAC filtering */
 338         u32   underpkts;         /* total frames less than 64 octets */
 339         u32   pkts256;           /* total frames(including bad)256~511 B */
 340         u32   pkts512;           /* total frames(including bad)512~1023 B */
 341         u32   pkts1024;          /* total frames(including bad)1024~1518 B */
 342         u32   pktsjumbo;         /* total frames(including bad) >1024 B */
 343         u32   frlossinmacer;
 344         u32   pausefr;           /* pause frames */
 345         u8    res1[0x4];
 346         u32   removevlan;
 347         u32   replacevlan;
 348         u32   insertvlan;
 349 } __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
 350
 351 /* Rx interrupt coalescing entry, each Rx queue has one this entry.
 352 */
 353 typedef struct uec_rx_interrupt_coalescing_entry {
 354         u32   maxvalue;
 355         u32   counter;
 356 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
 357
 358 typedef struct uec_rx_interrupt_coalescing_table {
 359         uec_rx_interrupt_coalescing_entry_t   entry[MAX_RX_QUEUES];
 360 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
 361
 362 /* RxBD queue entry, each Rx queue has one this entry.
 363 */
 364 typedef struct uec_rx_bd_queues_entry {
 365         u32   bdbaseptr;         /* BD base pointer          */
 366         u32   bdptr;             /* BD pointer               */
 367         u32   externalbdbaseptr; /* external BD base pointer */
 368         u32   externalbdptr;     /* external BD pointer      */
 369 } __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
 370
 371 /* Rx global paramter table
 372 */
 373 typedef struct uec_rx_global_pram {
 374         u32  remoder;             /* ethernet mode reg. */
 375         u32  rqptr;               /* base pointer to the Rx Queues */
 376         u32  res0[0x1];
 377         u8   res1[0x20-0xC];
 378         u16  typeorlen;
 379         u8   res2[0x1];
 380         u8   rxgstpack;           /* ack on GRACEFUL STOP RX command */
 381         u32  rxrmonbaseptr;       /* Rx RMON statistics base */
 382         u8   res3[0x30-0x28];
 383         u32  intcoalescingptr;    /* Interrupt coalescing table pointer */
 384         u8   res4[0x36-0x34];
 385         u8   rstate;
 386         u8   res5[0x46-0x37];
 387         u16  mrblr;               /* max receive buffer length reg. */
 388         u32  rbdqptr;             /* RxBD parameter table description */
 389         u16  mflr;                /* max frame length reg. */
 390         u16  minflr;              /* min frame length reg. */
 391         u16  maxd1;               /* max dma1 length reg. */
 392         u16  maxd2;               /* max dma2 length reg. */
 393         u32  ecamptr;             /* external CAM address */
 394         u32  l2qt;                /* VLAN priority mapping table. */
 395         u32  l3qt[0x8];           /* IP   priority mapping table. */
 396         u16  vlantype;            /* vlan type */
 397         u16  vlantci;             /* default vlan tci */
 398         u8   addressfiltering[64];/* address filtering data structure */
 399         u32  exfGlobalParam;      /* extended filtering global parameters */
 400         u8   res6[0x100-0xC4];    /* Initialize to zero */
 401 } __attribute__ ((packed)) uec_rx_global_pram_t;
 402
 403 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
 404
 405
 406 /****** UEC common ******/
 407 /* UCC statistics - hardware counters
 408 */
 409 typedef struct uec_hardware_statistics {
 410         u32 tx64;
 411         u32 tx127;
 412         u32 tx255;
 413         u32 rx64;
 414         u32 rx127;
 415         u32 rx255;
 416         u32 txok;
 417         u16 txcf;
 418         u32 tmca;
 419         u32 tbca;
 420         u32 rxfok;
 421         u32 rxbok;
 422         u32 rbyt;
 423         u32 rmca;
 424         u32 rbca;
 425 } __attribute__ ((packed)) uec_hardware_statistics_t;
 426
 427 /* InitEnet command parameter
 428 */
 429 typedef struct uec_init_cmd_pram {
 430         u8   resinit0;
 431         u8   resinit1;
 432         u8   resinit2;
 433         u8   resinit3;
 434         u16  resinit4;
 435         u8   res1[0x1];
 436         u8   largestexternallookupkeysize;
 437         u32  rgftgfrxglobal;
 438         u32  rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
 439         u8   res2[0x38 - 0x30];
 440         u32  txglobal;                             /* tx global  */
 441         u32  txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
 442         u8   res3[0x1];
 443 } __attribute__ ((packed)) uec_init_cmd_pram_t;
 444
 445 #define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
 446 #define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
 447
 448 #define ENET_INIT_PARAM_RISC_MASK               0x0000003f
 449 #define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
 450 #define ENET_INIT_PARAM_SNUM_MASK               0xff000000
 451 #define ENET_INIT_PARAM_SNUM_SHIFT              24
 452
 453 #define ENET_INIT_PARAM_MAGIC_RES_INIT0         0x06
 454 #define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x30
 455 #define ENET_INIT_PARAM_MAGIC_RES_INIT2         0xff
 456 #define ENET_INIT_PARAM_MAGIC_RES_INIT3         0x00
 457 #define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x0400
 458
 459 /* structure representing 82xx Address Filtering Enet Address in PRAM
 460 */
 461 typedef struct uec_82xx_enet_address {
 462         u8   res1[0x2];
 463         u16  h;       /* address (MSB) */
 464         u16  m;       /* address       */
 465         u16  l;       /* address (LSB) */
 466 } __attribute__ ((packed)) uec_82xx_enet_address_t;
 467
 468 /* structure representing 82xx Address Filtering PRAM
 469 */
 470 typedef struct uec_82xx_address_filtering_pram {
 471         u32  iaddr_h;        /* individual address filter, high */
 472         u32  iaddr_l;        /* individual address filter, low  */
 473         u32  gaddr_h;        /* group address filter, high      */
 474         u32  gaddr_l;        /* group address filter, low       */
 475         uec_82xx_enet_address_t    taddr;
 476         uec_82xx_enet_address_t    paddr[4];
 477         u8                         res0[0x40-0x38];
 478 } __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
 479
 480 /* Buffer Descriptor
 481 */
 482 typedef struct buffer_descriptor {
 483         u16 status;
 484         u16 len;
 485         u32 data;
 486 } __attribute__ ((packed)) qe_bd_t, *p_bd_t;
 487
 488 #define SIZEOFBD                sizeof(qe_bd_t)
 489
 490 /* Common BD flags
 491 */
 492 #define BD_WRAP                 0x2000
 493 #define BD_INT                  0x1000
 494 #define BD_LAST                 0x0800
 495 #define BD_CLEAN                0x3000
 496
 497 /* TxBD status flags
 498 */
 499 #define TxBD_READY              0x8000
 500 #define TxBD_PADCRC             0x4000
 501 #define TxBD_WRAP               BD_WRAP
 502 #define TxBD_INT                BD_INT
 503 #define TxBD_LAST               BD_LAST
 504 #define TxBD_TXCRC              0x0400
 505 #define TxBD_DEF                0x0200
 506 #define TxBD_PP                 0x0100
 507 #define TxBD_LC                 0x0080
 508 #define TxBD_RL                 0x0040
 509 #define TxBD_RC                 0x003C
 510 #define TxBD_UNDERRUN           0x0002
 511 #define TxBD_TRUNC              0x0001
 512
 513 #define TxBD_ERROR              (TxBD_UNDERRUN | TxBD_TRUNC)
 514
 515 /* RxBD status flags
 516 */
 517 #define RxBD_EMPTY              0x8000
 518 #define RxBD_OWNER              0x4000
 519 #define RxBD_WRAP               BD_WRAP
 520 #define RxBD_INT                BD_INT
 521 #define RxBD_LAST               BD_LAST
 522 #define RxBD_FIRST              0x0400
 523 #define RxBD_CMR                0x0200
 524 #define RxBD_MISS               0x0100
 525 #define RxBD_BCAST              0x0080
 526 #define RxBD_MCAST              0x0040
 527 #define RxBD_LG                 0x0020
 528 #define RxBD_NO                 0x0010
 529 #define RxBD_SHORT              0x0008
 530 #define RxBD_CRCERR             0x0004
 531 #define RxBD_OVERRUN            0x0002
 532 #define RxBD_IPCH               0x0001
 533
 534 #define RxBD_ERROR              (RxBD_LG | RxBD_NO | RxBD_SHORT | \
 535                                  RxBD_CRCERR | RxBD_OVERRUN)
 536
 537 /* BD access macros
 538 */
 539 #define BD_STATUS(_bd)                  (((p_bd_t)(_bd))->status)
 540 #define BD_STATUS_SET(_bd, _val)        (((p_bd_t)(_bd))->status = _val)
 541 #define BD_LENGTH(_bd)                  (((p_bd_t)(_bd))->len)
 542 #define BD_LENGTH_SET(_bd, _val)        (((p_bd_t)(_bd))->len = _val)
 543 #define BD_DATA_CLEAR(_bd)              (((p_bd_t)(_bd))->data = 0)
 544 #define BD_IS_DATA(_bd)                 (((p_bd_t)(_bd))->data)
 545 #define BD_DATA(_bd)                    ((u8 *)(((p_bd_t)(_bd))->data))
 546 #define BD_DATA_SET(_bd, _data)         (((p_bd_t)(_bd))->data = (u32)(_data))
 547 #define BD_ADVANCE(_bd,_status,_base)   \
 548         (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
 549
 550 /* Rx Prefetched BDs
 551 */
 552 typedef struct uec_rx_prefetched_bds {
 553     qe_bd_t   bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
 554 } __attribute__ ((packed)) uec_rx_prefetched_bds_t;
 555
 556 /* Alignments
 557  */
 558 #define UEC_RX_GLOBAL_PRAM_ALIGNMENT                            64
 559 #define UEC_TX_GLOBAL_PRAM_ALIGNMENT                            64
 560 #define UEC_THREAD_RX_PRAM_ALIGNMENT                            128
 561 #define UEC_THREAD_TX_PRAM_ALIGNMENT                            64
 562 #define UEC_THREAD_DATA_ALIGNMENT                               256
 563 #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT               32
 564 #define UEC_SCHEDULER_ALIGNMENT                                 4
 565 #define UEC_TX_STATISTICS_ALIGNMENT                             4
 566 #define UEC_RX_STATISTICS_ALIGNMENT                             4
 567 #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT                   4
 568 #define UEC_RX_BD_QUEUES_ALIGNMENT                              8
 569 #define UEC_RX_PREFETCHED_BDS_ALIGNMENT                         128
 570 #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT   4
 571 #define UEC_RX_BD_RING_ALIGNMENT                                32
 572 #define UEC_TX_BD_RING_ALIGNMENT                                32
 573 #define UEC_MRBLR_ALIGNMENT                                     128
 574 #define UEC_RX_BD_RING_SIZE_ALIGNMENT                           4
 575 #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT                    32
 576 #define UEC_RX_DATA_BUF_ALIGNMENT                               64
 577
 578 #define UEC_VLAN_PRIORITY_MAX                                   8
 579 #define UEC_IP_PRIORITY_MAX                                     64
 580 #define UEC_TX_VTAG_TABLE_ENTRY_MAX                             8
 581 #define UEC_RX_BD_RING_SIZE_MIN                                 8
 582 #define UEC_TX_BD_RING_SIZE_MIN                                 2
 583
 584 /* Ethernet speed
 585 */
 586 typedef enum enet_speed {
 587         ENET_SPEED_10BT,   /* 10 Base T */
 588         ENET_SPEED_100BT,  /* 100 Base T */
 589         ENET_SPEED_1000BT  /* 1000 Base T */
 590 } enet_speed_e;
 591
 592 /* Ethernet Address Type.
 593 */
 594 typedef enum enet_addr_type {
 595         ENET_ADDR_TYPE_INDIVIDUAL,
 596         ENET_ADDR_TYPE_GROUP,
 597         ENET_ADDR_TYPE_BROADCAST
 598 } enet_addr_type_e;
 599
 600 /* TBI / MII Set Register
 601 */
 602 typedef enum enet_tbi_mii_reg {
 603         ENET_TBI_MII_CR        = 0x00,
 604         ENET_TBI_MII_SR        = 0x01,
 605         ENET_TBI_MII_ANA       = 0x04,
 606         ENET_TBI_MII_ANLPBPA   = 0x05,
 607         ENET_TBI_MII_ANEX      = 0x06,
 608         ENET_TBI_MII_ANNPT     = 0x07,
 609         ENET_TBI_MII_ANLPANP   = 0x08,
 610         ENET_TBI_MII_EXST      = 0x0F,
 611         ENET_TBI_MII_JD        = 0x10,
 612         ENET_TBI_MII_TBICON    = 0x11
 613 } enet_tbi_mii_reg_e;
 614
 615 /* TBI MDIO register bit fields*/
 616 #define TBICON_CLK_SELECT       0x0020
 617 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
 618 #define TBIANA_SYMMETRIC_PAUSE  0x0080
 619 #define TBIANA_HALF_DUPLEX      0x0040
 620 #define TBIANA_FULL_DUPLEX      0x0020
 621 #define TBICR_PHY_RESET         0x8000
 622 #define TBICR_ANEG_ENABLE       0x1000
 623 #define TBICR_RESTART_ANEG      0x0200
 624 #define TBICR_FULL_DUPLEX       0x0100
 625 #define TBICR_SPEED1_SET        0x0040
 626
 627 #define TBIANA_SETTINGS ( \
 628                 TBIANA_ASYMMETRIC_PAUSE \
 629                 | TBIANA_SYMMETRIC_PAUSE \
 630                 | TBIANA_FULL_DUPLEX \
 631                 )
 632
 633 #define TBICR_SETTINGS ( \
 634                 TBICR_PHY_RESET \
 635                 | TBICR_ANEG_ENABLE \
 636                 | TBICR_FULL_DUPLEX \
 637                 | TBICR_SPEED1_SET \
 638                 )
 639
 640 /* UEC number of threads
 641 */
 642 typedef enum uec_num_of_threads {
 643         UEC_NUM_OF_THREADS_1  = 0x1,  /* 1 */
 644         UEC_NUM_OF_THREADS_2  = 0x2,  /* 2 */
 645         UEC_NUM_OF_THREADS_4  = 0x0,  /* 4 */
 646         UEC_NUM_OF_THREADS_6  = 0x3,  /* 6 */
 647         UEC_NUM_OF_THREADS_8  = 0x4   /* 8 */
 648 } uec_num_of_threads_e;
 649
 650 /* UEC initialization info struct
 651 */
 652 #define STD_UEC_INFO(num) \
 653 {                       \
 654         .uf_info                = {     \
 655                 .ucc_num        = CONFIG_SYS_UEC##num##_UCC_NUM,\
 656                 .rx_clock       = CONFIG_SYS_UEC##num##_RX_CLK, \
 657                 .tx_clock       = CONFIG_SYS_UEC##num##_TX_CLK, \
 658                 .eth_type       = CONFIG_SYS_UEC##num##_ETH_TYPE,\
 659         },      \
 660         .num_threads_tx         = UEC_NUM_OF_THREADS_1, \
 661         .num_threads_rx         = UEC_NUM_OF_THREADS_1, \
 662         .risc_tx                = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
 663         .risc_rx                = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
 664         .tx_bd_ring_len         = 16,   \
 665         .rx_bd_ring_len         = 16,   \
 666         .phy_address            = CONFIG_SYS_UEC##num##_PHY_ADDR, \
 667         .enet_interface_type    = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
 668         .speed                  = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
 669 }
 670
 671 typedef struct uec_info {
 672         ucc_fast_info_t                 uf_info;
 673         uec_num_of_threads_e            num_threads_tx;
 674         uec_num_of_threads_e            num_threads_rx;
 675         unsigned int                    risc_tx;
 676         unsigned int                    risc_rx;
 677         u16                             rx_bd_ring_len;
 678         u16                             tx_bd_ring_len;
 679         u8                              phy_address;
 680         phy_interface_t                 enet_interface_type;
 681         int                             speed;
 682 } uec_info_t;
 683
 684 /* UEC driver initialized info
 685 */
 686 #define MAX_RXBUF_LEN                   1536
 687 #define MAX_FRAME_LEN                   1518
 688 #define MIN_FRAME_LEN                   64
 689 #define MAX_DMA1_LEN                    1520
 690 #define MAX_DMA2_LEN                    1520
 691
 692 /* UEC driver private struct
 693 */
 694 typedef struct uec_private {
 695         uec_info_t                      *uec_info;
 696         ucc_fast_private_t              *uccf;
 697         struct eth_device               *dev;
 698         uec_t                           *uec_regs;
 699         uec_mii_t                       *uec_mii_regs;
 700         /* enet init command parameter */
 701         uec_init_cmd_pram_t             *p_init_enet_param;
 702         u32                             init_enet_param_offset;
 703         /* Rx and Tx paramter */
 704         uec_rx_global_pram_t            *p_rx_glbl_pram;
 705         u32                             rx_glbl_pram_offset;
 706         uec_tx_global_pram_t            *p_tx_glbl_pram;
 707         u32                             tx_glbl_pram_offset;
 708         uec_send_queue_mem_region_t     *p_send_q_mem_reg;
 709         u32                             send_q_mem_reg_offset;
 710         uec_thread_data_tx_t            *p_thread_data_tx;
 711         u32                             thread_dat_tx_offset;
 712         uec_thread_data_rx_t            *p_thread_data_rx;
 713         u32                             thread_dat_rx_offset;
 714         uec_rx_bd_queues_entry_t        *p_rx_bd_qs_tbl;
 715         u32                             rx_bd_qs_tbl_offset;
 716         /* BDs specific */
 717         u8                              *p_tx_bd_ring;
 718         u32                             tx_bd_ring_offset;
 719         u8                              *p_rx_bd_ring;
 720         u32                             rx_bd_ring_offset;
 721         u8                              *p_rx_buf;
 722         u32                             rx_buf_offset;
 723         volatile qe_bd_t                *txBd;
 724         volatile qe_bd_t                *rxBd;
 725         /* Status */
 726         int                             mac_tx_enabled;
 727         int                             mac_rx_enabled;
 728         int                             grace_stopped_tx;
 729         int                             grace_stopped_rx;
 730         int                             the_first_run;
 731         /* PHY specific */
 732         struct uec_mii_info             *mii_info;
 733         int                             oldspeed;
 734         int                             oldduplex;
 735         int                             oldlink;
 736 } uec_private_t;
 737
 738 int uec_initialize(bd_t *bis, uec_info_t *uec_info);
 739 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num);
 740 int uec_standard_init(bd_t *bis);
 741 #endif /* __UEC_H__ */