drivers/qe/uec.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include "common.h"
  23 #include "net.h"
  24 #include "malloc.h"
  25 #include "asm/errno.h"
  26 #include "asm/io.h"
  27 #include "asm/immap_qe.h"
  28 #include "qe.h"
  29 #include "uccf.h"
  30 #include "uec.h"
  31 #include "uec_phy.h"
  32
  33 #if defined(CONFIG_QE)
  34
  35 #ifdef CONFIG_UEC_ETH1
  36 static uec_info_t eth1_uec_info = {
  37         .uf_info                = {
  38                 .ucc_num        = CFG_UEC1_UCC_NUM,
  39                 .rx_clock       = CFG_UEC1_RX_CLK,
  40                 .tx_clock       = CFG_UEC1_TX_CLK,
  41                 .eth_type       = CFG_UEC1_ETH_TYPE,
  42         },
  43 #if (CFG_UEC1_ETH_TYPE == FAST_ETH)
  44         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  45         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  46 #else
  47         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  48         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  49 #endif
  50         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  51         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  52         .tx_bd_ring_len         = 16,
  53         .rx_bd_ring_len         = 16,
  54         .phy_address            = CFG_UEC1_PHY_ADDR,
  55         .enet_interface         = CFG_UEC1_INTERFACE_MODE,
  56 };
  57 #endif
  58 #ifdef CONFIG_UEC_ETH2
  59 static uec_info_t eth2_uec_info = {
  60         .uf_info                = {
  61                 .ucc_num        = CFG_UEC2_UCC_NUM,
  62                 .rx_clock       = CFG_UEC2_RX_CLK,
  63                 .tx_clock       = CFG_UEC2_TX_CLK,
  64                 .eth_type       = CFG_UEC2_ETH_TYPE,
  65         },
  66 #if (CFG_UEC2_ETH_TYPE == FAST_ETH)
  67         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  68         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  69 #else
  70         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  71         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  72 #endif
  73         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  74         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  75         .tx_bd_ring_len         = 16,
  76         .rx_bd_ring_len         = 16,
  77         .phy_address            = CFG_UEC2_PHY_ADDR,
  78         .enet_interface         = CFG_UEC2_INTERFACE_MODE,
  79 };
  80 #endif
  81 #ifdef CONFIG_UEC_ETH3
  82 static uec_info_t eth3_uec_info = {
  83         .uf_info                = {
  84                 .ucc_num        = CFG_UEC3_UCC_NUM,
  85                 .rx_clock       = CFG_UEC3_RX_CLK,
  86                 .tx_clock       = CFG_UEC3_TX_CLK,
  87                 .eth_type       = CFG_UEC3_ETH_TYPE,
  88         },
  89 #if (CFG_UEC3_ETH_TYPE == FAST_ETH)
  90         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
  91         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
  92 #else
  93         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
  94         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
  95 #endif
  96         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  97         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
  98         .tx_bd_ring_len         = 16,
  99         .rx_bd_ring_len         = 16,
 100         .phy_address            = CFG_UEC3_PHY_ADDR,
 101         .enet_interface         = CFG_UEC3_INTERFACE_MODE,
 102 };
 103 #endif
 104 #ifdef CONFIG_UEC_ETH4
 105 static uec_info_t eth4_uec_info = {
 106         .uf_info                = {
 107                 .ucc_num        = CFG_UEC4_UCC_NUM,
 108                 .rx_clock       = CFG_UEC4_RX_CLK,
 109                 .tx_clock       = CFG_UEC4_TX_CLK,
 110                 .eth_type       = CFG_UEC4_ETH_TYPE,
 111         },
 112 #if (CFG_UEC4_ETH_TYPE == FAST_ETH)
 113         .num_threads_tx         = UEC_NUM_OF_THREADS_1,
 114         .num_threads_rx         = UEC_NUM_OF_THREADS_1,
 115 #else
 116         .num_threads_tx         = UEC_NUM_OF_THREADS_4,
 117         .num_threads_rx         = UEC_NUM_OF_THREADS_4,
 118 #endif
 119         .riscTx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 120         .riscRx                 = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 121         .tx_bd_ring_len         = 16,
 122         .rx_bd_ring_len         = 16,
 123         .phy_address            = CFG_UEC4_PHY_ADDR,
 124         .enet_interface         = CFG_UEC4_INTERFACE_MODE,
 125 };
 126 #endif
 127
 128 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
 129 {
 130         uec_t           *uec_regs;
 131         u32             maccfg1;
 132
 133         if (!uec) {
 134                 printf("%s: uec not initial\n", __FUNCTION__);
 135                 return -EINVAL;
 136         }
 137         uec_regs = uec->uec_regs;
 138
 139         maccfg1 = in_be32(&uec_regs->maccfg1);
 140
 141         if (mode & COMM_DIR_TX) {
 142                 maccfg1 |= MACCFG1_ENABLE_TX;
 143                 out_be32(&uec_regs->maccfg1, maccfg1);
 144                 uec->mac_tx_enabled = 1;
 145         }
 146
 147         if (mode & COMM_DIR_RX) {
 148                 maccfg1 |= MACCFG1_ENABLE_RX;
 149                 out_be32(&uec_regs->maccfg1, maccfg1);
 150                 uec->mac_rx_enabled = 1;
 151         }
 152
 153         return 0;
 154 }
 155
 156 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
 157 {
 158         uec_t           *uec_regs;
 159         u32             maccfg1;
 160
 161         if (!uec) {
 162                 printf("%s: uec not initial\n", __FUNCTION__);
 163                 return -EINVAL;
 164         }
 165         uec_regs = uec->uec_regs;
 166
 167         maccfg1 = in_be32(&uec_regs->maccfg1);
 168
 169         if (mode & COMM_DIR_TX) {
 170                 maccfg1 &= ~MACCFG1_ENABLE_TX;
 171                 out_be32(&uec_regs->maccfg1, maccfg1);
 172                 uec->mac_tx_enabled = 0;
 173         }
 174
 175         if (mode & COMM_DIR_RX) {
 176                 maccfg1 &= ~MACCFG1_ENABLE_RX;
 177                 out_be32(&uec_regs->maccfg1, maccfg1);
 178                 uec->mac_rx_enabled = 0;
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int uec_graceful_stop_tx(uec_private_t *uec)
 185 {
 186         ucc_fast_t              *uf_regs;
 187         u32                     cecr_subblock;
 188         u32                     ucce;
 189
 190         if (!uec || !uec->uccf) {
 191                 printf("%s: No handle passed.\n", __FUNCTION__);
 192                 return -EINVAL;
 193         }
 194
 195         uf_regs = uec->uccf->uf_regs;
 196
 197         /* Clear the grace stop event */
 198         out_be32(&uf_regs->ucce, UCCE_GRA);
 199
 200         /* Issue host command */
 201         cecr_subblock =
 202                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 203         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
 204                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 205
 206         /* Wait for command to complete */
 207         do {
 208                 ucce = in_be32(&uf_regs->ucce);
 209         } while (! (ucce & UCCE_GRA));
 210
 211         uec->grace_stopped_tx = 1;
 212
 213         return 0;
 214 }
 215
 216 static int uec_graceful_stop_rx(uec_private_t *uec)
 217 {
 218         u32             cecr_subblock;
 219         u8              ack;
 220
 221         if (!uec) {
 222                 printf("%s: No handle passed.\n", __FUNCTION__);
 223                 return -EINVAL;
 224         }
 225
 226         if (!uec->p_rx_glbl_pram) {
 227                 printf("%s: No init rx global parameter\n", __FUNCTION__);
 228                 return -EINVAL;
 229         }
 230
 231         /* Clear acknowledge bit */
 232         ack = uec->p_rx_glbl_pram->rxgstpack;
 233         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
 234         uec->p_rx_glbl_pram->rxgstpack = ack;
 235
 236         /* Keep issuing cmd and checking ack bit until it is asserted */
 237         do {
 238                 /* Issue host command */
 239                 cecr_subblock =
 240                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 241                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
 242                                  (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 243                 ack = uec->p_rx_glbl_pram->rxgstpack;
 244         } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
 245
 246         uec->grace_stopped_rx = 1;
 247
 248         return 0;
 249 }
 250
 251 static int uec_restart_tx(uec_private_t *uec)
 252 {
 253         u32             cecr_subblock;
 254
 255         if (!uec || !uec->uec_info) {
 256                 printf("%s: No handle passed.\n", __FUNCTION__);
 257                 return -EINVAL;
 258         }
 259
 260         cecr_subblock =
 261          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 262         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
 263                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 264
 265         uec->grace_stopped_tx = 0;
 266
 267         return 0;
 268 }
 269
 270 static int uec_restart_rx(uec_private_t *uec)
 271 {
 272         u32             cecr_subblock;
 273
 274         if (!uec || !uec->uec_info) {
 275                 printf("%s: No handle passed.\n", __FUNCTION__);
 276                 return -EINVAL;
 277         }
 278
 279         cecr_subblock =
 280          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 281         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
 282                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 283
 284         uec->grace_stopped_rx = 0;
 285
 286         return 0;
 287 }
 288
 289 static int uec_open(uec_private_t *uec, comm_dir_e mode)
 290 {
 291         ucc_fast_private_t      *uccf;
 292
 293         if (!uec || !uec->uccf) {
 294                 printf("%s: No handle passed.\n", __FUNCTION__);
 295                 return -EINVAL;
 296         }
 297         uccf = uec->uccf;
 298
 299         /* check if the UCC number is in range. */
 300         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 301                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 302                 return -EINVAL;
 303         }
 304
 305         /* Enable MAC */
 306         uec_mac_enable(uec, mode);
 307
 308         /* Enable UCC fast */
 309         ucc_fast_enable(uccf, mode);
 310
 311         /* RISC microcode start */
 312         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
 313                 uec_restart_tx(uec);
 314         }
 315         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
 316                 uec_restart_rx(uec);
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
 323 {
 324         ucc_fast_private_t      *uccf;
 325
 326         if (!uec || !uec->uccf) {
 327                 printf("%s: No handle passed.\n", __FUNCTION__);
 328                 return -EINVAL;
 329         }
 330         uccf = uec->uccf;
 331
 332         /* check if the UCC number is in range. */
 333         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 334                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 335                 return -EINVAL;
 336         }
 337         /* Stop any transmissions */
 338         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
 339                 uec_graceful_stop_tx(uec);
 340         }
 341         /* Stop any receptions */
 342         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
 343                 uec_graceful_stop_rx(uec);
 344         }
 345
 346         /* Disable the UCC fast */
 347         ucc_fast_disable(uec->uccf, mode);
 348
 349         /* Disable the MAC */
 350         uec_mac_disable(uec, mode);
 351
 352         return 0;
 353 }
 354
 355 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
 356 {
 357         uec_t           *uec_regs;
 358         u32             maccfg2;
 359
 360         if (!uec) {
 361                 printf("%s: uec not initial\n", __FUNCTION__);
 362                 return -EINVAL;
 363         }
 364         uec_regs = uec->uec_regs;
 365
 366         if (duplex == DUPLEX_HALF) {
 367                 maccfg2 = in_be32(&uec_regs->maccfg2);
 368                 maccfg2 &= ~MACCFG2_FDX;
 369                 out_be32(&uec_regs->maccfg2, maccfg2);
 370         }
 371
 372         if (duplex == DUPLEX_FULL) {
 373                 maccfg2 = in_be32(&uec_regs->maccfg2);
 374                 maccfg2 |= MACCFG2_FDX;
 375                 out_be32(&uec_regs->maccfg2, maccfg2);
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
 382 {
 383         enet_interface_e        enet_if_mode;
 384         uec_info_t              *uec_info;
 385         uec_t                   *uec_regs;
 386         u32                     upsmr;
 387         u32                     maccfg2;
 388
 389         if (!uec) {
 390                 printf("%s: uec not initial\n", __FUNCTION__);
 391                 return -EINVAL;
 392         }
 393
 394         uec_info = uec->uec_info;
 395         uec_regs = uec->uec_regs;
 396         enet_if_mode = if_mode;
 397
 398         maccfg2 = in_be32(&uec_regs->maccfg2);
 399         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
 400
 401         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
 402         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
 403
 404         switch (enet_if_mode) {
 405                 case ENET_100_MII:
 406                 case ENET_10_MII:
 407                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 408                         break;
 409                 case ENET_1000_GMII:
 410                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 411                         break;
 412                 case ENET_1000_TBI:
 413                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 414                         upsmr |= UPSMR_TBIM;
 415                         break;
 416                 case ENET_1000_RTBI:
 417                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 418                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
 419                         break;
 420                 case ENET_1000_RGMII:
 421                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 422                         upsmr |= UPSMR_RPM;
 423                         break;
 424                 case ENET_100_RGMII:
 425                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 426                         upsmr |= UPSMR_RPM;
 427                         break;
 428                 case ENET_10_RGMII:
 429                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 430                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
 431                         break;
 432                 case ENET_100_RMII:
 433                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 434                         upsmr |= UPSMR_RMM;
 435                         break;
 436                 case ENET_10_RMII:
 437                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 438                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
 439                         break;
 440                 default:
 441                         return -EINVAL;
 442                         break;
 443         }
 444         out_be32(&uec_regs->maccfg2, maccfg2);
 445         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
 446
 447         return 0;
 448 }
 449
 450 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
 451 {
 452         uint            timeout = 0x1000;
 453         u32             miimcfg = 0;
 454
 455         miimcfg = in_be32(&uec_mii_regs->miimcfg);
 456         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
 457         out_be32(&uec_mii_regs->miimcfg, miimcfg);
 458
 459         /* Wait until the bus is free */
 460         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
 461         if (timeout <= 0) {
 462                 printf("%s: The MII Bus is stuck!", __FUNCTION__);
 463                 return -ETIMEDOUT;
 464         }
 465
 466         return 0;
 467 }
 468
 469 static int init_phy(struct eth_device *dev)
 470 {
 471         uec_private_t           *uec;
 472         uec_mii_t               *umii_regs;
 473         struct uec_mii_info     *mii_info;
 474         struct phy_info         *curphy;
 475         int                     err;
 476
 477         uec = (uec_private_t *)dev->priv;
 478         umii_regs = uec->uec_mii_regs;
 479
 480         uec->oldlink = 0;
 481         uec->oldspeed = 0;
 482         uec->oldduplex = -1;
 483
 484         mii_info = malloc(sizeof(*mii_info));
 485         if (!mii_info) {
 486                 printf("%s: Could not allocate mii_info", dev->name);
 487                 return -ENOMEM;
 488         }
 489         memset(mii_info, 0, sizeof(*mii_info));
 490
 491         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 492                 mii_info->speed = SPEED_1000;
 493         } else {
 494                 mii_info->speed = SPEED_100;
 495         }
 496
 497         mii_info->duplex = DUPLEX_FULL;
 498         mii_info->pause = 0;
 499         mii_info->link = 1;
 500
 501         mii_info->advertising = (ADVERTISED_10baseT_Half |
 502                                 ADVERTISED_10baseT_Full |
 503                                 ADVERTISED_100baseT_Half |
 504                                 ADVERTISED_100baseT_Full |
 505                                 ADVERTISED_1000baseT_Full);
 506         mii_info->autoneg = 1;
 507         mii_info->mii_id = uec->uec_info->phy_address;
 508         mii_info->dev = dev;
 509
 510         mii_info->mdio_read = &uec_read_phy_reg;
 511         mii_info->mdio_write = &uec_write_phy_reg;
 512
 513         uec->mii_info = mii_info;
 514
 515         if (init_mii_management_configuration(umii_regs)) {
 516                 printf("%s: The MII Bus is stuck!", dev->name);
 517                 err = -1;
 518                 goto bus_fail;
 519         }
 520
 521         /* get info for this PHY */
 522         curphy = uec_get_phy_info(uec->mii_info);
 523         if (!curphy) {
 524                 printf("%s: No PHY found", dev->name);
 525                 err = -1;
 526                 goto no_phy;
 527         }
 528
 529         mii_info->phyinfo = curphy;
 530
 531         /* Run the commands which initialize the PHY */
 532         if (curphy->init) {
 533                 err = curphy->init(uec->mii_info);
 534                 if (err)
 535                         goto phy_init_fail;
 536         }
 537
 538         return 0;
 539
 540 phy_init_fail:
 541 no_phy:
 542 bus_fail:
 543         free(mii_info);
 544         return err;
 545 }
 546
 547 static void adjust_link(struct eth_device *dev)
 548 {
 549         uec_private_t           *uec = (uec_private_t *)dev->priv;
 550         uec_t                   *uec_regs;
 551         struct uec_mii_info     *mii_info = uec->mii_info;
 552
 553         extern void change_phy_interface_mode(struct eth_device *dev,
 554                                          enet_interface_e mode);
 555         uec_regs = uec->uec_regs;
 556
 557         if (mii_info->link) {
 558                 /* Now we make sure that we can be in full duplex mode.
 559                 * If not, we operate in half-duplex mode. */
 560                 if (mii_info->duplex != uec->oldduplex) {
 561                         if (!(mii_info->duplex)) {
 562                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
 563                                 printf("%s: Half Duplex\n", dev->name);
 564                         } else {
 565                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
 566                                 printf("%s: Full Duplex\n", dev->name);
 567                         }
 568                         uec->oldduplex = mii_info->duplex;
 569                 }
 570
 571                 if (mii_info->speed != uec->oldspeed) {
 572                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 573                                 switch (mii_info->speed) {
 574                                 case 1000:
 575                                         break;
 576                                 case 100:
 577                                         printf ("switching to rgmii 100\n");
 578                                         /* change phy to rgmii 100 */
 579                                         change_phy_interface_mode(dev,
 580                                                                 ENET_100_RGMII);
 581                                         /* change the MAC interface mode */
 582                                         uec_set_mac_if_mode(uec,ENET_100_RGMII);
 583                                         break;
 584                                 case 10:
 585                                         printf ("switching to rgmii 10\n");
 586                                         /* change phy to rgmii 10 */
 587                                         change_phy_interface_mode(dev,
 588                                                                 ENET_10_RGMII);
 589                                         /* change the MAC interface mode */
 590                                         uec_set_mac_if_mode(uec,ENET_10_RGMII);
 591                                         break;
 592                                 default:
 593                                         printf("%s: Ack,Speed(%d)is illegal\n",
 594                                                 dev->name, mii_info->speed);
 595                                         break;
 596                                 }
 597                         }
 598
 599                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
 600                         uec->oldspeed = mii_info->speed;
 601                 }
 602
 603                 if (!uec->oldlink) {
 604                         printf("%s: Link is up\n", dev->name);
 605                         uec->oldlink = 1;
 606                 }
 607
 608         } else { /* if (mii_info->link) */
 609                 if (uec->oldlink) {
 610                         printf("%s: Link is down\n", dev->name);
 611                         uec->oldlink = 0;
 612                         uec->oldspeed = 0;
 613                         uec->oldduplex = -1;
 614                 }
 615         }
 616 }
 617
 618 static void phy_change(struct eth_device *dev)
 619 {
 620         uec_private_t   *uec = (uec_private_t *)dev->priv;
 621         uec_t           *uec_regs;
 622         int             result = 0;
 623
 624         uec_regs = uec->uec_regs;
 625
 626         /* Delay 5s to give the PHY a chance to change the register state */
 627         udelay(5000000);
 628
 629         /* Update the link, speed, duplex */
 630         result = uec->mii_info->phyinfo->read_status(uec->mii_info);
 631
 632         /* Adjust the interface according to speed */
 633         if ((0 == result) || (uec->mii_info->link == 0)) {
 634                 adjust_link(dev);
 635         }
 636 }
 637
 638 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
 639 {
 640         uec_t           *uec_regs;
 641         u32             mac_addr1;
 642         u32             mac_addr2;
 643
 644         if (!uec) {
 645                 printf("%s: uec not initial\n", __FUNCTION__);
 646                 return -EINVAL;
 647         }
 648
 649         uec_regs = uec->uec_regs;
 650
 651         /* if a station address of 0x12345678ABCD, perform a write to
 652         MACSTNADDR1 of 0xCDAB7856,
 653         MACSTNADDR2 of 0x34120000 */
 654
 655         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
 656                         (mac_addr[3] << 8)  | (mac_addr[2]);
 657         out_be32(&uec_regs->macstnaddr1, mac_addr1);
 658
 659         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
 660         out_be32(&uec_regs->macstnaddr2, mac_addr2);
 661
 662         return 0;
 663 }
 664
 665 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
 666                                          int *threads_num_ret)
 667 {
 668         int     num_threads_numerica;
 669
 670         switch (threads_num) {
 671                 case UEC_NUM_OF_THREADS_1:
 672                         num_threads_numerica = 1;
 673                         break;
 674                 case UEC_NUM_OF_THREADS_2:
 675                         num_threads_numerica = 2;
 676                         break;
 677                 case UEC_NUM_OF_THREADS_4:
 678                         num_threads_numerica = 4;
 679                         break;
 680                 case UEC_NUM_OF_THREADS_6:
 681                         num_threads_numerica = 6;
 682                         break;
 683                 case UEC_NUM_OF_THREADS_8:
 684                         num_threads_numerica = 8;
 685                         break;
 686                 default:
 687                         printf("%s: Bad number of threads value.",
 688                                  __FUNCTION__);
 689                         return -EINVAL;
 690         }
 691
 692         *threads_num_ret = num_threads_numerica;
 693
 694         return 0;
 695 }
 696
 697 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
 698 {
 699         uec_info_t      *uec_info;
 700         u32             end_bd;
 701         u8              bmrx = 0;
 702         int             i;
 703
 704         uec_info = uec->uec_info;
 705
 706         /* Alloc global Tx parameter RAM page */
 707         uec->tx_glbl_pram_offset = qe_muram_alloc(
 708                                 sizeof(uec_tx_global_pram_t),
 709                                  UEC_TX_GLOBAL_PRAM_ALIGNMENT);
 710         uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
 711                                 qe_muram_addr(uec->tx_glbl_pram_offset);
 712
 713         /* Zero the global Tx prameter RAM */
 714         memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
 715
 716         /* Init global Tx parameter RAM */
 717
 718         /* TEMODER, RMON statistics disable, one Tx queue */
 719         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
 720
 721         /* SQPTR */
 722         uec->send_q_mem_reg_offset = qe_muram_alloc(
 723                                 sizeof(uec_send_queue_qd_t),
 724                                  UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
 725         uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
 726                                 qe_muram_addr(uec->send_q_mem_reg_offset);
 727         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
 728
 729         /* Setup the table with TxBDs ring */
 730         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
 731                                          * SIZEOFBD;
 732         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
 733                                  (u32)(uec->p_tx_bd_ring));
 734         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
 735                                                  end_bd);
 736
 737         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
 738         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
 739
 740         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
 741         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
 742
 743         /* TSTATE, global snooping, big endian, the CSB bus selected */
 744         bmrx = BMR_INIT_VALUE;
 745         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
 746
 747         /* IPH_Offset */
 748         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
 749                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
 750         }
 751
 752         /* VTAG table */
 753         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
 754                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
 755         }
 756
 757         /* TQPTR */
 758         uec->thread_dat_tx_offset = qe_muram_alloc(
 759                 num_threads_tx * sizeof(uec_thread_data_tx_t) +
 760                  32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
 761
 762         uec->p_thread_data_tx = (uec_thread_data_tx_t *)
 763                                 qe_muram_addr(uec->thread_dat_tx_offset);
 764         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
 765 }
 766
 767 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
 768 {
 769         u8      bmrx = 0;
 770         int     i;
 771         uec_82xx_address_filtering_pram_t       *p_af_pram;
 772
 773         /* Allocate global Rx parameter RAM page */
 774         uec->rx_glbl_pram_offset = qe_muram_alloc(
 775                 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
 776         uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
 777                                 qe_muram_addr(uec->rx_glbl_pram_offset);
 778
 779         /* Zero Global Rx parameter RAM */
 780         memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
 781
 782         /* Init global Rx parameter RAM */
 783         /* REMODER, Extended feature mode disable, VLAN disable,
 784          LossLess flow control disable, Receive firmware statisic disable,
 785          Extended address parsing mode disable, One Rx queues,
 786          Dynamic maximum/minimum frame length disable, IP checksum check
 787          disable, IP address alignment disable
 788         */
 789         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
 790
 791         /* RQPTR */
 792         uec->thread_dat_rx_offset = qe_muram_alloc(
 793                         num_threads_rx * sizeof(uec_thread_data_rx_t),
 794                          UEC_THREAD_DATA_ALIGNMENT);
 795         uec->p_thread_data_rx = (uec_thread_data_rx_t *)
 796                                 qe_muram_addr(uec->thread_dat_rx_offset);
 797         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
 798
 799         /* Type_or_Len */
 800         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
 801
 802         /* RxRMON base pointer, we don't need it */
 803         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
 804
 805         /* IntCoalescingPTR, we don't need it, no interrupt */
 806         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
 807
 808         /* RSTATE, global snooping, big endian, the CSB bus selected */
 809         bmrx = BMR_INIT_VALUE;
 810         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
 811
 812         /* MRBLR */
 813         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
 814
 815         /* RBDQPTR */
 816         uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
 817                                 sizeof(uec_rx_bd_queues_entry_t) + \
 818                                 sizeof(uec_rx_prefetched_bds_t),
 819                                  UEC_RX_BD_QUEUES_ALIGNMENT);
 820         uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
 821                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
 822
 823         /* Zero it */
 824         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
 825                                         sizeof(uec_rx_prefetched_bds_t));
 826         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
 827         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
 828                  (u32)uec->p_rx_bd_ring);
 829
 830         /* MFLR */
 831         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
 832         /* MINFLR */
 833         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
 834         /* MAXD1 */
 835         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
 836         /* MAXD2 */
 837         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
 838         /* ECAM_PTR */
 839         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
 840         /* L2QT */
 841         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
 842         /* L3QT */
 843         for (i = 0; i < 8; i++) {
 844                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
 845         }
 846
 847         /* VLAN_TYPE */
 848         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
 849         /* TCI */
 850         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
 851
 852         /* Clear PQ2 style address filtering hash table */
 853         p_af_pram = (uec_82xx_address_filtering_pram_t *) \
 854                         uec->p_rx_glbl_pram->addressfiltering;
 855
 856         p_af_pram->iaddr_h = 0;
 857         p_af_pram->iaddr_l = 0;
 858         p_af_pram->gaddr_h = 0;
 859         p_af_pram->gaddr_l = 0;
 860 }
 861
 862 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
 863                                          int thread_tx, int thread_rx)
 864 {
 865         uec_init_cmd_pram_t             *p_init_enet_param;
 866         u32                             init_enet_param_offset;
 867         uec_info_t                      *uec_info;
 868         int                             i;
 869         int                             snum;
 870         u32                             init_enet_offset;
 871         u32                             entry_val;
 872         u32                             command;
 873         u32                             cecr_subblock;
 874
 875         uec_info = uec->uec_info;
 876
 877         /* Allocate init enet command parameter */
 878         uec->init_enet_param_offset = qe_muram_alloc(
 879                                         sizeof(uec_init_cmd_pram_t), 4);
 880         init_enet_param_offset = uec->init_enet_param_offset;
 881         uec->p_init_enet_param = (uec_init_cmd_pram_t *)
 882                                 qe_muram_addr(uec->init_enet_param_offset);
 883
 884         /* Zero init enet command struct */
 885         memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
 886
 887         /* Init the command struct */
 888         p_init_enet_param = uec->p_init_enet_param;
 889         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
 890         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
 891         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
 892         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
 893         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
 894         p_init_enet_param->largestexternallookupkeysize = 0;
 895
 896         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
 897                                          << ENET_INIT_PARAM_RGF_SHIFT;
 898         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
 899                                          << ENET_INIT_PARAM_TGF_SHIFT;
 900
 901         /* Init Rx global parameter pointer */
 902         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
 903                                                  (u32)uec_info->riscRx;
 904
 905         /* Init Rx threads */
 906         for (i = 0; i < (thread_rx + 1); i++) {
 907                 if ((snum = qe_get_snum()) < 0) {
 908                         printf("%s can not get snum\n", __FUNCTION__);
 909                         return -ENOMEM;
 910                 }
 911
 912                 if (i==0) {
 913                         init_enet_offset = 0;
 914                 } else {
 915                         init_enet_offset = qe_muram_alloc(
 916                                         sizeof(uec_thread_rx_pram_t),
 917                                          UEC_THREAD_RX_PRAM_ALIGNMENT);
 918                 }
 919
 920                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 921                                  init_enet_offset | (u32)uec_info->riscRx;
 922                 p_init_enet_param->rxthread[i] = entry_val;
 923         }
 924
 925         /* Init Tx global parameter pointer */
 926         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
 927                                          (u32)uec_info->riscTx;
 928
 929         /* Init Tx threads */
 930         for (i = 0; i < thread_tx; i++) {
 931                 if ((snum = qe_get_snum()) < 0) {
 932                         printf("%s can not get snum\n", __FUNCTION__);
 933                         return -ENOMEM;
 934                 }
 935
 936                 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
 937                                                  UEC_THREAD_TX_PRAM_ALIGNMENT);
 938
 939                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 940                                  init_enet_offset | (u32)uec_info->riscTx;
 941                 p_init_enet_param->txthread[i] = entry_val;
 942         }
 943
 944         __asm__ __volatile__("sync");
 945
 946         /* Issue QE command */
 947         command = QE_INIT_TX_RX;
 948         cecr_subblock = ucc_fast_get_qe_cr_subblock(
 949                                 uec->uec_info->uf_info.ucc_num);
 950         qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
 951                                                  init_enet_param_offset);
 952
 953         return 0;
 954 }
 955
 956 static int uec_startup(uec_private_t *uec)
 957 {
 958         uec_info_t                      *uec_info;
 959         ucc_fast_info_t                 *uf_info;
 960         ucc_fast_private_t              *uccf;
 961         ucc_fast_t                      *uf_regs;
 962         uec_t                           *uec_regs;
 963         int                             num_threads_tx;
 964         int                             num_threads_rx;
 965         u32                             utbipar;
 966         enet_interface_e                enet_interface;
 967         u32                             length;
 968         u32                             align;
 969         qe_bd_t                         *bd;
 970         u8                              *buf;
 971         int                             i;
 972
 973         if (!uec || !uec->uec_info) {
 974                 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
 975                 return -EINVAL;
 976         }
 977
 978         uec_info = uec->uec_info;
 979         uf_info = &(uec_info->uf_info);
 980
 981         /* Check if Rx BD ring len is illegal */
 982         if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
 983                 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
 984                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
 985                          __FUNCTION__);
 986                 return -EINVAL;
 987         }
 988
 989         /* Check if Tx BD ring len is illegal */
 990         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
 991                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
 992                          __FUNCTION__);
 993                 return -EINVAL;
 994         }
 995
 996         /* Check if MRBLR is illegal */
 997         if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
 998                 printf("%s: max rx buffer length must be mutliple of 128.\n",
 999                          __FUNCTION__);
1000                 return -EINVAL;
1001         }
1002
1003         /* Both Rx and Tx are stopped */
1004         uec->grace_stopped_rx = 1;
1005         uec->grace_stopped_tx = 1;
1006
1007         /* Init UCC fast */
1008         if (ucc_fast_init(uf_info, &uccf)) {
1009                 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1010                 return -ENOMEM;
1011         }
1012
1013         /* Save uccf */
1014         uec->uccf = uccf;
1015
1016         /* Convert the Tx threads number */
1017         if (uec_convert_threads_num(uec_info->num_threads_tx,
1018                                          &num_threads_tx)) {
1019                 return -EINVAL;
1020         }
1021
1022         /* Convert the Rx threads number */
1023         if (uec_convert_threads_num(uec_info->num_threads_rx,
1024                                          &num_threads_rx)) {
1025                 return -EINVAL;
1026         }
1027
1028         uf_regs = uccf->uf_regs;
1029
1030         /* UEC register is following UCC fast registers */
1031         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1032
1033         /* Save the UEC register pointer to UEC private struct */
1034         uec->uec_regs = uec_regs;
1035
1036         /* Init UPSMR, enable hardware statistics (UCC) */
1037         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1038
1039         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1040         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1041
1042         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1043         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1044
1045         /* Setup MAC interface mode */
1046         uec_set_mac_if_mode(uec, uec_info->enet_interface);
1047
1048         /* Setup MII management base */
1049 #ifndef CONFIG_eTSEC_MDIO_BUS
1050         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1051 #else
1052         uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1053 #endif
1054
1055         /* Setup MII master clock source */
1056         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1057
1058         /* Setup UTBIPAR */
1059         utbipar = in_be32(&uec_regs->utbipar);
1060         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1061         enet_interface = uec->uec_info->enet_interface;
1062         if (enet_interface == ENET_1000_TBI ||
1063                  enet_interface == ENET_1000_RTBI) {
1064                 utbipar |=  (uec_info->phy_address + uec_info->uf_info.ucc_num)
1065                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1066         } else {
1067                 utbipar |=  (0x10 + uec_info->uf_info.ucc_num)
1068                                                  << UTBIPAR_PHY_ADDRESS_SHIFT;
1069         }
1070
1071         out_be32(&uec_regs->utbipar, utbipar);
1072
1073         /* Allocate Tx BDs */
1074         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1075                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1076                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1077         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1078                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1079                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1080         }
1081
1082         align = UEC_TX_BD_RING_ALIGNMENT;
1083         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1084         if (uec->tx_bd_ring_offset != 0) {
1085                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1086                                                  & ~(align - 1));
1087         }
1088
1089         /* Zero all of Tx BDs */
1090         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1091
1092         /* Allocate Rx BDs */
1093         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1094         align = UEC_RX_BD_RING_ALIGNMENT;
1095         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1096         if (uec->rx_bd_ring_offset != 0) {
1097                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1098                                                          & ~(align - 1));
1099         }
1100
1101         /* Zero all of Rx BDs */
1102         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1103
1104         /* Allocate Rx buffer */
1105         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1106         align = UEC_RX_DATA_BUF_ALIGNMENT;
1107         uec->rx_buf_offset = (u32)malloc(length + align);
1108         if (uec->rx_buf_offset != 0) {
1109                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1110                                                  & ~(align - 1));
1111         }
1112
1113         /* Zero all of the Rx buffer */
1114         memset((void *)(uec->rx_buf_offset), 0, length + align);
1115
1116         /* Init TxBD ring */
1117         bd = (qe_bd_t *)uec->p_tx_bd_ring;
1118         uec->txBd = bd;
1119
1120         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1121                 BD_DATA_CLEAR(bd);
1122                 BD_STATUS_SET(bd, 0);
1123                 BD_LENGTH_SET(bd, 0);
1124                 bd ++;
1125         }
1126         BD_STATUS_SET((--bd), TxBD_WRAP);
1127
1128         /* Init RxBD ring */
1129         bd = (qe_bd_t *)uec->p_rx_bd_ring;
1130         uec->rxBd = bd;
1131         buf = uec->p_rx_buf;
1132         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1133                 BD_DATA_SET(bd, buf);
1134                 BD_LENGTH_SET(bd, 0);
1135                 BD_STATUS_SET(bd, RxBD_EMPTY);
1136                 buf += MAX_RXBUF_LEN;
1137                 bd ++;
1138         }
1139         BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1140
1141         /* Init global Tx parameter RAM */
1142         uec_init_tx_parameter(uec, num_threads_tx);
1143
1144         /* Init global Rx parameter RAM */
1145         uec_init_rx_parameter(uec, num_threads_rx);
1146
1147         /* Init ethernet Tx and Rx parameter command */
1148         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1149                                          num_threads_rx)) {
1150                 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1151                 return -ENOMEM;
1152         }
1153
1154         return 0;
1155 }
1156
1157 static int uec_init(struct eth_device* dev, bd_t *bd)
1158 {
1159         uec_private_t           *uec;
1160         int                     err;
1161
1162         uec = (uec_private_t *)dev->priv;
1163
1164         if (uec->the_first_run == 0) {
1165                 /* Set up the MAC address */
1166                 if (dev->enetaddr[0] & 0x01) {
1167                         printf("%s: MacAddress is multcast address\n",
1168                                  __FUNCTION__);
1169                         return -1;
1170                 }
1171                 uec_set_mac_address(uec, dev->enetaddr);
1172                 uec->the_first_run = 1;
1173         }
1174
1175         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1176         if (err) {
1177                 printf("%s: cannot enable UEC device\n", dev->name);
1178                 return -1;
1179         }
1180
1181         return (uec->mii_info->link ? 0 : -1);
1182 }
1183
1184 static void uec_halt(struct eth_device* dev)
1185 {
1186         uec_private_t   *uec = (uec_private_t *)dev->priv;
1187         uec_stop(uec, COMM_DIR_RX_AND_TX);
1188 }
1189
1190 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1191 {
1192         uec_private_t           *uec;
1193         ucc_fast_private_t      *uccf;
1194         volatile qe_bd_t        *bd;
1195         u16                     status;
1196         int                     i;
1197         int                     result = 0;
1198
1199         uec = (uec_private_t *)dev->priv;
1200         uccf = uec->uccf;
1201         bd = uec->txBd;
1202
1203         /* Find an empty TxBD */
1204         for (i = 0; bd->status & TxBD_READY; i++) {
1205                 if (i > 0x100000) {
1206                         printf("%s: tx buffer not ready\n", dev->name);
1207                         return result;
1208                 }
1209         }
1210
1211         /* Init TxBD */
1212         BD_DATA_SET(bd, buf);
1213         BD_LENGTH_SET(bd, len);
1214         status = bd->status;
1215         status &= BD_WRAP;
1216         status |= (TxBD_READY | TxBD_LAST);
1217         BD_STATUS_SET(bd, status);
1218
1219         /* Tell UCC to transmit the buffer */
1220         ucc_fast_transmit_on_demand(uccf);
1221
1222         /* Wait for buffer to be transmitted */
1223         for (i = 0; bd->status & TxBD_READY; i++) {
1224                 if (i > 0x100000) {
1225                         printf("%s: tx error\n", dev->name);
1226                         return result;
1227                 }
1228         }
1229
1230         /* Ok, the buffer be transimitted */
1231         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1232         uec->txBd = bd;
1233         result = 1;
1234
1235         return result;
1236 }
1237
1238 static int uec_recv(struct eth_device* dev)
1239 {
1240         uec_private_t           *uec = dev->priv;
1241         volatile qe_bd_t        *bd;
1242         u16                     status;
1243         u16                     len;
1244         u8                      *data;
1245
1246         bd = uec->rxBd;
1247         status = bd->status;
1248
1249         while (!(status & RxBD_EMPTY)) {
1250                 if (!(status & RxBD_ERROR)) {
1251                         data = BD_DATA(bd);
1252                         len = BD_LENGTH(bd);
1253                         NetReceive(data, len);
1254                 } else {
1255                         printf("%s: Rx error\n", dev->name);
1256                 }
1257                 status &= BD_CLEAN;
1258                 BD_LENGTH_SET(bd, 0);
1259                 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1260                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1261                 status = bd->status;
1262         }
1263         uec->rxBd = bd;
1264
1265         return 1;
1266 }
1267
1268 int uec_initialize(int index)
1269 {
1270         struct eth_device       *dev;
1271         int                     i;
1272         uec_private_t           *uec;
1273         uec_info_t              *uec_info;
1274         int                     err;
1275
1276         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1277         if (!dev)
1278                 return 0;
1279         memset(dev, 0, sizeof(struct eth_device));
1280
1281         /* Allocate the UEC private struct */
1282         uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1283         if (!uec) {
1284                 return -ENOMEM;
1285         }
1286         memset(uec, 0, sizeof(uec_private_t));
1287
1288         /* Init UEC private struct, they come from board.h */
1289         uec_info = NULL;
1290         if (index == 0) {
1291 #ifdef CONFIG_UEC_ETH1
1292                 uec_info = &eth1_uec_info;
1293 #endif
1294         } else if (index == 1) {
1295 #ifdef CONFIG_UEC_ETH2
1296                 uec_info = &eth2_uec_info;
1297 #endif
1298         } else if (index == 2) {
1299 #ifdef CONFIG_UEC_ETH3
1300                 uec_info = &eth3_uec_info;
1301 #endif
1302         } else if (index == 3) {
1303 #ifdef CONFIG_UEC_ETH4
1304                 uec_info = &eth4_uec_info;
1305 #endif
1306         } else {
1307                 printf("%s: index is illegal.\n", __FUNCTION__);
1308                 return -EINVAL;
1309         }
1310
1311         uec->uec_info = uec_info;
1312
1313         sprintf(dev->name, "FSL UEC%d", index);
1314         dev->iobase = 0;
1315         dev->priv = (void *)uec;
1316         dev->init = uec_init;
1317         dev->halt = uec_halt;
1318         dev->send = uec_send;
1319         dev->recv = uec_recv;
1320
1321         /* Clear the ethnet address */
1322         for (i = 0; i < 6; i++)
1323                 dev->enetaddr[i] = 0;
1324
1325         eth_register(dev);
1326
1327         err = uec_startup(uec);
1328         if (err) {
1329                 printf("%s: Cannot configure net device, aborting.",dev->name);
1330                 return err;
1331         }
1332
1333         err = init_phy(dev);
1334         if (err) {
1335                 printf("%s: Cannot initialize PHY, aborting.\n", dev->name);
1336                 return err;
1337         }
1338
1339         phy_change(dev);
1340
1341         return 1;
1342 }
1343 #endif /* CONFIG_QE */