tegra2: Enable MMC for Seaboard
[oweals/u-boot.git] / drivers / qe / uccf.c
1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  * based on source code of Shlomi Gridish
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22
23 #include "common.h"
24 #include "malloc.h"
25 #include "asm/errno.h"
26 #include "asm/io.h"
27 #include "asm/immap_qe.h"
28 #include "qe.h"
29 #include "uccf.h"
30
31 void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
32 {
33         out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
34 }
35
36 u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
37 {
38         switch (ucc_num) {
39                 case 0: return QE_CR_SUBBLOCK_UCCFAST1;
40                 case 1: return QE_CR_SUBBLOCK_UCCFAST2;
41                 case 2: return QE_CR_SUBBLOCK_UCCFAST3;
42                 case 3: return QE_CR_SUBBLOCK_UCCFAST4;
43                 case 4: return QE_CR_SUBBLOCK_UCCFAST5;
44                 case 5: return QE_CR_SUBBLOCK_UCCFAST6;
45                 case 6: return QE_CR_SUBBLOCK_UCCFAST7;
46                 case 7: return QE_CR_SUBBLOCK_UCCFAST8;
47                 default:        return QE_CR_SUBBLOCK_INVALID;
48         }
49 }
50
51 static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr,
52                                  u8 *reg_num, u8 *shift)
53 {
54         switch (ucc_num) {
55                 case 0: /* UCC1 */
56                         *p_cmxucr  = &(qe_immr->qmx.cmxucr1);
57                         *reg_num = 1;
58                         *shift  = 16;
59                         break;
60                 case 2: /* UCC3 */
61                         *p_cmxucr  = &(qe_immr->qmx.cmxucr1);
62                         *reg_num = 1;
63                         *shift  = 0;
64                         break;
65                 case 4: /* UCC5 */
66                         *p_cmxucr  = &(qe_immr->qmx.cmxucr2);
67                         *reg_num = 2;
68                         *shift  = 16;
69                         break;
70                 case 6: /* UCC7 */
71                         *p_cmxucr  = &(qe_immr->qmx.cmxucr2);
72                         *reg_num = 2;
73                         *shift  = 0;
74                         break;
75                 case 1: /* UCC2 */
76                         *p_cmxucr  = &(qe_immr->qmx.cmxucr3);
77                         *reg_num = 3;
78                         *shift  = 16;
79                         break;
80                 case 3: /* UCC4 */
81                         *p_cmxucr  = &(qe_immr->qmx.cmxucr3);
82                         *reg_num = 3;
83                         *shift  = 0;
84                         break;
85                 case 5: /* UCC6 */
86                         *p_cmxucr  = &(qe_immr->qmx.cmxucr4);
87                         *reg_num = 4;
88                         *shift  = 16;
89                         break;
90                 case 7: /* UCC8 */
91                         *p_cmxucr  = &(qe_immr->qmx.cmxucr4);
92                         *reg_num = 4;
93                         *shift  = 0;
94                         break;
95                 default:
96                         break;
97         }
98 }
99
100 static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
101 {
102         volatile u32    *p_cmxucr = NULL;
103         u8              reg_num = 0;
104         u8              shift = 0;
105         u32             clockBits;
106         u32             clockMask;
107         int             source = -1;
108
109         /* check if the UCC number is in range. */
110         if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
111                 return -EINVAL;
112
113         if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
114                 printf("%s: bad comm mode type passed\n", __FUNCTION__);
115                 return -EINVAL;
116         }
117
118         ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
119
120         switch (reg_num) {
121                 case 1:
122                         switch (clock) {
123                                 case QE_BRG1:   source = 1; break;
124                                 case QE_BRG2:   source = 2; break;
125                                 case QE_BRG7:   source = 3; break;
126                                 case QE_BRG8:   source = 4; break;
127                                 case QE_CLK9:   source = 5; break;
128                                 case QE_CLK10:  source = 6; break;
129                                 case QE_CLK11:  source = 7; break;
130                                 case QE_CLK12:  source = 8; break;
131                                 case QE_CLK15:  source = 9; break;
132                                 case QE_CLK16:  source = 10; break;
133                                 default:        source = -1; break;
134                         }
135                         break;
136                 case 2:
137                         switch (clock) {
138                                 case QE_BRG5:   source = 1; break;
139                                 case QE_BRG6:   source = 2; break;
140                                 case QE_BRG7:   source = 3; break;
141                                 case QE_BRG8:   source = 4; break;
142                                 case QE_CLK13:  source = 5; break;
143                                 case QE_CLK14:  source = 6; break;
144                                 case QE_CLK19:  source = 7; break;
145                                 case QE_CLK20:  source = 8; break;
146                                 case QE_CLK15:  source = 9; break;
147                                 case QE_CLK16:  source = 10; break;
148                                 default:        source = -1; break;
149                         }
150                         break;
151                 case 3:
152                         switch (clock) {
153                                 case QE_BRG9:   source = 1; break;
154                                 case QE_BRG10:  source = 2; break;
155                                 case QE_BRG15:  source = 3; break;
156                                 case QE_BRG16:  source = 4; break;
157                                 case QE_CLK3:   source = 5; break;
158                                 case QE_CLK4:   source = 6; break;
159                                 case QE_CLK17:  source = 7; break;
160                                 case QE_CLK18:  source = 8; break;
161                                 case QE_CLK7:   source = 9; break;
162                                 case QE_CLK8:   source = 10; break;
163                                 case QE_CLK16:  source = 11; break;
164                                 default:        source = -1; break;
165                         }
166                         break;
167                 case 4:
168                         switch (clock) {
169                                 case QE_BRG13:  source = 1; break;
170                                 case QE_BRG14:  source = 2; break;
171                                 case QE_BRG15:  source = 3; break;
172                                 case QE_BRG16:  source = 4; break;
173                                 case QE_CLK5:   source = 5; break;
174                                 case QE_CLK6:   source = 6; break;
175                                 case QE_CLK21:  source = 7; break;
176                                 case QE_CLK22:  source = 8; break;
177                                 case QE_CLK7:   source = 9; break;
178                                 case QE_CLK8:   source = 10; break;
179                                 case QE_CLK16:  source = 11; break;
180                                 default:        source = -1; break;
181                         }
182                         break;
183                 default:
184                         source = -1;
185                         break;
186         }
187
188         if (source == -1) {
189                 printf("%s: Bad combination of clock and UCC\n", __FUNCTION__);
190                 return -ENOENT;
191         }
192
193         clockBits = (u32) source;
194         clockMask = QE_CMXUCR_TX_CLK_SRC_MASK;
195         if (mode == COMM_DIR_RX) {
196                 clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */
197                 clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */
198         }
199         clockBits <<= shift;
200         clockMask <<= shift;
201
202         out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits);
203
204         return 0;
205 }
206
207 static uint ucc_get_reg_baseaddr(int ucc_num)
208 {
209         uint base = 0;
210
211         /* check if the UCC number is in range */
212         if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
213                 printf("%s: the UCC num not in ranges\n", __FUNCTION__);
214                 return 0;
215         }
216
217         switch (ucc_num) {
218                 case 0: base = 0x00002000; break;
219                 case 1: base = 0x00003000; break;
220                 case 2: base = 0x00002200; break;
221                 case 3: base = 0x00003200; break;
222                 case 4: base = 0x00002400; break;
223                 case 5: base = 0x00003400; break;
224                 case 6: base = 0x00002600; break;
225                 case 7: base = 0x00003600; break;
226                 default: break;
227         }
228
229         base = (uint)qe_immr + base;
230         return base;
231 }
232
233 void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode)
234 {
235         ucc_fast_t      *uf_regs;
236         u32             gumr;
237
238         uf_regs = uccf->uf_regs;
239
240         /* Enable reception and/or transmission on this UCC. */
241         gumr = in_be32(&uf_regs->gumr);
242         if (mode & COMM_DIR_TX) {
243                 gumr |= UCC_FAST_GUMR_ENT;
244                 uccf->enabled_tx = 1;
245         }
246         if (mode & COMM_DIR_RX) {
247                 gumr |= UCC_FAST_GUMR_ENR;
248                 uccf->enabled_rx = 1;
249         }
250         out_be32(&uf_regs->gumr, gumr);
251 }
252
253 void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode)
254 {
255         ucc_fast_t      *uf_regs;
256         u32             gumr;
257
258         uf_regs = uccf->uf_regs;
259
260         /* Disable reception and/or transmission on this UCC. */
261         gumr = in_be32(&uf_regs->gumr);
262         if (mode & COMM_DIR_TX) {
263                 gumr &= ~UCC_FAST_GUMR_ENT;
264                 uccf->enabled_tx = 0;
265         }
266         if (mode & COMM_DIR_RX) {
267                 gumr &= ~UCC_FAST_GUMR_ENR;
268                 uccf->enabled_rx = 0;
269         }
270         out_be32(&uf_regs->gumr, gumr);
271 }
272
273 int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t  **uccf_ret)
274 {
275         ucc_fast_private_t      *uccf;
276         ucc_fast_t              *uf_regs;
277
278         if (!uf_info)
279                 return -EINVAL;
280
281         if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
282                 printf("%s: Illagal UCC number!\n", __FUNCTION__);
283                 return -EINVAL;
284         }
285
286         uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t));
287         if (!uccf) {
288                 printf("%s: No memory for UCC fast data structure!\n",
289                          __FUNCTION__);
290                 return -ENOMEM;
291         }
292         memset(uccf, 0, sizeof(ucc_fast_private_t));
293
294         /* Save fast UCC structure */
295         uccf->uf_info   = uf_info;
296         uccf->uf_regs   = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
297
298         if (uccf->uf_regs == NULL) {
299                 printf("%s: No memory map for UCC fast controller!\n",
300                          __FUNCTION__);
301                 return -ENOMEM;
302         }
303
304         uccf->enabled_tx        = 0;
305         uccf->enabled_rx        = 0;
306
307         uf_regs                 = uccf->uf_regs;
308         uccf->p_ucce            = (u32 *) &(uf_regs->ucce);
309         uccf->p_uccm            = (u32 *) &(uf_regs->uccm);
310
311         /* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
312         out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
313                                  | UCC_GUEMR_MODE_FAST_TX);
314
315         /* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
316         out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
317
318         /* Set the Giga ethernet VFIFO stuff */
319         if (uf_info->eth_type == GIGA_ETH) {
320                 /* Allocate memory for Tx Virtual Fifo */
321                 uccf->ucc_fast_tx_virtual_fifo_base_offset =
322                 qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
323                                  UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
324
325                 /* Allocate memory for Rx Virtual Fifo */
326                 uccf->ucc_fast_rx_virtual_fifo_base_offset =
327                 qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
328                                  UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
329                                 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
330
331                 /* utfb, urfb are offsets from MURAM base */
332                 out_be32(&uf_regs->utfb,
333                          uccf->ucc_fast_tx_virtual_fifo_base_offset);
334                 out_be32(&uf_regs->urfb,
335                          uccf->ucc_fast_rx_virtual_fifo_base_offset);
336
337                 /* Set Virtual Fifo registers */
338                 out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
339                 out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
340                 out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
341                 out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
342                 out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
343                 out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
344         }
345
346         /* Set the Fast ethernet VFIFO stuff */
347         if (uf_info->eth_type == FAST_ETH) {
348                 /* Allocate memory for Tx Virtual Fifo */
349                 uccf->ucc_fast_tx_virtual_fifo_base_offset =
350                 qe_muram_alloc(UCC_GETH_UTFS_INIT,
351                                  UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
352
353                 /* Allocate memory for Rx Virtual Fifo */
354                 uccf->ucc_fast_rx_virtual_fifo_base_offset =
355                 qe_muram_alloc(UCC_GETH_URFS_INIT +
356                                  UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
357                                 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
358
359                 /* utfb, urfb are offsets from MURAM base */
360                 out_be32(&uf_regs->utfb,
361                          uccf->ucc_fast_tx_virtual_fifo_base_offset);
362                 out_be32(&uf_regs->urfb,
363                          uccf->ucc_fast_rx_virtual_fifo_base_offset);
364
365                 /* Set Virtual Fifo registers */
366                 out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
367                 out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
368                 out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
369                 out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
370                 out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
371                 out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
372         }
373
374         /* Rx clock routing */
375         if (uf_info->rx_clock != QE_CLK_NONE) {
376                 if (ucc_set_clk_src(uf_info->ucc_num,
377                          uf_info->rx_clock, COMM_DIR_RX)) {
378                         printf("%s: Illegal value for parameter 'RxClock'.\n",
379                                  __FUNCTION__);
380                         return -EINVAL;
381                 }
382         }
383
384         /* Tx clock routing */
385         if (uf_info->tx_clock != QE_CLK_NONE) {
386                 if (ucc_set_clk_src(uf_info->ucc_num,
387                          uf_info->tx_clock, COMM_DIR_TX)) {
388                         printf("%s: Illegal value for parameter 'TxClock'.\n",
389                                  __FUNCTION__);
390                         return -EINVAL;
391                 }
392         }
393
394         /* Clear interrupt mask register to disable all of interrupts */
395         out_be32(&uf_regs->uccm, 0x0);
396
397         /* Writing '1' to clear all of envents */
398         out_be32(&uf_regs->ucce, 0xffffffff);
399
400         *uccf_ret = uccf;
401         return 0;
402 }