2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include "asm/errno.h"
27 #include "asm/immap_qe.h"
30 qe_map_t *qe_immr = NULL;
31 static qe_snum_t snums[QE_NUM_OF_SNUM];
33 DECLARE_GLOBAL_DATA_PTR;
35 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
39 if (cmd == QE_RESET) {
40 out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
42 out_be32(&qe_immr->cp.cecdr, cmd_data);
43 out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
44 ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
46 /* Wait for the QE_CR_FLG to clear */
48 cecr = in_be32(&qe_immr->cp.cecr);
49 } while (cecr & QE_CR_FLG);
54 uint qe_muram_alloc(uint size, uint align)
60 align_mask = align - 1;
61 savebase = gd->mp_alloc_base;
63 if ((off = (gd->mp_alloc_base & align_mask)) != 0)
64 gd->mp_alloc_base += (align - off);
66 if ((off = size & align_mask) != 0)
67 size += (align - off);
69 if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) {
70 gd->mp_alloc_base = savebase;
71 printf("%s: ran out of ram.\n", __FUNCTION__);
74 retloc = gd->mp_alloc_base;
75 gd->mp_alloc_base += size;
77 memset((void *)&qe_immr->muram[retloc], 0, size);
79 __asm__ __volatile__("sync");
84 void *qe_muram_addr(uint offset)
86 return (void *)&qe_immr->muram[offset];
89 static void qe_sdma_init(void)
92 uint sdma_buffer_base;
94 p = (volatile sdma_t *)&qe_immr->sdma;
96 /* All of DMA transaction in bus 1 */
97 out_be32(&p->sdaqr, 0);
98 out_be32(&p->sdaqmr, 0);
100 /* Allocate 2KB temporary buffer for sdma */
101 sdma_buffer_base = qe_muram_alloc(2048, 4096);
102 out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
104 /* Clear sdma status */
105 out_be32(&p->sdsr, 0x03000000);
107 /* Enable global mode on bus 1, and 2KB buffer size */
108 out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
111 static u8 thread_snum[QE_NUM_OF_SNUM] = {
112 0x04, 0x05, 0x0c, 0x0d,
113 0x14, 0x15, 0x1c, 0x1d,
114 0x24, 0x25, 0x2c, 0x2d,
115 0x34, 0x35, 0x88, 0x89,
116 0x98, 0x99, 0xa8, 0xa9,
117 0xb8, 0xb9, 0xc8, 0xc9,
118 0xd8, 0xd9, 0xe8, 0xe9
121 static void qe_snums_init(void)
125 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
126 snums[i].state = QE_SNUM_STATE_FREE;
127 snums[i].num = thread_snum[i];
131 int qe_get_snum(void)
136 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
137 if (snums[i].state == QE_SNUM_STATE_FREE) {
138 snums[i].state = QE_SNUM_STATE_USED;
147 void qe_put_snum(u8 snum)
151 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
152 if (snums[i].num == snum) {
153 snums[i].state = QE_SNUM_STATE_FREE;
159 void qe_init(uint qe_base)
161 /* Init the QE IMMR base */
162 qe_immr = (qe_map_t *)qe_base;
164 #ifdef CONFIG_SYS_QE_FW_ADDR
166 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
168 qe_upload_firmware((const struct qe_firmware *) CONFIG_SYS_QE_FW_ADDR);
170 /* enable the microcode in IRAM */
171 out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
174 gd->mp_alloc_base = QE_DATAONLY_BASE;
175 gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE;
183 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
184 (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
187 void qe_assign_page(uint snum, uint para_ram_base)
191 out_be32(&qe_immr->cp.cecdr, para_ram_base);
192 out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
193 | QE_CR_FLG | QE_ASSIGN_PAGE);
195 /* Wait for the QE_CR_FLG to clear */
197 cecr = in_be32(&qe_immr->cp.cecr);
198 } while (cecr & QE_CR_FLG );
204 * brg: 0~15 as BRG1~BRG16
206 * BRG input clock comes from the BRGCLK (internal clock generated from
207 the QE clock, it is one-half of the QE clock), If need the clock source
208 from CLKn pin, we have te change the function.
211 #define BRG_CLK (gd->brg_clk)
213 int qe_set_brg(uint brg, uint rate)
219 if (brg >= QE_NUM_OF_BRGS)
221 bp = (uint *)&qe_immr->brg.brgc1;
224 divisor = (BRG_CLK / rate);
225 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
230 *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
231 __asm__ __volatile__("sync");
234 *bp |= QE_BRGC_DIV16;
235 __asm__ __volatile__("sync");
241 /* Set ethernet MII clock master
243 int qe_set_mii_clk_src(int ucc_num)
247 /* check if the UCC number is in range. */
248 if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
249 printf("%s: ucc num not in ranges\n", __FUNCTION__);
253 cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
254 cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
255 cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
256 out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
261 /* The maximum number of RISCs we support */
262 #define MAX_QE_RISC 2
264 /* Firmware information stored here for qe_get_firmware_info() */
265 static struct qe_firmware_info qe_firmware_info;
268 * Set to 1 if QE firmware has been uploaded, and therefore
269 * qe_firmware_info contains valid data.
271 static int qe_firmware_uploaded;
274 * Upload a QE microcode
276 * This function is a worker function for qe_upload_firmware(). It does
277 * the actual uploading of the microcode.
279 static void qe_upload_microcode(const void *base,
280 const struct qe_microcode *ucode)
282 const u32 *code = base + be32_to_cpu(ucode->code_offset);
285 if (ucode->major || ucode->minor || ucode->revision)
286 printf("QE: uploading microcode '%s' version %u.%u.%u\n",
287 ucode->id, ucode->major, ucode->minor, ucode->revision);
289 printf("QE: uploading microcode '%s'\n", ucode->id);
291 /* Use auto-increment */
292 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
293 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
295 for (i = 0; i < be32_to_cpu(ucode->count); i++)
296 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
300 * Upload a microcode to the I-RAM at a specific address.
302 * See docs/README.qe_firmware for information on QE microcode uploading.
304 * Currently, only version 1 is supported, so the 'version' field must be
307 * The SOC model and revision are not validated, they are only displayed for
308 * informational purposes.
310 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
311 * all of the microcode structures, minus the CRC.
313 * 'length' is the size that the structure says it is, including the CRC.
315 int qe_upload_firmware(const struct qe_firmware *firmware)
320 size_t calc_size = sizeof(struct qe_firmware);
322 const struct qe_header *hdr;
325 printf("Invalid address\n");
329 hdr = &firmware->header;
330 length = be32_to_cpu(hdr->length);
332 /* Check the magic */
333 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
334 (hdr->magic[2] != 'F')) {
335 printf("Not a microcode\n");
339 /* Check the version */
340 if (hdr->version != 1) {
341 printf("Unsupported version\n");
345 /* Validate some of the fields */
346 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
347 printf("Invalid data\n");
351 /* Validate the length and check if there's a CRC */
352 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
354 for (i = 0; i < firmware->count; i++)
356 * For situations where the second RISC uses the same microcode
357 * as the first, the 'code_offset' and 'count' fields will be
358 * zero, so it's okay to add those.
360 calc_size += sizeof(u32) *
361 be32_to_cpu(firmware->microcode[i].count);
363 /* Validate the length */
364 if (length != calc_size + sizeof(u32)) {
365 printf("Invalid length\n");
370 * Validate the CRC. We would normally call crc32_no_comp(), but that
371 * function isn't available unless you turn on JFFS support.
373 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
374 if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
375 printf("Firmware CRC is invalid\n");
380 * If the microcode calls for it, split the I-RAM.
382 if (!firmware->split) {
383 out_be16(&qe_immr->cp.cercr,
384 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
387 if (firmware->soc.model)
388 printf("Firmware '%s' for %u V%u.%u\n",
389 firmware->id, be16_to_cpu(firmware->soc.model),
390 firmware->soc.major, firmware->soc.minor);
392 printf("Firmware '%s'\n", firmware->id);
395 * The QE only supports one microcode per RISC, so clear out all the
396 * saved microcode information and put in the new.
398 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
399 strcpy(qe_firmware_info.id, (char *)firmware->id);
400 qe_firmware_info.extended_modes = firmware->extended_modes;
401 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
402 sizeof(firmware->vtraps));
403 qe_firmware_uploaded = 1;
405 /* Loop through each microcode. */
406 for (i = 0; i < firmware->count; i++) {
407 const struct qe_microcode *ucode = &firmware->microcode[i];
409 /* Upload a microcode if it's present */
410 if (ucode->code_offset)
411 qe_upload_microcode(firmware, ucode);
413 /* Program the traps for this processor */
414 for (j = 0; j < 16; j++) {
415 u32 trap = be32_to_cpu(ucode->traps[j]);
418 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
422 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
428 struct qe_firmware_info *qe_get_firmware_info(void)
430 return qe_firmware_uploaded ? &qe_firmware_info : NULL;
433 static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
442 if (strcmp(argv[1], "fw") == 0) {
443 addr = simple_strtoul(argv[2], NULL, 16);
446 printf("Invalid address\n");
451 * If a length was supplied, compare that with the 'length'
456 ulong length = simple_strtoul(argv[3], NULL, 16);
457 struct qe_firmware *firmware = (void *) addr;
459 if (length != be32_to_cpu(firmware->header.length)) {
460 printf("Length mismatch\n");
465 return qe_upload_firmware((const struct qe_firmware *) addr);
474 "QUICC Engine commands",
475 "fw <addr> [<length>] - Upload firmware binary at address <addr> to "
476 "the QE,\n\twith optional length <length> verification.\n"