1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
5 * Dave Liu <daveliu@freescale.com>
6 * based on source code of Shlomi Gridish
12 #include <linux/errno.h>
14 #include <linux/immap_qe.h>
18 #ifdef CONFIG_ARCH_LS1021A
19 #include <asm/arch/immap_ls102xa.h>
22 #include <asm/armv8/mmu.h>
23 #include <asm/arch/cpu.h>
26 #define MPC85xx_DEVDISR_QE_DISABLE 0x1
28 qe_map_t *qe_immr = NULL;
30 static qe_snum_t snums[QE_NUM_OF_SNUM];
33 DECLARE_GLOBAL_DATA_PTR;
35 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
39 if (cmd == QE_RESET) {
40 out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
42 out_be32(&qe_immr->cp.cecdr, cmd_data);
43 out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
44 ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
46 /* Wait for the QE_CR_FLG to clear */
48 cecr = in_be32(&qe_immr->cp.cecr);
49 } while (cecr & QE_CR_FLG);
55 uint qe_muram_alloc(uint size, uint align)
61 align_mask = align - 1;
62 savebase = gd->arch.mp_alloc_base;
64 off = gd->arch.mp_alloc_base & align_mask;
66 gd->arch.mp_alloc_base += (align - off);
68 if ((off = size & align_mask) != 0)
69 size += (align - off);
71 if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
72 gd->arch.mp_alloc_base = savebase;
73 printf("%s: ran out of ram.\n", __FUNCTION__);
76 retloc = gd->arch.mp_alloc_base;
77 gd->arch.mp_alloc_base += size;
79 memset((void *)&qe_immr->muram[retloc], 0, size);
81 __asm__ __volatile__("sync");
87 void *qe_muram_addr(uint offset)
89 return (void *)&qe_immr->muram[offset];
93 static void qe_sdma_init(void)
96 uint sdma_buffer_base;
98 p = (volatile sdma_t *)&qe_immr->sdma;
100 /* All of DMA transaction in bus 1 */
101 out_be32(&p->sdaqr, 0);
102 out_be32(&p->sdaqmr, 0);
104 /* Allocate 2KB temporary buffer for sdma */
105 sdma_buffer_base = qe_muram_alloc(2048, 4096);
106 out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
108 /* Clear sdma status */
109 out_be32(&p->sdsr, 0x03000000);
111 /* Enable global mode on bus 1, and 2KB buffer size */
112 out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
115 /* This table is a list of the serial numbers of the Threads, taken from the
116 * "SNUM Table" chart in the QE Reference Manual. The order is not important,
117 * we just need to know what the SNUMs are for the threads.
119 static u8 thread_snum[] = {
120 /* Evthreads 16-29 are not supported in MPC8309 */
121 #if !defined(CONFIG_ARCH_MPC8309)
122 0x04, 0x05, 0x0c, 0x0d,
123 0x14, 0x15, 0x1c, 0x1d,
124 0x24, 0x25, 0x2c, 0x2d,
127 0x88, 0x89, 0x98, 0x99,
128 0xa8, 0xa9, 0xb8, 0xb9,
129 0xc8, 0xc9, 0xd8, 0xd9,
130 0xe8, 0xe9, 0x08, 0x09,
131 0x18, 0x19, 0x28, 0x29,
132 0x38, 0x39, 0x48, 0x49,
133 0x58, 0x59, 0x68, 0x69,
134 0x78, 0x79, 0x80, 0x81
137 static void qe_snums_init(void)
141 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
142 snums[i].state = QE_SNUM_STATE_FREE;
143 snums[i].num = thread_snum[i];
147 int qe_get_snum(void)
152 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
153 if (snums[i].state == QE_SNUM_STATE_FREE) {
154 snums[i].state = QE_SNUM_STATE_USED;
163 void qe_put_snum(u8 snum)
167 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
168 if (snums[i].num == snum) {
169 snums[i].state = QE_SNUM_STATE_FREE;
175 #ifdef CONFIG_TFABOOT
176 void qe_init(uint qe_base)
178 enum boot_src src = get_boot_src();
180 /* Init the QE IMMR base */
181 qe_immr = (qe_map_t *)qe_base;
183 if (src == BOOT_SOURCE_IFC_NOR) {
185 * Upload microcode to IRAM for those SOCs
186 * which do not have ROM in QE.
188 qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
189 CONFIG_SYS_FSL_IFC_BASE));
191 /* enable the microcode in IRAM */
192 out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
195 gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
196 gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
202 void qe_init(uint qe_base)
204 /* Init the QE IMMR base */
205 qe_immr = (qe_map_t *)qe_base;
207 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR
209 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
211 qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
213 /* enable the microcode in IRAM */
214 out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
217 gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
218 gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
227 #ifdef CONFIG_TFABOOT
230 enum boot_src src = get_boot_src();
232 qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
234 void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
236 if (src == BOOT_SOURCE_IFC_NOR)
237 addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE);
239 if (src == BOOT_SOURCE_QSPI_NOR)
240 addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE);
242 if (src == BOOT_SOURCE_SD_MMC) {
243 int dev = CONFIG_SYS_MMC_ENV_DEV;
244 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
245 u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
247 if (mmc_initialize(gd->bd)) {
248 printf("%s: mmc_initialize() failed\n", __func__);
251 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
252 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
256 printf("\nMMC cannot find device for ucode\n");
258 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
261 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
265 if (!u_qe_upload_firmware(addr))
266 out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
267 if (src == BOOT_SOURCE_SD_MMC)
273 qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
275 void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
276 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
277 int dev = CONFIG_SYS_MMC_ENV_DEV;
278 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
279 u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
281 if (mmc_initialize(gd->bd)) {
282 printf("%s: mmc_initialize() failed\n", __func__);
285 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
286 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
290 printf("\nMMC cannot find device for ucode\n");
292 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
295 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
299 if (!u_qe_upload_firmware(addr))
300 out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
301 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
309 void u_qe_resume(void)
313 qe_immrr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
314 u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr);
315 out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);
321 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
322 (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
326 void qe_assign_page(uint snum, uint para_ram_base)
330 out_be32(&qe_immr->cp.cecdr, para_ram_base);
331 out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
332 | QE_CR_FLG | QE_ASSIGN_PAGE);
334 /* Wait for the QE_CR_FLG to clear */
336 cecr = in_be32(&qe_immr->cp.cecr);
337 } while (cecr & QE_CR_FLG );
344 * brg: 0~15 as BRG1~BRG16
346 * BRG input clock comes from the BRGCLK (internal clock generated from
347 the QE clock, it is one-half of the QE clock), If need the clock source
348 from CLKn pin, we have te change the function.
351 #define BRG_CLK (gd->arch.brg_clk)
354 int qe_set_brg(uint brg, uint rate)
360 if (brg >= QE_NUM_OF_BRGS)
362 bp = (uint *)&qe_immr->brg.brgc1;
365 divisor = (BRG_CLK / rate);
366 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
371 *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
372 __asm__ __volatile__("sync");
375 *bp |= QE_BRGC_DIV16;
376 __asm__ __volatile__("sync");
383 /* Set ethernet MII clock master
385 int qe_set_mii_clk_src(int ucc_num)
389 /* check if the UCC number is in range. */
390 if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
391 printf("%s: ucc num not in ranges\n", __FUNCTION__);
395 cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
396 cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
397 cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
398 out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
403 /* Firmware information stored here for qe_get_firmware_info() */
404 static struct qe_firmware_info qe_firmware_info;
407 * Set to 1 if QE firmware has been uploaded, and therefore
408 * qe_firmware_info contains valid data.
410 static int qe_firmware_uploaded;
413 * Upload a QE microcode
415 * This function is a worker function for qe_upload_firmware(). It does
416 * the actual uploading of the microcode.
418 static void qe_upload_microcode(const void *base,
419 const struct qe_microcode *ucode)
421 const u32 *code = base + be32_to_cpu(ucode->code_offset);
424 if (ucode->major || ucode->minor || ucode->revision)
425 printf("QE: uploading microcode '%s' version %u.%u.%u\n",
426 (char *)ucode->id, (u16)ucode->major, (u16)ucode->minor,
427 (u16)ucode->revision);
429 printf("QE: uploading microcode '%s'\n", (char *)ucode->id);
431 /* Use auto-increment */
432 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
433 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
435 for (i = 0; i < be32_to_cpu(ucode->count); i++)
436 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
440 * Upload a microcode to the I-RAM at a specific address.
442 * See docs/README.qe_firmware for information on QE microcode uploading.
444 * Currently, only version 1 is supported, so the 'version' field must be
447 * The SOC model and revision are not validated, they are only displayed for
448 * informational purposes.
450 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
451 * all of the microcode structures, minus the CRC.
453 * 'length' is the size that the structure says it is, including the CRC.
455 int qe_upload_firmware(const struct qe_firmware *firmware)
460 size_t calc_size = sizeof(struct qe_firmware);
462 const struct qe_header *hdr;
463 #ifdef CONFIG_DEEP_SLEEP
464 #ifdef CONFIG_ARCH_LS1021A
465 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
467 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
471 printf("Invalid address\n");
475 hdr = &firmware->header;
476 length = be32_to_cpu(hdr->length);
478 /* Check the magic */
479 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
480 (hdr->magic[2] != 'F')) {
481 printf("QE microcode not found\n");
482 #ifdef CONFIG_DEEP_SLEEP
483 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
488 /* Check the version */
489 if (hdr->version != 1) {
490 printf("Unsupported version\n");
494 /* Validate some of the fields */
495 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
496 printf("Invalid data\n");
500 /* Validate the length and check if there's a CRC */
501 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
503 for (i = 0; i < firmware->count; i++)
505 * For situations where the second RISC uses the same microcode
506 * as the first, the 'code_offset' and 'count' fields will be
507 * zero, so it's okay to add those.
509 calc_size += sizeof(u32) *
510 be32_to_cpu(firmware->microcode[i].count);
512 /* Validate the length */
513 if (length != calc_size + sizeof(u32)) {
514 printf("Invalid length\n");
519 * Validate the CRC. We would normally call crc32_no_comp(), but that
520 * function isn't available unless you turn on JFFS support.
522 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
523 if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
524 printf("Firmware CRC is invalid\n");
529 * If the microcode calls for it, split the I-RAM.
531 if (!firmware->split) {
532 out_be16(&qe_immr->cp.cercr,
533 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
536 if (firmware->soc.model)
537 printf("Firmware '%s' for %u V%u.%u\n",
538 firmware->id, be16_to_cpu(firmware->soc.model),
539 firmware->soc.major, firmware->soc.minor);
541 printf("Firmware '%s'\n", firmware->id);
544 * The QE only supports one microcode per RISC, so clear out all the
545 * saved microcode information and put in the new.
547 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
548 strncpy(qe_firmware_info.id, (char *)firmware->id, 62);
549 qe_firmware_info.extended_modes = firmware->extended_modes;
550 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
551 sizeof(firmware->vtraps));
552 qe_firmware_uploaded = 1;
554 /* Loop through each microcode. */
555 for (i = 0; i < firmware->count; i++) {
556 const struct qe_microcode *ucode = &firmware->microcode[i];
558 /* Upload a microcode if it's present */
559 if (ucode->code_offset)
560 qe_upload_microcode(firmware, ucode);
562 /* Program the traps for this processor */
563 for (j = 0; j < 16; j++) {
564 u32 trap = be32_to_cpu(ucode->traps[j]);
567 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
571 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
579 * Upload a microcode to the I-RAM at a specific address.
581 * See docs/README.qe_firmware for information on QE microcode uploading.
583 * Currently, only version 1 is supported, so the 'version' field must be
586 * The SOC model and revision are not validated, they are only displayed for
587 * informational purposes.
589 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
590 * all of the microcode structures, minus the CRC.
592 * 'length' is the size that the structure says it is, including the CRC.
594 int u_qe_upload_firmware(const struct qe_firmware *firmware)
599 size_t calc_size = sizeof(struct qe_firmware);
601 const struct qe_header *hdr;
602 #ifdef CONFIG_DEEP_SLEEP
603 #ifdef CONFIG_ARCH_LS1021A
604 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
606 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
610 printf("Invalid address\n");
614 hdr = &firmware->header;
615 length = be32_to_cpu(hdr->length);
617 /* Check the magic */
618 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
619 (hdr->magic[2] != 'F')) {
620 printf("Not a microcode\n");
621 #ifdef CONFIG_DEEP_SLEEP
622 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
627 /* Check the version */
628 if (hdr->version != 1) {
629 printf("Unsupported version\n");
633 /* Validate some of the fields */
634 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
635 printf("Invalid data\n");
639 /* Validate the length and check if there's a CRC */
640 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
642 for (i = 0; i < firmware->count; i++)
644 * For situations where the second RISC uses the same microcode
645 * as the first, the 'code_offset' and 'count' fields will be
646 * zero, so it's okay to add those.
648 calc_size += sizeof(u32) *
649 be32_to_cpu(firmware->microcode[i].count);
651 /* Validate the length */
652 if (length != calc_size + sizeof(u32)) {
653 printf("Invalid length\n");
658 * Validate the CRC. We would normally call crc32_no_comp(), but that
659 * function isn't available unless you turn on JFFS support.
661 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
662 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
663 printf("Firmware CRC is invalid\n");
668 * If the microcode calls for it, split the I-RAM.
670 if (!firmware->split) {
671 out_be16(&qe_immr->cp.cercr,
672 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
675 if (firmware->soc.model)
676 printf("Firmware '%s' for %u V%u.%u\n",
677 firmware->id, be16_to_cpu(firmware->soc.model),
678 firmware->soc.major, firmware->soc.minor);
680 printf("Firmware '%s'\n", firmware->id);
682 /* Loop through each microcode. */
683 for (i = 0; i < firmware->count; i++) {
684 const struct qe_microcode *ucode = &firmware->microcode[i];
686 /* Upload a microcode if it's present */
687 if (ucode->code_offset)
688 qe_upload_microcode(firmware, ucode);
690 /* Program the traps for this processor */
691 for (j = 0; j < 16; j++) {
692 u32 trap = be32_to_cpu(ucode->traps[j]);
695 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
699 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
707 int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
711 const struct qe_header *hdr;
713 #ifdef CONFIG_DEEP_SLEEP
715 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
717 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
724 hdr = &firmware->header;
726 /* Check the magic */
727 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
728 (hdr->magic[2] != 'F')) {
729 #ifdef CONFIG_DEEP_SLEEP
730 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
736 * If the microcode calls for it, split the I-RAM.
738 if (!firmware->split) {
739 out_be16(&qe_immrr->cp.cercr,
740 in_be16(&qe_immrr->cp.cercr) | QE_CP_CERCR_CIR);
743 /* Loop through each microcode. */
744 for (i = 0; i < firmware->count; i++) {
745 const struct qe_microcode *ucode = &firmware->microcode[i];
747 /* Upload a microcode if it's present */
748 if (!ucode->code_offset)
751 code = (const void *)firmware + be32_to_cpu(ucode->code_offset);
753 /* Use auto-increment */
754 out_be32(&qe_immrr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
755 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
757 for (i = 0; i < be32_to_cpu(ucode->count); i++)
758 out_be32(&qe_immrr->iram.idata, be32_to_cpu(code[i]));
760 /* Program the traps for this processor */
761 for (j = 0; j < 16; j++) {
762 u32 trap = be32_to_cpu(ucode->traps[j]);
765 out_be32(&qe_immrr->rsp[i].tibcr[j], trap);
769 out_be32(&qe_immrr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
776 struct qe_firmware_info *qe_get_firmware_info(void)
778 return qe_firmware_uploaded ? &qe_firmware_info : NULL;
781 static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
786 return cmd_usage(cmdtp);
788 if (strcmp(argv[1], "fw") == 0) {
789 addr = simple_strtoul(argv[2], NULL, 16);
792 printf("Invalid address\n");
797 * If a length was supplied, compare that with the 'length'
802 ulong length = simple_strtoul(argv[3], NULL, 16);
803 struct qe_firmware *firmware = (void *) addr;
805 if (length != be32_to_cpu(firmware->header.length)) {
806 printf("Length mismatch\n");
811 return qe_upload_firmware((const struct qe_firmware *) addr);
814 return cmd_usage(cmdtp);
819 "QUICC Engine commands",
820 "fw <addr> [<length>] - Upload firmware binary at address <addr> to "
822 "\twith optional length <length> verification."