1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
16 #include <asm/arch-rockchip/pwm.h>
17 #include <linux/bitops.h>
18 #include <power/regulator.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 struct rockchip_pwm_data {
23 struct rockchip_pwm_regs regs;
24 unsigned int prescaler;
25 bool supports_polarity;
35 const struct rockchip_pwm_data *data;
38 static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
40 struct rk_pwm_priv *priv = dev_get_priv(dev);
42 if (!priv->data->supports_polarity) {
43 debug("%s: Do not support polarity\n", __func__);
47 debug("%s: polarity=%u\n", __func__, polarity);
49 priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
51 priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
56 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
59 struct rk_pwm_priv *priv = dev_get_priv(dev);
60 const struct rockchip_pwm_regs *regs = &priv->data->regs;
61 unsigned long period, duty;
64 debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
66 ctrl = readl(priv->base + regs->ctrl);
68 * Lock the period and duty of previous configuration, then
69 * change the duty and period, that would not be effective.
71 if (priv->data->supports_lock) {
73 writel(ctrl, priv->base + regs->ctrl);
76 period = lldiv((uint64_t)priv->freq * period_ns,
77 priv->data->prescaler * 1000000000);
78 duty = lldiv((uint64_t)priv->freq * duty_ns,
79 priv->data->prescaler * 1000000000);
81 writel(period, priv->base + regs->period);
82 writel(duty, priv->base + regs->duty);
84 if (priv->data->supports_polarity) {
85 ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
86 ctrl |= priv->conf_polarity;
90 * Unlock and set polarity at the same time,
91 * the configuration of duty, period and polarity
92 * would be effective together at next period.
94 if (priv->data->supports_lock)
96 writel(ctrl, priv->base + regs->ctrl);
98 debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
103 static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
105 struct rk_pwm_priv *priv = dev_get_priv(dev);
106 const struct rockchip_pwm_regs *regs = &priv->data->regs;
109 debug("%s: Enable '%s'\n", __func__, dev->name);
111 ctrl = readl(priv->base + regs->ctrl);
112 ctrl &= ~priv->data->enable_conf_mask;
115 ctrl |= priv->data->enable_conf;
117 ctrl &= ~priv->data->enable_conf;
119 writel(ctrl, priv->base + regs->ctrl);
124 static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
126 struct rk_pwm_priv *priv = dev_get_priv(dev);
128 priv->base = dev_read_addr(dev);
133 static int rk_pwm_probe(struct udevice *dev)
135 struct rk_pwm_priv *priv = dev_get_priv(dev);
139 ret = clk_get_by_index(dev, 0, &clk);
141 debug("%s get clock fail!\n", __func__);
145 priv->freq = clk_get_rate(&clk);
146 priv->data = (struct rockchip_pwm_data *)dev_get_driver_data(dev);
148 if (priv->data->supports_polarity)
149 priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
154 static const struct pwm_ops rk_pwm_ops = {
155 .set_invert = rk_pwm_set_invert,
156 .set_config = rk_pwm_set_config,
157 .set_enable = rk_pwm_set_enable,
160 static const struct rockchip_pwm_data pwm_data_v1 = {
168 .supports_polarity = false,
169 .supports_lock = false,
170 .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
171 .enable_conf_mask = BIT(1) | BIT(3),
174 static const struct rockchip_pwm_data pwm_data_v2 = {
182 .supports_polarity = true,
183 .supports_lock = false,
184 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
186 .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
189 static const struct rockchip_pwm_data pwm_data_v3 = {
197 .supports_polarity = true,
198 .supports_lock = true,
199 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
201 .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
204 static const struct udevice_id rk_pwm_ids[] = {
205 { .compatible = "rockchip,rk2928-pwm", .data = (ulong)&pwm_data_v1},
206 { .compatible = "rockchip,rk3288-pwm", .data = (ulong)&pwm_data_v2},
207 { .compatible = "rockchip,rk3328-pwm", .data = (ulong)&pwm_data_v3},
211 U_BOOT_DRIVER(rk_pwm) = {
214 .of_match = rk_pwm_ids,
216 .ofdata_to_platdata = rk_pwm_ofdata_to_platdata,
217 .probe = rk_pwm_probe,
218 .priv_auto_alloc_size = sizeof(struct rk_pwm_priv),