dm: core: Introduce dev_read_alias_highest_id()
[oweals/u-boot.git] / drivers / pwm / rk_pwm.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (c) 2016 Google, Inc
4  * Written by Simon Glass <sjg@chromium.org>
5  */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <div64.h>
10 #include <dm.h>
11 #include <pwm.h>
12 #include <regmap.h>
13 #include <syscon.h>
14 #include <asm/io.h>
15 #include <asm/arch/pwm.h>
16 #include <power/regulator.h>
17
18 struct rk_pwm_priv {
19         struct rk3288_pwm *regs;
20         ulong freq;
21         uint enable_conf;
22 };
23
24 static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
25 {
26         struct rk_pwm_priv *priv = dev_get_priv(dev);
27
28         debug("%s: polarity=%u\n", __func__, polarity);
29         priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
30         if (polarity)
31                 priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
32         else
33                 priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
34
35         return 0;
36 }
37
38 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
39                              uint duty_ns)
40 {
41         struct rk_pwm_priv *priv = dev_get_priv(dev);
42         struct rk3288_pwm *regs = priv->regs;
43         unsigned long period, duty;
44
45         debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
46         writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
47                 PWM_CONTINUOUS | priv->enable_conf |
48                 RK_PWM_DISABLE,
49                 &regs->ctrl);
50
51         period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
52         duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
53
54         writel(period, &regs->period_hpr);
55         writel(duty, &regs->duty_lpr);
56         debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
57
58         return 0;
59 }
60
61 static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
62 {
63         struct rk_pwm_priv *priv = dev_get_priv(dev);
64         struct rk3288_pwm *regs = priv->regs;
65
66         debug("%s: Enable '%s'\n", __func__, dev->name);
67         clrsetbits_le32(&regs->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
68
69         return 0;
70 }
71
72 static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
73 {
74         struct rk_pwm_priv *priv = dev_get_priv(dev);
75
76         priv->regs = (struct rk3288_pwm *)dev_read_addr(dev);
77
78         return 0;
79 }
80
81 static int rk_pwm_probe(struct udevice *dev)
82 {
83         struct rk_pwm_priv *priv = dev_get_priv(dev);
84         struct clk clk;
85         int ret = 0;
86
87         ret = clk_get_by_index(dev, 0, &clk);
88         if (ret < 0) {
89                 debug("%s get clock fail!\n", __func__);
90                 return -EINVAL;
91         }
92         priv->freq = clk_get_rate(&clk);
93         priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
94
95         return 0;
96 }
97
98 static const struct pwm_ops rk_pwm_ops = {
99         .set_invert     = rk_pwm_set_invert,
100         .set_config     = rk_pwm_set_config,
101         .set_enable     = rk_pwm_set_enable,
102 };
103
104 static const struct udevice_id rk_pwm_ids[] = {
105         { .compatible = "rockchip,rk3288-pwm" },
106         { }
107 };
108
109 U_BOOT_DRIVER(rk_pwm) = {
110         .name   = "rk_pwm",
111         .id     = UCLASS_PWM,
112         .of_match = rk_pwm_ids,
113         .ops    = &rk_pwm_ops,
114         .ofdata_to_platdata     = rk_pwm_ofdata_to_platdata,
115         .probe          = rk_pwm_probe,
116         .priv_auto_alloc_size   = sizeof(struct rk_pwm_priv),
117 };