1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
15 #include <asm/arch-rockchip/pwm.h>
16 #include <power/regulator.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 struct rockchip_pwm_data {
21 struct rockchip_pwm_regs regs;
22 unsigned int prescaler;
23 bool supports_polarity;
33 const struct rockchip_pwm_data *data;
36 static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
38 struct rk_pwm_priv *priv = dev_get_priv(dev);
40 if (!priv->data->supports_polarity) {
41 debug("%s: Do not support polarity\n", __func__);
45 debug("%s: polarity=%u\n", __func__, polarity);
47 priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
49 priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
54 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
57 struct rk_pwm_priv *priv = dev_get_priv(dev);
58 const struct rockchip_pwm_regs *regs = &priv->data->regs;
59 unsigned long period, duty;
62 debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
64 ctrl = readl(priv->base + regs->ctrl);
66 * Lock the period and duty of previous configuration, then
67 * change the duty and period, that would not be effective.
69 if (priv->data->supports_lock) {
71 writel(ctrl, priv->base + regs->ctrl);
74 period = lldiv((uint64_t)priv->freq * period_ns,
75 priv->data->prescaler * 1000000000);
76 duty = lldiv((uint64_t)priv->freq * duty_ns,
77 priv->data->prescaler * 1000000000);
79 writel(period, priv->base + regs->period);
80 writel(duty, priv->base + regs->duty);
82 if (priv->data->supports_polarity) {
83 ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
84 ctrl |= priv->conf_polarity;
88 * Unlock and set polarity at the same time,
89 * the configuration of duty, period and polarity
90 * would be effective together at next period.
92 if (priv->data->supports_lock)
94 writel(ctrl, priv->base + regs->ctrl);
96 debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
101 static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
103 struct rk_pwm_priv *priv = dev_get_priv(dev);
104 const struct rockchip_pwm_regs *regs = &priv->data->regs;
107 debug("%s: Enable '%s'\n", __func__, dev->name);
109 ctrl = readl(priv->base + regs->ctrl);
110 ctrl &= ~priv->data->enable_conf_mask;
113 ctrl |= priv->data->enable_conf;
115 ctrl &= ~priv->data->enable_conf;
117 writel(ctrl, priv->base + regs->ctrl);
122 static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
124 struct rk_pwm_priv *priv = dev_get_priv(dev);
126 priv->base = dev_read_addr(dev);
131 static int rk_pwm_probe(struct udevice *dev)
133 struct rk_pwm_priv *priv = dev_get_priv(dev);
137 ret = clk_get_by_index(dev, 0, &clk);
139 debug("%s get clock fail!\n", __func__);
143 priv->freq = clk_get_rate(&clk);
144 priv->data = (struct rockchip_pwm_data *)dev_get_driver_data(dev);
146 if (priv->data->supports_polarity)
147 priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
152 static const struct pwm_ops rk_pwm_ops = {
153 .set_invert = rk_pwm_set_invert,
154 .set_config = rk_pwm_set_config,
155 .set_enable = rk_pwm_set_enable,
158 static const struct rockchip_pwm_data pwm_data_v1 = {
166 .supports_polarity = false,
167 .supports_lock = false,
168 .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
169 .enable_conf_mask = BIT(1) | BIT(3),
172 static const struct rockchip_pwm_data pwm_data_v2 = {
180 .supports_polarity = true,
181 .supports_lock = false,
182 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
184 .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
187 static const struct rockchip_pwm_data pwm_data_v3 = {
195 .supports_polarity = true,
196 .supports_lock = true,
197 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
199 .enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
202 static const struct udevice_id rk_pwm_ids[] = {
203 { .compatible = "rockchip,rk2928-pwm", .data = (ulong)&pwm_data_v1},
204 { .compatible = "rockchip,rk3288-pwm", .data = (ulong)&pwm_data_v2},
205 { .compatible = "rockchip,rk3328-pwm", .data = (ulong)&pwm_data_v3},
209 U_BOOT_DRIVER(rk_pwm) = {
212 .of_match = rk_pwm_ids,
214 .ofdata_to_platdata = rk_pwm_ofdata_to_platdata,
215 .probe = rk_pwm_probe,
216 .priv_auto_alloc_size = sizeof(struct rk_pwm_priv),