drivers/power/supply/pm2301_charger.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) ST-Ericsson SA 2012
   4  *
   5  * PM2301 power supply interface
   6  */
   7
   8 #ifndef PM2301_CHARGER_H
   9 #define PM2301_CHARGER_H
  10
  11 /* Watchdog timeout constant */
  12 #define WD_TIMER                        0x30 /* 4min */
  13 #define WD_KICK_INTERVAL                (30 * HZ)
  14
  15 #define PM2XXX_NUM_INT_REG              0x6
  16
  17 /* Constant voltage/current */
  18 #define PM2XXX_CONST_CURR               0x0
  19 #define PM2XXX_CONST_VOLT               0x1
  20
  21 /* Lowest charger voltage is 3.39V -> 0x4E */
  22 #define LOW_VOLT_REG                    0x4E
  23
  24 #define PM2XXX_BATT_CTRL_REG1           0x00
  25 #define PM2XXX_BATT_CTRL_REG2           0x01
  26 #define PM2XXX_BATT_CTRL_REG3           0x02
  27 #define PM2XXX_BATT_CTRL_REG4           0x03
  28 #define PM2XXX_BATT_CTRL_REG5           0x04
  29 #define PM2XXX_BATT_CTRL_REG6           0x05
  30 #define PM2XXX_BATT_CTRL_REG7           0x06
  31 #define PM2XXX_BATT_CTRL_REG8           0x07
  32 #define PM2XXX_NTC_CTRL_REG1            0x08
  33 #define PM2XXX_NTC_CTRL_REG2            0x09
  34 #define PM2XXX_BATT_CTRL_REG9           0x0A
  35 #define PM2XXX_BATT_STAT_REG1           0x0B
  36 #define PM2XXX_INP_VOLT_VPWR2           0x11
  37 #define PM2XXX_INP_DROP_VPWR2           0x13
  38 #define PM2XXX_INP_VOLT_VPWR1           0x15
  39 #define PM2XXX_INP_DROP_VPWR1           0x17
  40 #define PM2XXX_INP_MODE_VPWR            0x18
  41 #define PM2XXX_BATT_WD_KICK             0x70
  42 #define PM2XXX_DEV_VER_STAT             0x0C
  43 #define PM2XXX_THERM_WARN_CTRL_REG      0x20
  44 #define PM2XXX_BATT_DISC_REG            0x21
  45 #define PM2XXX_BATT_LOW_LEV_COMP_REG    0x22
  46 #define PM2XXX_BATT_LOW_LEV_VAL_REG     0x23
  47 #define PM2XXX_I2C_PAD_CTRL_REG         0x24
  48 #define PM2XXX_SW_CTRL_REG              0x26
  49 #define PM2XXX_LED_CTRL_REG             0x28
  50
  51 #define PM2XXX_REG_INT1                 0x40
  52 #define PM2XXX_MASK_REG_INT1            0x50
  53 #define PM2XXX_SRCE_REG_INT1            0x60
  54 #define PM2XXX_REG_INT2                 0x41
  55 #define PM2XXX_MASK_REG_INT2            0x51
  56 #define PM2XXX_SRCE_REG_INT2            0x61
  57 #define PM2XXX_REG_INT3                 0x42
  58 #define PM2XXX_MASK_REG_INT3            0x52
  59 #define PM2XXX_SRCE_REG_INT3            0x62
  60 #define PM2XXX_REG_INT4                 0x43
  61 #define PM2XXX_MASK_REG_INT4            0x53
  62 #define PM2XXX_SRCE_REG_INT4            0x63
  63 #define PM2XXX_REG_INT5                 0x44
  64 #define PM2XXX_MASK_REG_INT5            0x54
  65 #define PM2XXX_SRCE_REG_INT5            0x64
  66 #define PM2XXX_REG_INT6                 0x45
  67 #define PM2XXX_MASK_REG_INT6            0x55
  68 #define PM2XXX_SRCE_REG_INT6            0x65
  69
  70 #define VPWR_OVV                        0x0
  71 #define VSYSTEM_OVV                     0x1
  72
  73 /* control Reg 1 */
  74 #define PM2XXX_CH_RESUME_EN             0x1
  75 #define PM2XXX_CH_RESUME_DIS            0x0
  76
  77 /* control Reg 2 */
  78 #define PM2XXX_CH_AUTO_RESUME_EN        0X2
  79 #define PM2XXX_CH_AUTO_RESUME_DIS       0X0
  80 #define PM2XXX_CHARGER_ENA              0x4
  81 #define PM2XXX_CHARGER_DIS              0x0
  82
  83 /* control Reg 3 */
  84 #define PM2XXX_CH_WD_CC_PHASE_OFF       0x0
  85 #define PM2XXX_CH_WD_CC_PHASE_5MIN      0x1
  86 #define PM2XXX_CH_WD_CC_PHASE_10MIN     0x2
  87 #define PM2XXX_CH_WD_CC_PHASE_30MIN     0x3
  88 #define PM2XXX_CH_WD_CC_PHASE_60MIN     0x4
  89 #define PM2XXX_CH_WD_CC_PHASE_120MIN    0x5
  90 #define PM2XXX_CH_WD_CC_PHASE_240MIN    0x6
  91 #define PM2XXX_CH_WD_CC_PHASE_360MIN    0x7
  92
  93 #define PM2XXX_CH_WD_CV_PHASE_OFF       (0x0<<3)
  94 #define PM2XXX_CH_WD_CV_PHASE_5MIN      (0x1<<3)
  95 #define PM2XXX_CH_WD_CV_PHASE_10MIN     (0x2<<3)
  96 #define PM2XXX_CH_WD_CV_PHASE_30MIN     (0x3<<3)
  97 #define PM2XXX_CH_WD_CV_PHASE_60MIN     (0x4<<3)
  98 #define PM2XXX_CH_WD_CV_PHASE_120MIN    (0x5<<3)
  99 #define PM2XXX_CH_WD_CV_PHASE_240MIN    (0x6<<3)
 100 #define PM2XXX_CH_WD_CV_PHASE_360MIN    (0x7<<3)
 101
 102 /* control Reg 4 */
 103 #define PM2XXX_CH_WD_PRECH_PHASE_OFF    0x0
 104 #define PM2XXX_CH_WD_PRECH_PHASE_1MIN   0x1
 105 #define PM2XXX_CH_WD_PRECH_PHASE_5MIN   0x2
 106 #define PM2XXX_CH_WD_PRECH_PHASE_10MIN  0x3
 107 #define PM2XXX_CH_WD_PRECH_PHASE_30MIN  0x4
 108 #define PM2XXX_CH_WD_PRECH_PHASE_60MIN  0x5
 109 #define PM2XXX_CH_WD_PRECH_PHASE_120MIN 0x6
 110 #define PM2XXX_CH_WD_PRECH_PHASE_240MIN 0x7
 111
 112 /* control Reg 5 */
 113 #define PM2XXX_CH_WD_AUTO_TIMEOUT_NONE  0x0
 114 #define PM2XXX_CH_WD_AUTO_TIMEOUT_20MIN 0x1
 115
 116 /* control Reg 6 */
 117 #define PM2XXX_DIR_CH_CC_CURRENT_MASK   0x0F
 118 #define PM2XXX_DIR_CH_CC_CURRENT_200MA  0x0
 119 #define PM2XXX_DIR_CH_CC_CURRENT_400MA  0x2
 120 #define PM2XXX_DIR_CH_CC_CURRENT_600MA  0x3
 121 #define PM2XXX_DIR_CH_CC_CURRENT_800MA  0x4
 122 #define PM2XXX_DIR_CH_CC_CURRENT_1000MA 0x5
 123 #define PM2XXX_DIR_CH_CC_CURRENT_1200MA 0x6
 124 #define PM2XXX_DIR_CH_CC_CURRENT_1400MA 0x7
 125 #define PM2XXX_DIR_CH_CC_CURRENT_1600MA 0x8
 126 #define PM2XXX_DIR_CH_CC_CURRENT_1800MA 0x9
 127 #define PM2XXX_DIR_CH_CC_CURRENT_2000MA 0xA
 128 #define PM2XXX_DIR_CH_CC_CURRENT_2200MA 0xB
 129 #define PM2XXX_DIR_CH_CC_CURRENT_2400MA 0xC
 130 #define PM2XXX_DIR_CH_CC_CURRENT_2600MA 0xD
 131 #define PM2XXX_DIR_CH_CC_CURRENT_2800MA 0xE
 132 #define PM2XXX_DIR_CH_CC_CURRENT_3000MA 0xF
 133
 134 #define PM2XXX_CH_PRECH_CURRENT_MASK    0x30
 135 #define PM2XXX_CH_PRECH_CURRENT_25MA    (0x0<<4)
 136 #define PM2XXX_CH_PRECH_CURRENT_50MA    (0x1<<4)
 137 #define PM2XXX_CH_PRECH_CURRENT_75MA    (0x2<<4)
 138 #define PM2XXX_CH_PRECH_CURRENT_100MA   (0x3<<4)
 139
 140 #define PM2XXX_CH_EOC_CURRENT_MASK      0xC0
 141 #define PM2XXX_CH_EOC_CURRENT_100MA     (0x0<<6)
 142 #define PM2XXX_CH_EOC_CURRENT_150MA     (0x1<<6)
 143 #define PM2XXX_CH_EOC_CURRENT_300MA     (0x2<<6)
 144 #define PM2XXX_CH_EOC_CURRENT_400MA     (0x3<<6)
 145
 146 /* control Reg 7 */
 147 #define PM2XXX_CH_PRECH_VOL_2_5         0x0
 148 #define PM2XXX_CH_PRECH_VOL_2_7         0x1
 149 #define PM2XXX_CH_PRECH_VOL_2_9         0x2
 150 #define PM2XXX_CH_PRECH_VOL_3_1         0x3
 151
 152 #define PM2XXX_CH_VRESUME_VOL_3_2       (0x0<<2)
 153 #define PM2XXX_CH_VRESUME_VOL_3_4       (0x1<<2)
 154 #define PM2XXX_CH_VRESUME_VOL_3_6       (0x2<<2)
 155 #define PM2XXX_CH_VRESUME_VOL_3_8       (0x3<<2)
 156
 157 /* control Reg 8 */
 158 #define PM2XXX_CH_VOLT_MASK             0x3F
 159 #define PM2XXX_CH_VOLT_3_5              0x0
 160 #define PM2XXX_CH_VOLT_3_5225           0x1
 161 #define PM2XXX_CH_VOLT_3_6              0x4
 162 #define PM2XXX_CH_VOLT_3_7              0x8
 163 #define PM2XXX_CH_VOLT_4_0              0x14
 164 #define PM2XXX_CH_VOLT_4_175            0x1B
 165 #define PM2XXX_CH_VOLT_4_2              0x1C
 166 #define PM2XXX_CH_VOLT_4_275            0x1F
 167 #define PM2XXX_CH_VOLT_4_3              0x20
 168
 169 /*NTC control register 1*/
 170 #define PM2XXX_BTEMP_HIGH_TH_45         0x0
 171 #define PM2XXX_BTEMP_HIGH_TH_50         0x1
 172 #define PM2XXX_BTEMP_HIGH_TH_55         0x2
 173 #define PM2XXX_BTEMP_HIGH_TH_60         0x3
 174 #define PM2XXX_BTEMP_HIGH_TH_65         0x4
 175
 176 #define PM2XXX_BTEMP_LOW_TH_N5          (0x0<<3)
 177 #define PM2XXX_BTEMP_LOW_TH_0           (0x1<<3)
 178 #define PM2XXX_BTEMP_LOW_TH_5           (0x2<<3)
 179 #define PM2XXX_BTEMP_LOW_TH_10          (0x3<<3)
 180
 181 /*NTC control register 2*/
 182 #define PM2XXX_NTC_BETA_COEFF_3477      0x0
 183 #define PM2XXX_NTC_BETA_COEFF_3964      0x1
 184
 185 #define PM2XXX_NTC_RES_10K              (0x0<<2)
 186 #define PM2XXX_NTC_RES_47K              (0x1<<2)
 187 #define PM2XXX_NTC_RES_100K             (0x2<<2)
 188 #define PM2XXX_NTC_RES_NO_NTC           (0x3<<2)
 189
 190 /* control Reg 9 */
 191 #define PM2XXX_CH_CC_MODEDROP_EN        1
 192 #define PM2XXX_CH_CC_MODEDROP_DIS       0
 193
 194 #define PM2XXX_CH_CC_REDUCED_CURRENT_100MA      (0x0<<1)
 195 #define PM2XXX_CH_CC_REDUCED_CURRENT_200MA      (0x1<<1)
 196 #define PM2XXX_CH_CC_REDUCED_CURRENT_400MA      (0x2<<1)
 197 #define PM2XXX_CH_CC_REDUCED_CURRENT_IDENT      (0x3<<1)
 198
 199 #define PM2XXX_CHARCHING_INFO_DIS       (0<<3)
 200 #define PM2XXX_CHARCHING_INFO_EN        (1<<3)
 201
 202 #define PM2XXX_CH_150MV_DROP_300MV      (0<<4)
 203 #define PM2XXX_CH_150MV_DROP_150MV      (1<<4)
 204
 205
 206 /* charger status register */
 207 #define PM2XXX_CHG_STATUS_OFF           0x0
 208 #define PM2XXX_CHG_STATUS_ON            0x1
 209 #define PM2XXX_CHG_STATUS_FULL          0x2
 210 #define PM2XXX_CHG_STATUS_ERR           0x3
 211 #define PM2XXX_CHG_STATUS_WAIT          0x4
 212 #define PM2XXX_CHG_STATUS_NOBAT         0x5
 213
 214 /* Input charger voltage VPWR2 */
 215 #define PM2XXX_VPWR2_OVV_6_0            0x0
 216 #define PM2XXX_VPWR2_OVV_6_3            0x1
 217 #define PM2XXX_VPWR2_OVV_10             0x2
 218 #define PM2XXX_VPWR2_OVV_NONE           0x3
 219
 220 /* Input charger drop VPWR2 */
 221 #define PM2XXX_VPWR2_HW_OPT_EN          (0x1<<4)
 222 #define PM2XXX_VPWR2_HW_OPT_DIS         (0x0<<4)
 223
 224 #define PM2XXX_VPWR2_VALID_EN           (0x1<<3)
 225 #define PM2XXX_VPWR2_VALID_DIS          (0x0<<3)
 226
 227 #define PM2XXX_VPWR2_DROP_EN            (0x1<<2)
 228 #define PM2XXX_VPWR2_DROP_DIS           (0x0<<2)
 229
 230 /* Input charger voltage VPWR1 */
 231 #define PM2XXX_VPWR1_OVV_6_0            0x0
 232 #define PM2XXX_VPWR1_OVV_6_3            0x1
 233 #define PM2XXX_VPWR1_OVV_10             0x2
 234 #define PM2XXX_VPWR1_OVV_NONE           0x3
 235
 236 /* Input charger drop VPWR1 */
 237 #define PM2XXX_VPWR1_HW_OPT_EN          (0x1<<4)
 238 #define PM2XXX_VPWR1_HW_OPT_DIS         (0x0<<4)
 239
 240 #define PM2XXX_VPWR1_VALID_EN           (0x1<<3)
 241 #define PM2XXX_VPWR1_VALID_DIS          (0x0<<3)
 242
 243 #define PM2XXX_VPWR1_DROP_EN            (0x1<<2)
 244 #define PM2XXX_VPWR1_DROP_DIS           (0x0<<2)
 245
 246 /* Battery low level comparator control register */
 247 #define PM2XXX_VBAT_LOW_MONITORING_DIS  0x0
 248 #define PM2XXX_VBAT_LOW_MONITORING_ENA  0x1
 249
 250 /* Battery low level value control register */
 251 #define PM2XXX_VBAT_LOW_LEVEL_2_3       0x0
 252 #define PM2XXX_VBAT_LOW_LEVEL_2_4       0x1
 253 #define PM2XXX_VBAT_LOW_LEVEL_2_5       0x2
 254 #define PM2XXX_VBAT_LOW_LEVEL_2_6       0x3
 255 #define PM2XXX_VBAT_LOW_LEVEL_2_7       0x4
 256 #define PM2XXX_VBAT_LOW_LEVEL_2_8       0x5
 257 #define PM2XXX_VBAT_LOW_LEVEL_2_9       0x6
 258 #define PM2XXX_VBAT_LOW_LEVEL_3_0       0x7
 259 #define PM2XXX_VBAT_LOW_LEVEL_3_1       0x8
 260 #define PM2XXX_VBAT_LOW_LEVEL_3_2       0x9
 261 #define PM2XXX_VBAT_LOW_LEVEL_3_3       0xA
 262 #define PM2XXX_VBAT_LOW_LEVEL_3_4       0xB
 263 #define PM2XXX_VBAT_LOW_LEVEL_3_5       0xC
 264 #define PM2XXX_VBAT_LOW_LEVEL_3_6       0xD
 265 #define PM2XXX_VBAT_LOW_LEVEL_3_7       0xE
 266 #define PM2XXX_VBAT_LOW_LEVEL_3_8       0xF
 267 #define PM2XXX_VBAT_LOW_LEVEL_3_9       0x10
 268 #define PM2XXX_VBAT_LOW_LEVEL_4_0       0x11
 269 #define PM2XXX_VBAT_LOW_LEVEL_4_1       0x12
 270 #define PM2XXX_VBAT_LOW_LEVEL_4_2       0x13
 271
 272 /* SW CTRL */
 273 #define PM2XXX_SWCTRL_HW                0x0
 274 #define PM2XXX_SWCTRL_SW                0x1
 275
 276
 277 /* LED Driver Control */
 278 #define PM2XXX_LED_CURRENT_MASK         0x0C
 279 #define PM2XXX_LED_CURRENT_2_5MA        (0X0<<2)
 280 #define PM2XXX_LED_CURRENT_1MA          (0X1<<2)
 281 #define PM2XXX_LED_CURRENT_5MA          (0X2<<2)
 282 #define PM2XXX_LED_CURRENT_10MA         (0X3<<2)
 283
 284 #define PM2XXX_LED_SELECT_MASK          0x02
 285 #define PM2XXX_LED_SELECT_EN            (0X0<<1)
 286 #define PM2XXX_LED_SELECT_DIS           (0X1<<1)
 287
 288 #define PM2XXX_ANTI_OVERSHOOT_MASK      0x01
 289 #define PM2XXX_ANTI_OVERSHOOT_DIS       0X0
 290 #define PM2XXX_ANTI_OVERSHOOT_EN        0X1
 291
 292 enum pm2xxx_reg_int1 {
 293         PM2XXX_INT1_ITVBATDISCONNECT    = 0x02,
 294         PM2XXX_INT1_ITVBATLOWR          = 0x04,
 295         PM2XXX_INT1_ITVBATLOWF          = 0x08,
 296 };
 297
 298 enum pm2xxx_mask_reg_int1 {
 299         PM2XXX_INT1_M_ITVBATDISCONNECT  = 0x02,
 300         PM2XXX_INT1_M_ITVBATLOWR        = 0x04,
 301         PM2XXX_INT1_M_ITVBATLOWF        = 0x08,
 302 };
 303
 304 enum pm2xxx_source_reg_int1 {
 305         PM2XXX_INT1_S_ITVBATDISCONNECT  = 0x02,
 306         PM2XXX_INT1_S_ITVBATLOWR        = 0x04,
 307         PM2XXX_INT1_S_ITVBATLOWF        = 0x08,
 308 };
 309
 310 enum pm2xxx_reg_int2 {
 311         PM2XXX_INT2_ITVPWR2PLUG         = 0x01,
 312         PM2XXX_INT2_ITVPWR2UNPLUG       = 0x02,
 313         PM2XXX_INT2_ITVPWR1PLUG         = 0x04,
 314         PM2XXX_INT2_ITVPWR1UNPLUG       = 0x08,
 315 };
 316
 317 enum pm2xxx_mask_reg_int2 {
 318         PM2XXX_INT2_M_ITVPWR2PLUG       = 0x01,
 319         PM2XXX_INT2_M_ITVPWR2UNPLUG     = 0x02,
 320         PM2XXX_INT2_M_ITVPWR1PLUG       = 0x04,
 321         PM2XXX_INT2_M_ITVPWR1UNPLUG     = 0x08,
 322 };
 323
 324 enum pm2xxx_source_reg_int2 {
 325         PM2XXX_INT2_S_ITVPWR2PLUG       = 0x03,
 326         PM2XXX_INT2_S_ITVPWR1PLUG       = 0x0c,
 327 };
 328
 329 enum pm2xxx_reg_int3 {
 330         PM2XXX_INT3_ITCHPRECHARGEWD     = 0x01,
 331         PM2XXX_INT3_ITCHCCWD            = 0x02,
 332         PM2XXX_INT3_ITCHCVWD            = 0x04,
 333         PM2XXX_INT3_ITAUTOTIMEOUTWD     = 0x08,
 334 };
 335
 336 enum pm2xxx_mask_reg_int3 {
 337         PM2XXX_INT3_M_ITCHPRECHARGEWD   = 0x01,
 338         PM2XXX_INT3_M_ITCHCCWD          = 0x02,
 339         PM2XXX_INT3_M_ITCHCVWD          = 0x04,
 340         PM2XXX_INT3_M_ITAUTOTIMEOUTWD   = 0x08,
 341 };
 342
 343 enum pm2xxx_source_reg_int3 {
 344         PM2XXX_INT3_S_ITCHPRECHARGEWD   = 0x01,
 345         PM2XXX_INT3_S_ITCHCCWD          = 0x02,
 346         PM2XXX_INT3_S_ITCHCVWD          = 0x04,
 347         PM2XXX_INT3_S_ITAUTOTIMEOUTWD   = 0x08,
 348 };
 349
 350 enum pm2xxx_reg_int4 {
 351         PM2XXX_INT4_ITBATTEMPCOLD       = 0x01,
 352         PM2XXX_INT4_ITBATTEMPHOT        = 0x02,
 353         PM2XXX_INT4_ITVPWR2OVV          = 0x04,
 354         PM2XXX_INT4_ITVPWR1OVV          = 0x08,
 355         PM2XXX_INT4_ITCHARGINGON        = 0x10,
 356         PM2XXX_INT4_ITVRESUME           = 0x20,
 357         PM2XXX_INT4_ITBATTFULL          = 0x40,
 358         PM2XXX_INT4_ITCVPHASE           = 0x80,
 359 };
 360
 361 enum pm2xxx_mask_reg_int4 {
 362         PM2XXX_INT4_M_ITBATTEMPCOLD     = 0x01,
 363         PM2XXX_INT4_M_ITBATTEMPHOT      = 0x02,
 364         PM2XXX_INT4_M_ITVPWR2OVV        = 0x04,
 365         PM2XXX_INT4_M_ITVPWR1OVV        = 0x08,
 366         PM2XXX_INT4_M_ITCHARGINGON      = 0x10,
 367         PM2XXX_INT4_M_ITVRESUME         = 0x20,
 368         PM2XXX_INT4_M_ITBATTFULL        = 0x40,
 369         PM2XXX_INT4_M_ITCVPHASE         = 0x80,
 370 };
 371
 372 enum pm2xxx_source_reg_int4 {
 373         PM2XXX_INT4_S_ITBATTEMPCOLD     = 0x01,
 374         PM2XXX_INT4_S_ITBATTEMPHOT      = 0x02,
 375         PM2XXX_INT4_S_ITVPWR2OVV        = 0x04,
 376         PM2XXX_INT4_S_ITVPWR1OVV        = 0x08,
 377         PM2XXX_INT4_S_ITCHARGINGON      = 0x10,
 378         PM2XXX_INT4_S_ITVRESUME         = 0x20,
 379         PM2XXX_INT4_S_ITBATTFULL        = 0x40,
 380         PM2XXX_INT4_S_ITCVPHASE         = 0x80,
 381 };
 382
 383 enum pm2xxx_reg_int5 {
 384         PM2XXX_INT5_ITTHERMALSHUTDOWNRISE       = 0x01,
 385         PM2XXX_INT5_ITTHERMALSHUTDOWNFALL       = 0x02,
 386         PM2XXX_INT5_ITTHERMALWARNINGRISE        = 0x04,
 387         PM2XXX_INT5_ITTHERMALWARNINGFALL        = 0x08,
 388         PM2XXX_INT5_ITVSYSTEMOVV                = 0x10,
 389 };
 390
 391 enum pm2xxx_mask_reg_int5 {
 392         PM2XXX_INT5_M_ITTHERMALSHUTDOWNRISE     = 0x01,
 393         PM2XXX_INT5_M_ITTHERMALSHUTDOWNFALL     = 0x02,
 394         PM2XXX_INT5_M_ITTHERMALWARNINGRISE      = 0x04,
 395         PM2XXX_INT5_M_ITTHERMALWARNINGFALL      = 0x08,
 396         PM2XXX_INT5_M_ITVSYSTEMOVV              = 0x10,
 397 };
 398
 399 enum pm2xxx_source_reg_int5 {
 400         PM2XXX_INT5_S_ITTHERMALSHUTDOWNRISE     = 0x01,
 401         PM2XXX_INT5_S_ITTHERMALSHUTDOWNFALL     = 0x02,
 402         PM2XXX_INT5_S_ITTHERMALWARNINGRISE      = 0x04,
 403         PM2XXX_INT5_S_ITTHERMALWARNINGFALL      = 0x08,
 404         PM2XXX_INT5_S_ITVSYSTEMOVV              = 0x10,
 405 };
 406
 407 enum pm2xxx_reg_int6 {
 408         PM2XXX_INT6_ITVPWR2DROP         = 0x01,
 409         PM2XXX_INT6_ITVPWR1DROP         = 0x02,
 410         PM2XXX_INT6_ITVPWR2VALIDRISE    = 0x04,
 411         PM2XXX_INT6_ITVPWR2VALIDFALL    = 0x08,
 412         PM2XXX_INT6_ITVPWR1VALIDRISE    = 0x10,
 413         PM2XXX_INT6_ITVPWR1VALIDFALL    = 0x20,
 414 };
 415
 416 enum pm2xxx_mask_reg_int6 {
 417         PM2XXX_INT6_M_ITVPWR2DROP       = 0x01,
 418         PM2XXX_INT6_M_ITVPWR1DROP       = 0x02,
 419         PM2XXX_INT6_M_ITVPWR2VALIDRISE  = 0x04,
 420         PM2XXX_INT6_M_ITVPWR2VALIDFALL  = 0x08,
 421         PM2XXX_INT6_M_ITVPWR1VALIDRISE  = 0x10,
 422         PM2XXX_INT6_M_ITVPWR1VALIDFALL  = 0x20,
 423 };
 424
 425 enum pm2xxx_source_reg_int6 {
 426         PM2XXX_INT6_S_ITVPWR2DROP       = 0x01,
 427         PM2XXX_INT6_S_ITVPWR1DROP       = 0x02,
 428         PM2XXX_INT6_S_ITVPWR2VALIDRISE  = 0x04,
 429         PM2XXX_INT6_S_ITVPWR2VALIDFALL  = 0x08,
 430         PM2XXX_INT6_S_ITVPWR1VALIDRISE  = 0x10,
 431         PM2XXX_INT6_S_ITVPWR1VALIDFALL  = 0x20,
 432 };
 433
 434 struct pm2xxx_charger_info {
 435         int charger_connected;
 436         int charger_online;
 437         int cv_active;
 438         bool wd_expired;
 439 };
 440
 441 struct pm2xxx_charger_event_flags {
 442         bool mainextchnotok;
 443         bool main_thermal_prot;
 444         bool ovv;
 445         bool chgwdexp;
 446 };
 447
 448 struct pm2xxx_interrupts {
 449         u8 reg[PM2XXX_NUM_INT_REG];
 450         int (*handler[PM2XXX_NUM_INT_REG])(void *, int);
 451 };
 452
 453 struct pm2xxx_config {
 454         struct i2c_client *pm2xxx_i2c;
 455         struct i2c_device_id *pm2xxx_id;
 456 };
 457
 458 struct pm2xxx_irq {
 459         char *name;
 460         irqreturn_t (*isr)(int irq, void *data);
 461 };
 462
 463 struct pm2xxx_charger {
 464         struct device *dev;
 465         u8 chip_id;
 466         bool vddadc_en_ac;
 467         struct pm2xxx_config config;
 468         bool ac_conn;
 469         unsigned int gpio_irq;
 470         int vbat;
 471         int old_vbat;
 472         int failure_case;
 473         int failure_input_ovv;
 474         unsigned int lpn_pin;
 475         struct pm2xxx_interrupts *pm2_int;
 476         struct regulator *regu;
 477         struct pm2xxx_bm_data *bat;
 478         struct mutex lock;
 479         struct ab8500 *parent;
 480         struct pm2xxx_charger_info ac;
 481         struct pm2xxx_charger_platform_data *pdata;
 482         struct workqueue_struct *charger_wq;
 483         struct delayed_work check_vbat_work;
 484         struct work_struct ac_work;
 485         struct work_struct check_main_thermal_prot_work;
 486         struct delayed_work check_hw_failure_work;
 487         struct ux500_charger ac_chg;
 488         struct power_supply_desc ac_chg_desc;
 489         struct pm2xxx_charger_event_flags flags;
 490 };
 491
 492 #endif /* PM2301_CHARGER_H */