1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 * Author: Christophe Kerello <christophe.kerello@st.com>
10 #include <power/pmic.h>
11 #include <power/regulator.h>
12 #include <power/stpmu1.h>
21 struct stpmu1_output_range {
22 const struct stpmu1_range *ranges;
26 #define STPMU1_MODE(_id, _val, _name) { \
28 .register_value = _val, \
32 #define STPMU1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \
34 .min_sel = _min_sel, \
35 .max_sel = _max_sel, \
39 #define STPMU1_OUTPUT_RANGE(_ranges, _nbranges) { \
41 .nbranges = _nbranges, \
44 static int stpmu1_output_find_uv(int sel,
45 const struct stpmu1_output_range *output_range)
47 const struct stpmu1_range *range;
50 for (i = 0, range = output_range->ranges;
51 i < output_range->nbranges; i++, range++) {
52 if (sel >= range->min_sel && sel <= range->max_sel)
53 return range->min_uv +
54 (sel - range->min_sel) * range->step;
60 static int stpmu1_output_find_sel(int uv,
61 const struct stpmu1_output_range *output_range)
63 const struct stpmu1_range *range;
66 for (i = 0, range = output_range->ranges;
67 i < output_range->nbranges; i++, range++) {
68 if (uv == range->min_uv && !range->step)
69 return range->min_sel;
71 if (uv >= range->min_uv &&
73 (range->max_sel - range->min_sel) * range->step)
74 return range->min_sel +
75 (uv - range->min_uv) / range->step;
85 static const struct stpmu1_range buck1_ranges[] = {
86 STPMU1_RANGE(600000, 0, 30, 25000),
87 STPMU1_RANGE(1350000, 31, 63, 0),
90 static const struct stpmu1_range buck2_ranges[] = {
91 STPMU1_RANGE(1000000, 0, 17, 0),
92 STPMU1_RANGE(1050000, 18, 19, 0),
93 STPMU1_RANGE(1100000, 20, 21, 0),
94 STPMU1_RANGE(1150000, 22, 23, 0),
95 STPMU1_RANGE(1200000, 24, 25, 0),
96 STPMU1_RANGE(1250000, 26, 27, 0),
97 STPMU1_RANGE(1300000, 28, 29, 0),
98 STPMU1_RANGE(1350000, 30, 31, 0),
99 STPMU1_RANGE(1400000, 32, 33, 0),
100 STPMU1_RANGE(1450000, 34, 35, 0),
101 STPMU1_RANGE(1500000, 36, 63, 0),
104 static const struct stpmu1_range buck3_ranges[] = {
105 STPMU1_RANGE(1000000, 0, 19, 0),
106 STPMU1_RANGE(1100000, 20, 23, 0),
107 STPMU1_RANGE(1200000, 24, 27, 0),
108 STPMU1_RANGE(1300000, 28, 31, 0),
109 STPMU1_RANGE(1400000, 32, 35, 0),
110 STPMU1_RANGE(1500000, 36, 55, 100000),
111 STPMU1_RANGE(3400000, 56, 63, 0),
114 static const struct stpmu1_range buck4_ranges[] = {
115 STPMU1_RANGE(600000, 0, 27, 25000),
116 STPMU1_RANGE(1300000, 28, 29, 0),
117 STPMU1_RANGE(1350000, 30, 31, 0),
118 STPMU1_RANGE(1400000, 32, 33, 0),
119 STPMU1_RANGE(1450000, 34, 35, 0),
120 STPMU1_RANGE(1500000, 36, 60, 100000),
121 STPMU1_RANGE(3900000, 61, 63, 0),
124 /* BUCK: 1,2,3,4 - voltage ranges */
125 static const struct stpmu1_output_range buck_voltage_range[] = {
126 STPMU1_OUTPUT_RANGE(buck1_ranges, ARRAY_SIZE(buck1_ranges)),
127 STPMU1_OUTPUT_RANGE(buck2_ranges, ARRAY_SIZE(buck2_ranges)),
128 STPMU1_OUTPUT_RANGE(buck3_ranges, ARRAY_SIZE(buck3_ranges)),
129 STPMU1_OUTPUT_RANGE(buck4_ranges, ARRAY_SIZE(buck4_ranges)),
133 static const struct dm_regulator_mode buck_modes[] = {
134 STPMU1_MODE(STPMU1_BUCK_MODE_HP, STPMU1_BUCK_MODE_HP, "HP"),
135 STPMU1_MODE(STPMU1_BUCK_MODE_LP, STPMU1_BUCK_MODE_LP, "LP"),
138 static int stpmu1_buck_get_uv(struct udevice *dev, int buck)
142 sel = pmic_reg_read(dev, STPMU1_BUCKX_CTRL_REG(buck));
146 sel &= STPMU1_BUCK_OUTPUT_MASK;
147 sel >>= STPMU1_BUCK_OUTPUT_SHIFT;
149 return stpmu1_output_find_uv(sel, &buck_voltage_range[buck]);
152 static int stpmu1_buck_get_value(struct udevice *dev)
154 return stpmu1_buck_get_uv(dev->parent, dev->driver_data - 1);
157 static int stpmu1_buck_set_value(struct udevice *dev, int uv)
159 int sel, buck = dev->driver_data - 1;
161 sel = stpmu1_output_find_sel(uv, &buck_voltage_range[buck]);
165 return pmic_clrsetbits(dev->parent,
166 STPMU1_BUCKX_CTRL_REG(buck),
167 STPMU1_BUCK_OUTPUT_MASK,
168 sel << STPMU1_BUCK_OUTPUT_SHIFT);
171 static int stpmu1_buck_get_enable(struct udevice *dev)
175 ret = pmic_reg_read(dev->parent,
176 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1));
180 return ret & STPMU1_BUCK_EN ? true : false;
183 static int stpmu1_buck_set_enable(struct udevice *dev, bool enable)
185 struct dm_regulator_uclass_platdata *uc_pdata;
186 int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
187 STPMU1_DEFAULT_STOP_DELAY_MS;
190 /* if regulator is already in the wanted state, nothing to do */
191 if (stpmu1_buck_get_enable(dev) == enable)
195 uc_pdata = dev_get_uclass_platdata(dev);
196 uv = stpmu1_buck_get_value(dev);
197 if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV))
198 stpmu1_buck_set_value(dev, uc_pdata->min_uV);
201 ret = pmic_clrsetbits(dev->parent,
202 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1),
203 STPMU1_BUCK_EN, enable ? STPMU1_BUCK_EN : 0);
209 static int stpmu1_buck_get_mode(struct udevice *dev)
213 ret = pmic_reg_read(dev->parent,
214 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1));
218 return ret & STPMU1_BUCK_MODE ? STPMU1_BUCK_MODE_LP :
222 static int stpmu1_buck_set_mode(struct udevice *dev, int mode)
224 return pmic_clrsetbits(dev->parent,
225 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1),
227 mode ? STPMU1_BUCK_MODE : 0);
230 static int stpmu1_buck_probe(struct udevice *dev)
232 struct dm_regulator_uclass_platdata *uc_pdata;
234 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_BUCK)
237 uc_pdata = dev_get_uclass_platdata(dev);
239 uc_pdata->type = REGULATOR_TYPE_BUCK;
240 uc_pdata->mode = (struct dm_regulator_mode *)buck_modes;
241 uc_pdata->mode_count = ARRAY_SIZE(buck_modes);
246 static const struct dm_regulator_ops stpmu1_buck_ops = {
247 .get_value = stpmu1_buck_get_value,
248 .set_value = stpmu1_buck_set_value,
249 .get_enable = stpmu1_buck_get_enable,
250 .set_enable = stpmu1_buck_set_enable,
251 .get_mode = stpmu1_buck_get_mode,
252 .set_mode = stpmu1_buck_set_mode,
255 U_BOOT_DRIVER(stpmu1_buck) = {
256 .name = "stpmu1_buck",
257 .id = UCLASS_REGULATOR,
258 .ops = &stpmu1_buck_ops,
259 .probe = stpmu1_buck_probe,
266 static const struct stpmu1_range ldo12_ranges[] = {
267 STPMU1_RANGE(1700000, 0, 7, 0),
268 STPMU1_RANGE(1700000, 8, 24, 100000),
269 STPMU1_RANGE(3300000, 25, 31, 0),
272 static const struct stpmu1_range ldo3_ranges[] = {
273 STPMU1_RANGE(1700000, 0, 7, 0),
274 STPMU1_RANGE(1700000, 8, 24, 100000),
275 STPMU1_RANGE(3300000, 25, 30, 0),
276 /* Sel 31 is special case when LDO3 is in mode sync_source (BUCK2/2) */
279 static const struct stpmu1_range ldo5_ranges[] = {
280 STPMU1_RANGE(1700000, 0, 7, 0),
281 STPMU1_RANGE(1700000, 8, 30, 100000),
282 STPMU1_RANGE(3900000, 31, 31, 0),
285 static const struct stpmu1_range ldo6_ranges[] = {
286 STPMU1_RANGE(900000, 0, 24, 100000),
287 STPMU1_RANGE(3300000, 25, 31, 0),
290 /* LDO: 1,2,3,4,5,6 - voltage ranges */
291 static const struct stpmu1_output_range ldo_voltage_range[] = {
292 STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
293 STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
294 STPMU1_OUTPUT_RANGE(ldo3_ranges, ARRAY_SIZE(ldo3_ranges)),
295 STPMU1_OUTPUT_RANGE(NULL, 0),
296 STPMU1_OUTPUT_RANGE(ldo5_ranges, ARRAY_SIZE(ldo5_ranges)),
297 STPMU1_OUTPUT_RANGE(ldo6_ranges, ARRAY_SIZE(ldo6_ranges)),
301 static const struct dm_regulator_mode ldo_modes[] = {
302 STPMU1_MODE(STPMU1_LDO_MODE_NORMAL,
303 STPMU1_LDO_MODE_NORMAL, "NORMAL"),
304 STPMU1_MODE(STPMU1_LDO_MODE_BYPASS,
305 STPMU1_LDO_MODE_BYPASS, "BYPASS"),
306 STPMU1_MODE(STPMU1_LDO_MODE_SINK_SOURCE,
307 STPMU1_LDO_MODE_SINK_SOURCE, "SINK SOURCE"),
310 static int stpmu1_ldo_get_value(struct udevice *dev)
312 int sel, ldo = dev->driver_data - 1;
314 sel = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
319 if (ldo == STPMU1_LDO4)
320 return STPMU1_LDO4_UV;
322 sel &= STPMU1_LDO12356_OUTPUT_MASK;
323 sel >>= STPMU1_LDO12356_OUTPUT_SHIFT;
325 /* ldo3, sel = 31 => BUCK2/2 */
326 if (ldo == STPMU1_LDO3 && sel == STPMU1_LDO3_DDR_SEL)
327 return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2;
329 return stpmu1_output_find_uv(sel, &ldo_voltage_range[ldo]);
332 static int stpmu1_ldo_set_value(struct udevice *dev, int uv)
334 int sel, ldo = dev->driver_data - 1;
336 /* ldo4 => not possible */
337 if (ldo == STPMU1_LDO4)
340 sel = stpmu1_output_find_sel(uv, &ldo_voltage_range[ldo]);
344 return pmic_clrsetbits(dev->parent,
345 STPMU1_LDOX_CTRL_REG(ldo),
346 STPMU1_LDO12356_OUTPUT_MASK,
347 sel << STPMU1_LDO12356_OUTPUT_SHIFT);
350 static int stpmu1_ldo_get_enable(struct udevice *dev)
354 ret = pmic_reg_read(dev->parent,
355 STPMU1_LDOX_CTRL_REG(dev->driver_data - 1));
359 return ret & STPMU1_LDO_EN ? true : false;
362 static int stpmu1_ldo_set_enable(struct udevice *dev, bool enable)
364 struct dm_regulator_uclass_platdata *uc_pdata;
365 int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
366 STPMU1_DEFAULT_STOP_DELAY_MS;
369 /* if regulator is already in the wanted state, nothing to do */
370 if (stpmu1_ldo_get_enable(dev) == enable)
374 uc_pdata = dev_get_uclass_platdata(dev);
375 uv = stpmu1_ldo_get_value(dev);
376 if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV))
377 stpmu1_ldo_set_value(dev, uc_pdata->min_uV);
380 ret = pmic_clrsetbits(dev->parent,
381 STPMU1_LDOX_CTRL_REG(dev->driver_data - 1),
382 STPMU1_LDO_EN, enable ? STPMU1_LDO_EN : 0);
388 static int stpmu1_ldo_get_mode(struct udevice *dev)
390 int ret, ldo = dev->driver_data - 1;
392 if (ldo != STPMU1_LDO3)
395 ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
399 if (ret & STPMU1_LDO3_MODE)
400 return STPMU1_LDO_MODE_BYPASS;
402 ret &= STPMU1_LDO12356_OUTPUT_MASK;
403 ret >>= STPMU1_LDO12356_OUTPUT_SHIFT;
405 return ret == STPMU1_LDO3_DDR_SEL ? STPMU1_LDO_MODE_SINK_SOURCE :
406 STPMU1_LDO_MODE_NORMAL;
409 static int stpmu1_ldo_set_mode(struct udevice *dev, int mode)
411 int ret, ldo = dev->driver_data - 1;
413 if (ldo != STPMU1_LDO3)
416 ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
421 case STPMU1_LDO_MODE_SINK_SOURCE:
422 ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
423 ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
424 case STPMU1_LDO_MODE_NORMAL:
425 ret &= ~STPMU1_LDO3_MODE;
427 case STPMU1_LDO_MODE_BYPASS:
428 ret |= STPMU1_LDO3_MODE;
432 return pmic_reg_write(dev->parent, STPMU1_LDOX_CTRL_REG(ldo), ret);
435 static int stpmu1_ldo_probe(struct udevice *dev)
437 struct dm_regulator_uclass_platdata *uc_pdata;
439 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_LDO)
442 uc_pdata = dev_get_uclass_platdata(dev);
444 uc_pdata->type = REGULATOR_TYPE_LDO;
445 if (dev->driver_data - 1 == STPMU1_LDO3) {
446 uc_pdata->mode = (struct dm_regulator_mode *)ldo_modes;
447 uc_pdata->mode_count = ARRAY_SIZE(ldo_modes);
449 uc_pdata->mode_count = 0;
455 static const struct dm_regulator_ops stpmu1_ldo_ops = {
456 .get_value = stpmu1_ldo_get_value,
457 .set_value = stpmu1_ldo_set_value,
458 .get_enable = stpmu1_ldo_get_enable,
459 .set_enable = stpmu1_ldo_set_enable,
460 .get_mode = stpmu1_ldo_get_mode,
461 .set_mode = stpmu1_ldo_set_mode,
464 U_BOOT_DRIVER(stpmu1_ldo) = {
465 .name = "stpmu1_ldo",
466 .id = UCLASS_REGULATOR,
467 .ops = &stpmu1_ldo_ops,
468 .probe = stpmu1_ldo_probe,
475 static int stpmu1_vref_ddr_get_value(struct udevice *dev)
478 return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2;
481 static int stpmu1_vref_ddr_get_enable(struct udevice *dev)
485 ret = pmic_reg_read(dev->parent, STPMU1_VREF_CTRL_REG);
489 return ret & STPMU1_VREF_EN ? true : false;
492 static int stpmu1_vref_ddr_set_enable(struct udevice *dev, bool enable)
494 int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
495 STPMU1_DEFAULT_STOP_DELAY_MS;
498 /* if regulator is already in the wanted state, nothing to do */
499 if (stpmu1_vref_ddr_get_enable(dev) == enable)
502 ret = pmic_clrsetbits(dev->parent, STPMU1_VREF_CTRL_REG,
503 STPMU1_VREF_EN, enable ? STPMU1_VREF_EN : 0);
509 static int stpmu1_vref_ddr_probe(struct udevice *dev)
511 struct dm_regulator_uclass_platdata *uc_pdata;
513 uc_pdata = dev_get_uclass_platdata(dev);
515 uc_pdata->type = REGULATOR_TYPE_FIXED;
516 uc_pdata->mode_count = 0;
521 static const struct dm_regulator_ops stpmu1_vref_ddr_ops = {
522 .get_value = stpmu1_vref_ddr_get_value,
523 .get_enable = stpmu1_vref_ddr_get_enable,
524 .set_enable = stpmu1_vref_ddr_set_enable,
527 U_BOOT_DRIVER(stpmu1_vref_ddr) = {
528 .name = "stpmu1_vref_ddr",
529 .id = UCLASS_REGULATOR,
530 .ops = &stpmu1_vref_ddr_ops,
531 .probe = stpmu1_vref_ddr_probe,
538 static int stpmu1_boost_get_enable(struct udevice *dev)
542 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
546 return ret & STPMU1_USB_BOOST_EN ? true : false;
549 static int stpmu1_boost_set_enable(struct udevice *dev, bool enable)
553 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
557 if (!enable && ret & STPMU1_USB_PWR_SW_EN)
560 /* if regulator is already in the wanted state, nothing to do */
561 if (!!(ret & STPMU1_USB_BOOST_EN) == enable)
564 ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
566 enable ? STPMU1_USB_BOOST_EN : 0);
568 mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS);
573 static int stpmu1_boost_probe(struct udevice *dev)
575 struct dm_regulator_uclass_platdata *uc_pdata;
577 uc_pdata = dev_get_uclass_platdata(dev);
579 uc_pdata->type = REGULATOR_TYPE_FIXED;
580 uc_pdata->mode_count = 0;
585 static const struct dm_regulator_ops stpmu1_boost_ops = {
586 .get_enable = stpmu1_boost_get_enable,
587 .set_enable = stpmu1_boost_set_enable,
590 U_BOOT_DRIVER(stpmu1_boost) = {
591 .name = "stpmu1_boost",
592 .id = UCLASS_REGULATOR,
593 .ops = &stpmu1_boost_ops,
594 .probe = stpmu1_boost_probe,
601 static int stpmu1_pwr_sw_get_enable(struct udevice *dev)
603 uint mask = 1 << dev->driver_data;
606 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
610 return ret & mask ? true : false;
613 static int stpmu1_pwr_sw_set_enable(struct udevice *dev, bool enable)
615 uint mask = 1 << dev->driver_data;
616 int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
617 STPMU1_DEFAULT_STOP_DELAY_MS;
620 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
624 /* if regulator is already in the wanted state, nothing to do */
625 if (!!(ret & mask) == enable)
628 /* Boost management */
629 if (enable && !(ret & STPMU1_USB_BOOST_EN)) {
630 pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
631 STPMU1_USB_BOOST_EN, STPMU1_USB_BOOST_EN);
632 mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS);
633 } else if (!enable && ret & STPMU1_USB_BOOST_EN &&
634 (ret & STPMU1_USB_PWR_SW_EN) != STPMU1_USB_PWR_SW_EN) {
635 pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
636 STPMU1_USB_BOOST_EN, 0);
639 ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
640 mask, enable ? mask : 0);
646 static int stpmu1_pwr_sw_probe(struct udevice *dev)
648 struct dm_regulator_uclass_platdata *uc_pdata;
650 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_PWR_SW)
653 uc_pdata = dev_get_uclass_platdata(dev);
655 uc_pdata->type = REGULATOR_TYPE_FIXED;
656 uc_pdata->mode_count = 0;
661 static const struct dm_regulator_ops stpmu1_pwr_sw_ops = {
662 .get_enable = stpmu1_pwr_sw_get_enable,
663 .set_enable = stpmu1_pwr_sw_set_enable,
666 U_BOOT_DRIVER(stpmu1_pwr_sw) = {
667 .name = "stpmu1_pwr_sw",
668 .id = UCLASS_REGULATOR,
669 .ops = &stpmu1_pwr_sw_ops,
670 .probe = stpmu1_pwr_sw_probe,