1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 * Author: Christophe Kerello <christophe.kerello@st.com>
10 #include <power/pmic.h>
11 #include <power/regulator.h>
12 #include <power/stpmu1.h>
21 struct stpmu1_output_range {
22 const struct stpmu1_range *ranges;
26 #define STPMU1_MODE(_id, _val, _name) { \
28 .register_value = _val, \
32 #define STPMU1_RANGE(_min_uv, _min_sel, _max_sel, _step) { \
34 .min_sel = _min_sel, \
35 .max_sel = _max_sel, \
39 #define STPMU1_OUTPUT_RANGE(_ranges, _nbranges) { \
41 .nbranges = _nbranges, \
44 static int stpmu1_output_find_uv(int sel,
45 const struct stpmu1_output_range *output_range)
47 const struct stpmu1_range *range;
50 for (i = 0, range = output_range->ranges;
51 i < output_range->nbranges; i++, range++) {
52 if (sel >= range->min_sel && sel <= range->max_sel)
53 return range->min_uv +
54 (sel - range->min_sel) * range->step;
60 static int stpmu1_output_find_sel(int uv,
61 const struct stpmu1_output_range *output_range)
63 const struct stpmu1_range *range;
66 for (i = 0, range = output_range->ranges;
67 i < output_range->nbranges; i++, range++) {
68 if (uv == range->min_uv && !range->step)
69 return range->min_sel;
71 if (uv >= range->min_uv &&
73 (range->max_sel - range->min_sel) * range->step)
74 return range->min_sel +
75 (uv - range->min_uv) / range->step;
85 static const struct stpmu1_range buck1_ranges[] = {
86 STPMU1_RANGE(600000, 0, 30, 25000),
87 STPMU1_RANGE(1350000, 31, 63, 0),
90 static const struct stpmu1_range buck2_ranges[] = {
91 STPMU1_RANGE(1000000, 0, 17, 0),
92 STPMU1_RANGE(1050000, 18, 19, 0),
93 STPMU1_RANGE(1100000, 20, 21, 0),
94 STPMU1_RANGE(1150000, 22, 23, 0),
95 STPMU1_RANGE(1200000, 24, 25, 0),
96 STPMU1_RANGE(1250000, 26, 27, 0),
97 STPMU1_RANGE(1300000, 28, 29, 0),
98 STPMU1_RANGE(1350000, 30, 31, 0),
99 STPMU1_RANGE(1400000, 32, 33, 0),
100 STPMU1_RANGE(1450000, 34, 35, 0),
101 STPMU1_RANGE(1500000, 36, 63, 0),
104 static const struct stpmu1_range buck3_ranges[] = {
105 STPMU1_RANGE(1000000, 0, 19, 0),
106 STPMU1_RANGE(1100000, 20, 23, 0),
107 STPMU1_RANGE(1200000, 24, 27, 0),
108 STPMU1_RANGE(1300000, 28, 31, 0),
109 STPMU1_RANGE(1400000, 32, 35, 0),
110 STPMU1_RANGE(1500000, 36, 55, 100000),
111 STPMU1_RANGE(3400000, 56, 63, 0),
114 static const struct stpmu1_range buck4_ranges[] = {
115 STPMU1_RANGE(600000, 0, 27, 25000),
116 STPMU1_RANGE(1300000, 28, 29, 0),
117 STPMU1_RANGE(1350000, 30, 31, 0),
118 STPMU1_RANGE(1400000, 32, 33, 0),
119 STPMU1_RANGE(1450000, 34, 35, 0),
120 STPMU1_RANGE(1500000, 36, 60, 100000),
121 STPMU1_RANGE(3900000, 61, 63, 0),
124 /* BUCK: 1,2,3,4 - voltage ranges */
125 static const struct stpmu1_output_range buck_voltage_range[] = {
126 STPMU1_OUTPUT_RANGE(buck1_ranges, ARRAY_SIZE(buck1_ranges)),
127 STPMU1_OUTPUT_RANGE(buck2_ranges, ARRAY_SIZE(buck2_ranges)),
128 STPMU1_OUTPUT_RANGE(buck3_ranges, ARRAY_SIZE(buck3_ranges)),
129 STPMU1_OUTPUT_RANGE(buck4_ranges, ARRAY_SIZE(buck4_ranges)),
133 static const struct dm_regulator_mode buck_modes[] = {
134 STPMU1_MODE(STPMU1_BUCK_MODE_HP, STPMU1_BUCK_MODE_HP, "HP"),
135 STPMU1_MODE(STPMU1_BUCK_MODE_LP, STPMU1_BUCK_MODE_LP, "LP"),
138 static int stpmu1_buck_get_uv(struct udevice *dev, int buck)
142 sel = pmic_reg_read(dev, STPMU1_BUCKX_CTRL_REG(buck));
146 sel &= STPMU1_BUCK_OUTPUT_MASK;
147 sel >>= STPMU1_BUCK_OUTPUT_SHIFT;
149 return stpmu1_output_find_uv(sel, &buck_voltage_range[buck]);
152 static int stpmu1_buck_get_value(struct udevice *dev)
154 return stpmu1_buck_get_uv(dev->parent, dev->driver_data - 1);
157 static int stpmu1_buck_set_value(struct udevice *dev, int uv)
159 int sel, buck = dev->driver_data - 1;
161 sel = stpmu1_output_find_sel(uv, &buck_voltage_range[buck]);
165 return pmic_clrsetbits(dev->parent,
166 STPMU1_BUCKX_CTRL_REG(buck),
167 STPMU1_BUCK_OUTPUT_MASK,
168 sel << STPMU1_BUCK_OUTPUT_SHIFT);
171 static int stpmu1_buck_get_enable(struct udevice *dev)
175 ret = pmic_reg_read(dev->parent,
176 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1));
180 return ret & STPMU1_BUCK_EN ? true : false;
183 static int stpmu1_buck_set_enable(struct udevice *dev, bool enable)
185 struct dm_regulator_uclass_platdata *uc_pdata;
188 /* if regulator is already in the wanted state, nothing to do */
189 if (stpmu1_buck_get_enable(dev) == enable)
193 uc_pdata = dev_get_uclass_platdata(dev);
194 uv = stpmu1_buck_get_value(dev);
195 if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV))
196 stpmu1_buck_set_value(dev, uc_pdata->min_uV);
199 ret = pmic_clrsetbits(dev->parent,
200 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1),
201 STPMU1_BUCK_EN, enable ? STPMU1_BUCK_EN : 0);
203 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
208 static int stpmu1_buck_get_mode(struct udevice *dev)
212 ret = pmic_reg_read(dev->parent,
213 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1));
217 return ret & STPMU1_BUCK_MODE ? STPMU1_BUCK_MODE_LP :
221 static int stpmu1_buck_set_mode(struct udevice *dev, int mode)
223 return pmic_clrsetbits(dev->parent,
224 STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1),
226 mode ? STPMU1_BUCK_MODE : 0);
229 static int stpmu1_buck_probe(struct udevice *dev)
231 struct dm_regulator_uclass_platdata *uc_pdata;
233 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_BUCK)
236 uc_pdata = dev_get_uclass_platdata(dev);
238 uc_pdata->type = REGULATOR_TYPE_BUCK;
239 uc_pdata->mode = (struct dm_regulator_mode *)buck_modes;
240 uc_pdata->mode_count = ARRAY_SIZE(buck_modes);
245 static const struct dm_regulator_ops stpmu1_buck_ops = {
246 .get_value = stpmu1_buck_get_value,
247 .set_value = stpmu1_buck_set_value,
248 .get_enable = stpmu1_buck_get_enable,
249 .set_enable = stpmu1_buck_set_enable,
250 .get_mode = stpmu1_buck_get_mode,
251 .set_mode = stpmu1_buck_set_mode,
254 U_BOOT_DRIVER(stpmu1_buck) = {
255 .name = "stpmu1_buck",
256 .id = UCLASS_REGULATOR,
257 .ops = &stpmu1_buck_ops,
258 .probe = stpmu1_buck_probe,
265 static const struct stpmu1_range ldo12_ranges[] = {
266 STPMU1_RANGE(1700000, 0, 7, 0),
267 STPMU1_RANGE(1700000, 8, 24, 100000),
268 STPMU1_RANGE(3300000, 25, 31, 0),
271 static const struct stpmu1_range ldo3_ranges[] = {
272 STPMU1_RANGE(1700000, 0, 7, 0),
273 STPMU1_RANGE(1700000, 8, 24, 100000),
274 STPMU1_RANGE(3300000, 25, 30, 0),
275 /* Sel 31 is special case when LDO3 is in mode sync_source (BUCK2/2) */
278 static const struct stpmu1_range ldo5_ranges[] = {
279 STPMU1_RANGE(1700000, 0, 7, 0),
280 STPMU1_RANGE(1700000, 8, 30, 100000),
281 STPMU1_RANGE(3900000, 31, 31, 0),
284 static const struct stpmu1_range ldo6_ranges[] = {
285 STPMU1_RANGE(900000, 0, 24, 100000),
286 STPMU1_RANGE(3300000, 25, 31, 0),
289 /* LDO: 1,2,3,4,5,6 - voltage ranges */
290 static const struct stpmu1_output_range ldo_voltage_range[] = {
291 STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
292 STPMU1_OUTPUT_RANGE(ldo12_ranges, ARRAY_SIZE(ldo12_ranges)),
293 STPMU1_OUTPUT_RANGE(ldo3_ranges, ARRAY_SIZE(ldo3_ranges)),
294 STPMU1_OUTPUT_RANGE(NULL, 0),
295 STPMU1_OUTPUT_RANGE(ldo5_ranges, ARRAY_SIZE(ldo5_ranges)),
296 STPMU1_OUTPUT_RANGE(ldo6_ranges, ARRAY_SIZE(ldo6_ranges)),
300 static const struct dm_regulator_mode ldo_modes[] = {
301 STPMU1_MODE(STPMU1_LDO_MODE_NORMAL,
302 STPMU1_LDO_MODE_NORMAL, "NORMAL"),
303 STPMU1_MODE(STPMU1_LDO_MODE_BYPASS,
304 STPMU1_LDO_MODE_BYPASS, "BYPASS"),
305 STPMU1_MODE(STPMU1_LDO_MODE_SINK_SOURCE,
306 STPMU1_LDO_MODE_SINK_SOURCE, "SINK SOURCE"),
309 static int stpmu1_ldo_get_value(struct udevice *dev)
311 int sel, ldo = dev->driver_data - 1;
313 sel = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
318 if (ldo == STPMU1_LDO4)
319 return STPMU1_LDO4_UV;
321 sel &= STPMU1_LDO12356_OUTPUT_MASK;
322 sel >>= STPMU1_LDO12356_OUTPUT_SHIFT;
324 /* ldo3, sel = 31 => BUCK2/2 */
325 if (ldo == STPMU1_LDO3 && sel == STPMU1_LDO3_DDR_SEL)
326 return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2;
328 return stpmu1_output_find_uv(sel, &ldo_voltage_range[ldo]);
331 static int stpmu1_ldo_set_value(struct udevice *dev, int uv)
333 int sel, ldo = dev->driver_data - 1;
335 /* ldo4 => not possible */
336 if (ldo == STPMU1_LDO4)
339 sel = stpmu1_output_find_sel(uv, &ldo_voltage_range[ldo]);
343 return pmic_clrsetbits(dev->parent,
344 STPMU1_LDOX_CTRL_REG(ldo),
345 STPMU1_LDO12356_OUTPUT_MASK,
346 sel << STPMU1_LDO12356_OUTPUT_SHIFT);
349 static int stpmu1_ldo_get_enable(struct udevice *dev)
353 ret = pmic_reg_read(dev->parent,
354 STPMU1_LDOX_CTRL_REG(dev->driver_data - 1));
358 return ret & STPMU1_LDO_EN ? true : false;
361 static int stpmu1_ldo_set_enable(struct udevice *dev, bool enable)
363 struct dm_regulator_uclass_platdata *uc_pdata;
366 /* if regulator is already in the wanted state, nothing to do */
367 if (stpmu1_ldo_get_enable(dev) == enable)
371 uc_pdata = dev_get_uclass_platdata(dev);
372 uv = stpmu1_ldo_get_value(dev);
373 if ((uv < uc_pdata->min_uV) || (uv > uc_pdata->max_uV))
374 stpmu1_ldo_set_value(dev, uc_pdata->min_uV);
377 ret = pmic_clrsetbits(dev->parent,
378 STPMU1_LDOX_CTRL_REG(dev->driver_data - 1),
379 STPMU1_LDO_EN, enable ? STPMU1_LDO_EN : 0);
381 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
386 static int stpmu1_ldo_get_mode(struct udevice *dev)
388 int ret, ldo = dev->driver_data - 1;
390 if (ldo != STPMU1_LDO3)
393 ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
397 if (ret & STPMU1_LDO3_MODE)
398 return STPMU1_LDO_MODE_BYPASS;
400 ret &= STPMU1_LDO12356_OUTPUT_MASK;
401 ret >>= STPMU1_LDO12356_OUTPUT_SHIFT;
403 return ret == STPMU1_LDO3_DDR_SEL ? STPMU1_LDO_MODE_SINK_SOURCE :
404 STPMU1_LDO_MODE_NORMAL;
407 static int stpmu1_ldo_set_mode(struct udevice *dev, int mode)
409 int ret, ldo = dev->driver_data - 1;
411 if (ldo != STPMU1_LDO3)
414 ret = pmic_reg_read(dev->parent, STPMU1_LDOX_CTRL_REG(ldo));
419 case STPMU1_LDO_MODE_SINK_SOURCE:
420 ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
421 ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
422 case STPMU1_LDO_MODE_NORMAL:
423 ret &= ~STPMU1_LDO3_MODE;
425 case STPMU1_LDO_MODE_BYPASS:
426 ret |= STPMU1_LDO3_MODE;
430 return pmic_reg_write(dev->parent, STPMU1_LDOX_CTRL_REG(ldo), ret);
433 static int stpmu1_ldo_probe(struct udevice *dev)
435 struct dm_regulator_uclass_platdata *uc_pdata;
437 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_LDO)
440 uc_pdata = dev_get_uclass_platdata(dev);
442 uc_pdata->type = REGULATOR_TYPE_LDO;
443 if (dev->driver_data - 1 == STPMU1_LDO3) {
444 uc_pdata->mode = (struct dm_regulator_mode *)ldo_modes;
445 uc_pdata->mode_count = ARRAY_SIZE(ldo_modes);
447 uc_pdata->mode_count = 0;
453 static const struct dm_regulator_ops stpmu1_ldo_ops = {
454 .get_value = stpmu1_ldo_get_value,
455 .set_value = stpmu1_ldo_set_value,
456 .get_enable = stpmu1_ldo_get_enable,
457 .set_enable = stpmu1_ldo_set_enable,
458 .get_mode = stpmu1_ldo_get_mode,
459 .set_mode = stpmu1_ldo_set_mode,
462 U_BOOT_DRIVER(stpmu1_ldo) = {
463 .name = "stpmu1_ldo",
464 .id = UCLASS_REGULATOR,
465 .ops = &stpmu1_ldo_ops,
466 .probe = stpmu1_ldo_probe,
473 static int stpmu1_vref_ddr_get_value(struct udevice *dev)
476 return stpmu1_buck_get_uv(dev->parent, STPMU1_BUCK2) / 2;
479 static int stpmu1_vref_ddr_get_enable(struct udevice *dev)
483 ret = pmic_reg_read(dev->parent, STPMU1_VREF_CTRL_REG);
487 return ret & STPMU1_VREF_EN ? true : false;
490 static int stpmu1_vref_ddr_set_enable(struct udevice *dev, bool enable)
494 /* if regulator is already in the wanted state, nothing to do */
495 if (stpmu1_vref_ddr_get_enable(dev) == enable)
498 ret = pmic_clrsetbits(dev->parent, STPMU1_VREF_CTRL_REG,
499 STPMU1_VREF_EN, enable ? STPMU1_VREF_EN : 0);
501 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
506 static int stpmu1_vref_ddr_probe(struct udevice *dev)
508 struct dm_regulator_uclass_platdata *uc_pdata;
510 uc_pdata = dev_get_uclass_platdata(dev);
512 uc_pdata->type = REGULATOR_TYPE_FIXED;
513 uc_pdata->mode_count = 0;
518 static const struct dm_regulator_ops stpmu1_vref_ddr_ops = {
519 .get_value = stpmu1_vref_ddr_get_value,
520 .get_enable = stpmu1_vref_ddr_get_enable,
521 .set_enable = stpmu1_vref_ddr_set_enable,
524 U_BOOT_DRIVER(stpmu1_vref_ddr) = {
525 .name = "stpmu1_vref_ddr",
526 .id = UCLASS_REGULATOR,
527 .ops = &stpmu1_vref_ddr_ops,
528 .probe = stpmu1_vref_ddr_probe,
535 static int stpmu1_boost_get_enable(struct udevice *dev)
539 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
543 return ret & STPMU1_USB_BOOST_EN ? true : false;
546 static int stpmu1_boost_set_enable(struct udevice *dev, bool enable)
550 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
554 if (!enable && ret & STPMU1_USB_PWR_SW_EN)
557 /* if regulator is already in the wanted state, nothing to do */
558 if (!!(ret & STPMU1_USB_BOOST_EN) == enable)
561 ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
563 enable ? STPMU1_USB_BOOST_EN : 0);
565 mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS);
570 static int stpmu1_boost_probe(struct udevice *dev)
572 struct dm_regulator_uclass_platdata *uc_pdata;
574 uc_pdata = dev_get_uclass_platdata(dev);
576 uc_pdata->type = REGULATOR_TYPE_FIXED;
577 uc_pdata->mode_count = 0;
582 static const struct dm_regulator_ops stpmu1_boost_ops = {
583 .get_enable = stpmu1_boost_get_enable,
584 .set_enable = stpmu1_boost_set_enable,
587 U_BOOT_DRIVER(stpmu1_boost) = {
588 .name = "stpmu1_boost",
589 .id = UCLASS_REGULATOR,
590 .ops = &stpmu1_boost_ops,
591 .probe = stpmu1_boost_probe,
598 static int stpmu1_pwr_sw_get_enable(struct udevice *dev)
600 uint mask = 1 << dev->driver_data;
603 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
607 return ret & mask ? true : false;
610 static int stpmu1_pwr_sw_set_enable(struct udevice *dev, bool enable)
612 uint mask = 1 << dev->driver_data;
615 ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
619 /* if regulator is already in the wanted state, nothing to do */
620 if (!!(ret & mask) == enable)
623 /* Boost management */
624 if (enable && !(ret & STPMU1_USB_BOOST_EN)) {
625 pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
626 STPMU1_USB_BOOST_EN, STPMU1_USB_BOOST_EN);
627 mdelay(STPMU1_USB_BOOST_START_UP_DELAY_MS);
628 } else if (!enable && ret & STPMU1_USB_BOOST_EN &&
629 (ret & STPMU1_USB_PWR_SW_EN) != STPMU1_USB_PWR_SW_EN) {
630 pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
631 STPMU1_USB_BOOST_EN, 0);
634 ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
635 mask, enable ? mask : 0);
637 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
642 static int stpmu1_pwr_sw_probe(struct udevice *dev)
644 struct dm_regulator_uclass_platdata *uc_pdata;
646 if (!dev->driver_data || dev->driver_data > STPMU1_MAX_PWR_SW)
649 uc_pdata = dev_get_uclass_platdata(dev);
651 uc_pdata->type = REGULATOR_TYPE_FIXED;
652 uc_pdata->mode_count = 0;
657 static const struct dm_regulator_ops stpmu1_pwr_sw_ops = {
658 .get_enable = stpmu1_pwr_sw_get_enable,
659 .set_enable = stpmu1_pwr_sw_set_enable,
662 U_BOOT_DRIVER(stpmu1_pwr_sw) = {
663 .name = "stpmu1_pwr_sw",
664 .id = UCLASS_REGULATOR,
665 .ops = &stpmu1_pwr_sw_ops,
666 .probe = stpmu1_pwr_sw_probe,