drivers/power/regulator/pfuze100.c

   1 #include <common.h>
   2 #include <fdtdec.h>
   3 #include <errno.h>
   4 #include <dm.h>
   5 #include <i2c.h>
   6 #include <power/pmic.h>
   7 #include <power/regulator.h>
   8 #include <power/pfuze100_pmic.h>
   9
  10 /**
  11  * struct pfuze100_regulator_desc - regulator descriptor
  12  *
  13  * @name: Identify name for the regulator.
  14  * @type: Indicates the regulator type.
  15  * @uV_step: Voltage increase for each selector.
  16  * @vsel_reg: Register for adjust regulator voltage for normal.
  17  * @vsel_mask: Mask bit for setting regulator voltage for normal.
  18  * @stby_reg: Register for adjust regulator voltage for standby.
  19  * @stby_mask: Mask bit for setting regulator voltage for standby.
  20  * @volt_table: Voltage mapping table (if table based mapping).
  21  * @voltage: Current voltage for REGULATOR_TYPE_FIXED type regulator.
  22  */
  23 struct pfuze100_regulator_desc {
  24         char *name;
  25         enum regulator_type type;
  26         unsigned int uV_step;
  27         unsigned int vsel_reg;
  28         unsigned int vsel_mask;
  29         unsigned int stby_reg;
  30         unsigned int stby_mask;
  31         unsigned int *volt_table;
  32         unsigned int voltage;
  33 };
  34
  35 /**
  36  * struct pfuze100_regulator_platdata - platform data for pfuze100
  37  *
  38  * @desc: Points the description entry of one regulator of pfuze100
  39  */
  40 struct pfuze100_regulator_platdata {
  41         struct pfuze100_regulator_desc *desc;
  42 };
  43
  44 #define PFUZE100_FIXED_REG(_name, base, vol)                            \
  45         {                                                               \
  46                 .name           =       #_name,                         \
  47                 .type           =       REGULATOR_TYPE_FIXED,           \
  48                 .voltage        =       (vol),                          \
  49         }
  50
  51 #define PFUZE100_SW_REG(_name, base, step)                              \
  52         {                                                               \
  53                 .name           =       #_name,                         \
  54                 .type           =       REGULATOR_TYPE_BUCK,            \
  55                 .uV_step        =       (step),                         \
  56                 .vsel_reg       =       (base) + PFUZE100_VOL_OFFSET,   \
  57                 .vsel_mask      =       0x3F,                           \
  58                 .stby_reg       =       (base) + PFUZE100_STBY_OFFSET,  \
  59                 .stby_mask      =       0x3F,                           \
  60         }
  61
  62 #define PFUZE100_SWB_REG(_name, base, mask, step, voltages)             \
  63         {                                                               \
  64                 .name           =       #_name,                         \
  65                 .type           =       REGULATOR_TYPE_BUCK,            \
  66                 .uV_step        =       (step),                         \
  67                 .vsel_reg       =       (base),                         \
  68                 .vsel_mask      =       (mask),                         \
  69                 .volt_table     =       (voltages),                     \
  70         }
  71
  72 #define PFUZE100_SNVS_REG(_name, base, mask, voltages)                  \
  73         {                                                               \
  74                 .name           =       #_name,                         \
  75                 .type           =       REGULATOR_TYPE_OTHER,           \
  76                 .vsel_reg       =       (base),                         \
  77                 .vsel_mask      =       (mask),                         \
  78                 .volt_table     =       (voltages),                     \
  79         }
  80
  81 #define PFUZE100_VGEN_REG(_name, base, step)                            \
  82         {                                                               \
  83                 .name           =       #_name,                         \
  84                 .type           =       REGULATOR_TYPE_LDO,             \
  85                 .uV_step        =       (step),                         \
  86                 .vsel_reg       =       (base),                         \
  87                 .vsel_mask      =       0xF,                            \
  88                 .stby_reg       =       (base),                         \
  89                 .stby_mask      =       0x20,                           \
  90         }
  91
  92 #define PFUZE3000_VCC_REG(_name, base, step)                            \
  93         {                                                               \
  94                 .name           =       #_name,                         \
  95                 .type           =       REGULATOR_TYPE_LDO,             \
  96                 .uV_step        =       (step),                         \
  97                 .vsel_reg       =       (base),                         \
  98                 .vsel_mask      =       0x3,                            \
  99                 .stby_reg       =       (base),                         \
 100                 .stby_mask      =       0x20,                           \
 101 }
 102
 103 #define PFUZE3000_SW1_REG(_name, base, step)                            \
 104         {                                                               \
 105                 .name           =       #_name,                         \
 106                 .type           =       REGULATOR_TYPE_BUCK,            \
 107                 .uV_step        =       (step),                         \
 108                 .vsel_reg       =       (base) + PFUZE100_VOL_OFFSET,   \
 109                 .vsel_mask      =       0x1F,                           \
 110                 .stby_reg       =       (base) + PFUZE100_STBY_OFFSET,  \
 111                 .stby_mask      =       0x1F,                           \
 112         }
 113
 114 #define PFUZE3000_SW2_REG(_name, base, step)                            \
 115         {                                                               \
 116                 .name           =       #_name,                         \
 117                 .type           =       REGULATOR_TYPE_BUCK,            \
 118                 .uV_step        =       (step),                         \
 119                 .vsel_reg       =       (base) + PFUZE100_VOL_OFFSET,   \
 120                 .vsel_mask      =       0x7,                            \
 121                 .stby_reg       =       (base) + PFUZE100_STBY_OFFSET,  \
 122                 .stby_mask      =       0x7,                            \
 123         }
 124
 125 #define PFUZE3000_SW3_REG(_name, base, step)                            \
 126         {                                                               \
 127                 .name           =       #_name,                         \
 128                 .type           =       REGULATOR_TYPE_BUCK,            \
 129                 .uV_step        =       (step),                         \
 130                 .vsel_reg       =       (base) + PFUZE100_VOL_OFFSET,   \
 131                 .vsel_mask      =       0xF,                            \
 132                 .stby_reg       =       (base) + PFUZE100_STBY_OFFSET,  \
 133                 .stby_mask      =       0xF,                            \
 134         }
 135
 136 static unsigned int pfuze100_swbst[] = {
 137         5000000, 5050000, 5100000, 5150000
 138 };
 139
 140 static unsigned int pfuze100_vsnvs[] = {
 141         1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000, -1
 142 };
 143
 144 static unsigned int pfuze3000_vsnvs[] = {
 145         -1, -1, -1, -1, -1, -1, 3000000, -1
 146 };
 147
 148 static unsigned int pfuze3000_sw2lo[] = {
 149         1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000
 150 };
 151
 152 /* PFUZE100 */
 153 static struct pfuze100_regulator_desc pfuze100_regulators[] = {
 154         PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000),
 155         PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000),
 156         PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000),
 157         PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000),
 158         PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000),
 159         PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000),
 160         PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),
 161         PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
 162         PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),
 163         PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000),
 164         PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000),
 165         PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000),
 166         PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000),
 167         PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000),
 168         PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000),
 169 };
 170
 171 /* PFUZE200 */
 172 static struct pfuze100_regulator_desc pfuze200_regulators[] = {
 173         PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000),
 174         PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000),
 175         PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000),
 176         PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000),
 177         PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),
 178         PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
 179         PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),
 180         PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000),
 181         PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000),
 182         PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000),
 183         PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000),
 184         PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000),
 185         PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000),
 186 };
 187
 188 /* PFUZE3000 */
 189 static struct pfuze100_regulator_desc pfuze3000_regulators[] = {
 190         PFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 25000),
 191         PFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 25000),
 192         PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo),
 193         PFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 50000),
 194         PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),
 195         PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze3000_vsnvs),
 196         PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000),
 197         PFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 100000),
 198         PFUZE100_VGEN_REG(vldo2, PFUZE100_VGEN2VOL, 50000),
 199         PFUZE3000_VCC_REG(vccsd, PFUZE100_VGEN3VOL, 150000),
 200         PFUZE3000_VCC_REG(v33, PFUZE100_VGEN4VOL, 150000),
 201         PFUZE100_VGEN_REG(vldo3, PFUZE100_VGEN5VOL, 100000),
 202         PFUZE100_VGEN_REG(vldo4, PFUZE100_VGEN6VOL, 100000),
 203 };
 204
 205 #define MODE(_id, _val, _name) { \
 206         .id = _id, \
 207         .register_value = _val, \
 208         .name = _name, \
 209 }
 210
 211 /* SWx Buck regulator mode */
 212 static struct dm_regulator_mode pfuze_sw_modes[] = {
 213         MODE(OFF_OFF, OFF_OFF, "OFF_OFF"),
 214         MODE(PWM_OFF, PWM_OFF, "PWM_OFF"),
 215         MODE(PFM_OFF, PFM_OFF, "PFM_OFF"),
 216         MODE(APS_OFF, APS_OFF, "APS_OFF"),
 217         MODE(PWM_PWM, PWM_PWM, "PWM_PWM"),
 218         MODE(PWM_APS, PWM_APS, "PWM_APS"),
 219         MODE(APS_APS, APS_APS, "APS_APS"),
 220         MODE(APS_PFM, APS_PFM, "APS_PFM"),
 221         MODE(PWM_PFM, PWM_PFM, "PWM_PFM"),
 222 };
 223
 224 /* Boost Buck regulator mode for normal operation */
 225 static struct dm_regulator_mode pfuze_swbst_modes[] = {
 226         MODE(SWBST_MODE_OFF, SWBST_MODE_OFF , "SWBST_MODE_OFF"),
 227         MODE(SWBST_MODE_PFM, SWBST_MODE_PFM, "SWBST_MODE_PFM"),
 228         MODE(SWBST_MODE_AUTO, SWBST_MODE_AUTO, "SWBST_MODE_AUTO"),
 229         MODE(SWBST_MODE_APS, SWBST_MODE_APS, "SWBST_MODE_APS"),
 230 };
 231
 232 /* VGENx LDO regulator mode for normal operation */
 233 static struct dm_regulator_mode pfuze_ldo_modes[] = {
 234         MODE(LDO_MODE_OFF, LDO_MODE_OFF, "LDO_MODE_OFF"),
 235         MODE(LDO_MODE_ON, LDO_MODE_ON, "LDO_MODE_ON"),
 236 };
 237
 238 static struct pfuze100_regulator_desc *se_desc(struct pfuze100_regulator_desc *desc,
 239                                                int size,
 240                                                const char *name)
 241 {
 242         int i;
 243
 244         for (i = 0; i < size; desc++) {
 245                 if (!strcmp(desc->name, name))
 246                         return desc;
 247                 continue;
 248         }
 249
 250         return NULL;
 251 }
 252
 253 static int pfuze100_regulator_probe(struct udevice *dev)
 254 {
 255         struct dm_regulator_uclass_platdata *uc_pdata;
 256         struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
 257         struct pfuze100_regulator_desc *desc;
 258
 259         switch (dev_get_driver_data(dev_get_parent(dev))) {
 260         case PFUZE100:
 261                 desc = se_desc(pfuze100_regulators,
 262                                ARRAY_SIZE(pfuze100_regulators),
 263                                dev->name);
 264                 break;
 265         case PFUZE200:
 266                 desc = se_desc(pfuze200_regulators,
 267                                ARRAY_SIZE(pfuze200_regulators),
 268                                dev->name);
 269                 break;
 270         case PFUZE3000:
 271                 desc = se_desc(pfuze3000_regulators,
 272                                ARRAY_SIZE(pfuze3000_regulators),
 273                                dev->name);
 274                 break;
 275         default:
 276                 debug("Unsupported PFUZE\n");
 277                 return -EINVAL;
 278         }
 279         if (!desc) {
 280                 debug("Do not support regulator %s\n", dev->name);
 281                 return -EINVAL;
 282         }
 283
 284         plat->desc = desc;
 285         uc_pdata = dev_get_uclass_platdata(dev);
 286
 287         uc_pdata->type = desc->type;
 288         if (uc_pdata->type == REGULATOR_TYPE_BUCK) {
 289                 if (!strcmp(dev->name, "swbst")) {
 290                         uc_pdata->mode = pfuze_swbst_modes;
 291                         uc_pdata->mode_count = ARRAY_SIZE(pfuze_swbst_modes);
 292                 } else {
 293                         uc_pdata->mode = pfuze_sw_modes;
 294                         uc_pdata->mode_count = ARRAY_SIZE(pfuze_sw_modes);
 295                 }
 296         } else if (uc_pdata->type == REGULATOR_TYPE_LDO) {
 297                 uc_pdata->mode = pfuze_ldo_modes;
 298                 uc_pdata->mode_count = ARRAY_SIZE(pfuze_ldo_modes);
 299         } else {
 300                 uc_pdata->mode = NULL;
 301                 uc_pdata->mode_count = 0;
 302         }
 303
 304         return 0;
 305 }
 306
 307 static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
 308 {
 309         unsigned char val;
 310         struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
 311         struct pfuze100_regulator_desc *desc = plat->desc;
 312
 313         if (op == PMIC_OP_GET) {
 314                 if (desc->type == REGULATOR_TYPE_BUCK) {
 315                         if (!strcmp(dev->name, "swbst")) {
 316                                 val = pmic_reg_read(dev->parent,
 317                                                     desc->vsel_reg);
 318                                 if (val < 0)
 319                                         return val;
 320
 321                                 val &= SWBST_MODE_MASK;
 322                                 val >>= SWBST_MODE_SHIFT;
 323                                 *opmode = val;
 324
 325                                 return 0;
 326                         }
 327                         val = pmic_reg_read(dev->parent,
 328                                             desc->vsel_reg +
 329                                             PFUZE100_MODE_OFFSET);
 330                         if (val < 0)
 331                                 return val;
 332
 333                         val &= SW_MODE_MASK;
 334                         val >>= SW_MODE_SHIFT;
 335                         *opmode = val;
 336
 337                         return 0;
 338
 339                 } else if (desc->type == REGULATOR_TYPE_LDO) {
 340                         val = pmic_reg_read(dev->parent, desc->vsel_reg);
 341                         if (val < 0)
 342                                 return val;
 343
 344                         val &= LDO_MODE_MASK;
 345                         val >>= LDO_MODE_SHIFT;
 346                         *opmode = val;
 347
 348                         return 0;
 349                 } else {
 350                         return -EINVAL;
 351                 }
 352         }
 353
 354         if (desc->type == REGULATOR_TYPE_BUCK) {
 355                 if (!strcmp(dev->name, "swbst"))
 356                         return pmic_clrsetbits(dev->parent, desc->vsel_reg,
 357                                                SWBST_MODE_MASK,
 358                                                *opmode << SWBST_MODE_SHIFT);
 359
 360                 val = pmic_clrsetbits(dev->parent,
 361                                        desc->vsel_reg + PFUZE100_MODE_OFFSET,
 362                                        SW_MODE_MASK,
 363                                        *opmode << SW_MODE_SHIFT);
 364
 365         } else if (desc->type == REGULATOR_TYPE_LDO) {
 366                 val = pmic_clrsetbits(dev->parent, desc->vsel_reg,
 367                                        LDO_MODE_MASK,
 368                                        *opmode << LDO_MODE_SHIFT);
 369                 return val;
 370         } else {
 371                 return -EINVAL;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static int pfuze100_regulator_enable(struct udevice *dev, int op, bool *enable)
 378 {
 379         unsigned char val;
 380         int ret, on_off;
 381         struct dm_regulator_uclass_platdata *uc_pdata =
 382                 dev_get_uclass_platdata(dev);
 383
 384         if (op == PMIC_OP_GET) {
 385                 if (!strcmp(dev->name, "vrefddr")) {
 386                         val = pmic_reg_read(dev->parent, PFUZE100_VREFDDRCON);
 387                         if (val < 0)
 388                                 return val;
 389
 390                         if (val & VREFDDRCON_EN)
 391                                 *enable = true;
 392                         else
 393                                 *enable = false;
 394                         return 0;
 395                 }
 396                 ret = pfuze100_regulator_mode(dev, op, &on_off);
 397                 if (ret)
 398                         return ret;
 399                 switch (on_off) {
 400                 /* OFF_OFF, SWBST_MODE_OFF, LDO_MODE_OFF have same value */
 401                 case OFF_OFF:
 402                         *enable = false;
 403                         break;
 404                 default:
 405                         *enable = true;
 406                         break;
 407                 }
 408         } else if (op == PMIC_OP_SET) {
 409                 if (!strcmp(dev->name, "vrefddr")) {
 410                         val = pmic_reg_read(dev->parent, PFUZE100_VREFDDRCON);
 411                         if (val < 0)
 412                                 return val;
 413
 414                         if (val & VREFDDRCON_EN)
 415                                 return 0;
 416                         val |= VREFDDRCON_EN;
 417
 418                         return pmic_reg_write(dev->parent, PFUZE100_VREFDDRCON,
 419                                               val);
 420                 }
 421
 422                 if (uc_pdata->type == REGULATOR_TYPE_LDO) {
 423                         on_off = *enable ? LDO_MODE_ON : LDO_MODE_OFF;
 424                 } else if (uc_pdata->type == REGULATOR_TYPE_BUCK) {
 425                         if (!strcmp(dev->name, "swbst"))
 426                                 on_off = *enable ? SWBST_MODE_AUTO :
 427                                         SWBST_MODE_OFF;
 428                         else
 429                                 on_off = *enable ? APS_PFM : OFF_OFF;
 430                 } else {
 431                         return -EINVAL;
 432                 }
 433
 434                 return pfuze100_regulator_mode(dev, op, &on_off);
 435         }
 436
 437         return 0;
 438 }
 439
 440 static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)
 441 {
 442         int i;
 443         unsigned char val;
 444         struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
 445         struct pfuze100_regulator_desc *desc = plat->desc;
 446         struct dm_regulator_uclass_platdata *uc_pdata =
 447                 dev_get_uclass_platdata(dev);
 448
 449         if (op == PMIC_OP_GET) {
 450                 *uV = 0;
 451                 if (uc_pdata->type == REGULATOR_TYPE_FIXED) {
 452                         *uV = desc->voltage;
 453                 } else if (desc->volt_table) {
 454                         val = pmic_reg_read(dev->parent, desc->vsel_reg);
 455                         if (val < 0)
 456                                 return val;
 457                         val &= desc->vsel_mask;
 458                         *uV = desc->volt_table[val];
 459                 } else {
 460                         if (uc_pdata->min_uV < 0) {
 461                                 debug("Need to provide min_uV in dts.\n");
 462                                 return -EINVAL;
 463                         }
 464                         val = pmic_reg_read(dev->parent, desc->vsel_reg);
 465                         if (val < 0)
 466                                 return val;
 467                         val &= desc->vsel_mask;
 468                         *uV = uc_pdata->min_uV + (int)val * desc->uV_step;
 469                 }
 470
 471                 return 0;
 472         }
 473
 474         if (uc_pdata->type == REGULATOR_TYPE_FIXED) {
 475                 debug("Set voltage for REGULATOR_TYPE_FIXED regulator\n");
 476                 return -EINVAL;
 477         } else if (desc->volt_table) {
 478                 for (i = 0; i < desc->vsel_mask; i++) {
 479                         if (*uV == desc->volt_table[i])
 480                                 break;
 481                 }
 482                 if (i == desc->vsel_mask) {
 483                         debug("Unsupported voltage %u\n", *uV);
 484                         return -EINVAL;
 485                 }
 486
 487                 return pmic_clrsetbits(dev->parent, desc->vsel_reg,
 488                                        desc->vsel_mask, i);
 489         } else {
 490                 if (uc_pdata->min_uV < 0) {
 491                         debug("Need to provide min_uV in dts.\n");
 492                         return -EINVAL;
 493                 }
 494                 return pmic_clrsetbits(dev->parent, desc->vsel_reg,
 495                                        desc->vsel_mask,
 496                                        (*uV - uc_pdata->min_uV) / desc->uV_step);
 497         }
 498
 499         return 0;
 500 }
 501
 502 static int pfuze100_regulator_get_value(struct udevice *dev)
 503 {
 504         int uV;
 505         int ret;
 506
 507         ret = pfuze100_regulator_val(dev, PMIC_OP_GET, &uV);
 508         if (ret)
 509                 return ret;
 510
 511         return uV;
 512 }
 513
 514 static int pfuze100_regulator_set_value(struct udevice *dev, int uV)
 515 {
 516         return pfuze100_regulator_val(dev, PMIC_OP_SET, &uV);
 517 }
 518
 519 static bool pfuze100_regulator_get_enable(struct udevice *dev)
 520 {
 521         int ret;
 522         bool enable = false;
 523
 524         ret = pfuze100_regulator_enable(dev, PMIC_OP_GET, &enable);
 525         if (ret)
 526                 return ret;
 527
 528         return enable;
 529 }
 530
 531 static int pfuze100_regulator_set_enable(struct udevice *dev, bool enable)
 532 {
 533         return pfuze100_regulator_enable(dev, PMIC_OP_SET, &enable);
 534 }
 535
 536 static int pfuze100_regulator_get_mode(struct udevice *dev)
 537 {
 538         int mode;
 539         int ret;
 540
 541         ret = pfuze100_regulator_mode(dev, PMIC_OP_GET, &mode);
 542         if (ret)
 543                 return ret;
 544
 545         return mode;
 546 }
 547
 548 static int pfuze100_regulator_set_mode(struct udevice *dev, int mode)
 549 {
 550         return pfuze100_regulator_mode(dev, PMIC_OP_SET, &mode);
 551 }
 552
 553 static const struct dm_regulator_ops pfuze100_regulator_ops = {
 554         .get_value  = pfuze100_regulator_get_value,
 555         .set_value  = pfuze100_regulator_set_value,
 556         .get_enable = pfuze100_regulator_get_enable,
 557         .set_enable = pfuze100_regulator_set_enable,
 558         .get_mode   = pfuze100_regulator_get_mode,
 559         .set_mode   = pfuze100_regulator_set_mode,
 560 };
 561
 562 U_BOOT_DRIVER(pfuze100_regulator) = {
 563         .name = "pfuze100_regulator",
 564         .id = UCLASS_REGULATOR,
 565         .ops = &pfuze100_regulator_ops,
 566         .probe = pfuze100_regulator_probe,
 567         .platdata_auto_alloc_size = sizeof(struct pfuze100_regulator_platdata),
 568 };