1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
13 #include <dm/device.h>
14 #include <dm/device_compat.h>
16 #include <power/pmic.h>
17 #include <power/stpmic1.h>
19 #define STPMIC1_NUM_OF_REGS 0x100
21 #define STPMIC1_NVM_SIZE 8
22 #define STPMIC1_NVM_POLL_TIMEOUT 100000
23 #define STPMIC1_NVM_START_ADDRESS 0xf8
32 #if CONFIG_IS_ENABLED(DM_REGULATOR)
33 static const struct pmic_child_info stpmic1_children_info[] = {
34 { .prefix = "ldo", .driver = "stpmic1_ldo" },
35 { .prefix = "buck", .driver = "stpmic1_buck" },
36 { .prefix = "vref_ddr", .driver = "stpmic1_vref_ddr" },
37 { .prefix = "pwr_sw", .driver = "stpmic1_pwr_sw" },
38 { .prefix = "boost", .driver = "stpmic1_boost" },
41 #endif /* DM_REGULATOR */
43 static int stpmic1_reg_count(struct udevice *dev)
45 return STPMIC1_NUM_OF_REGS;
48 static int stpmic1_write(struct udevice *dev, uint reg, const uint8_t *buff,
53 ret = dm_i2c_write(dev, reg, buff, len);
55 dev_err(dev, "%s: failed to write register %#x :%d",
61 static int stpmic1_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
65 ret = dm_i2c_read(dev, reg, buff, len);
67 dev_err(dev, "%s: failed to read register %#x : %d",
73 static int stpmic1_bind(struct udevice *dev)
76 #if CONFIG_IS_ENABLED(DM_REGULATOR)
77 ofnode regulators_node;
80 regulators_node = dev_read_subnode(dev, "regulators");
81 if (!ofnode_valid(regulators_node)) {
82 dev_dbg(dev, "regulators subnode not found!");
85 dev_dbg(dev, "found regulators subnode\n");
87 children = pmic_bind_children(dev, regulators_node,
88 stpmic1_children_info);
90 dev_dbg(dev, "no child found\n");
91 #endif /* DM_REGULATOR */
93 if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
94 ret = device_bind_driver(dev, "stpmic1-nvm",
100 if (CONFIG_IS_ENABLED(SYSRESET))
101 return device_bind_driver(dev, "stpmic1-sysreset",
102 "stpmic1-sysreset", NULL);
107 static struct dm_pmic_ops stpmic1_ops = {
108 .reg_count = stpmic1_reg_count,
109 .read = stpmic1_read,
110 .write = stpmic1_write,
113 static const struct udevice_id stpmic1_ids[] = {
114 { .compatible = "st,stpmic1" },
118 U_BOOT_DRIVER(pmic_stpmic1) = {
119 .name = "stpmic1_pmic",
121 .of_match = stpmic1_ids,
122 .bind = stpmic1_bind,
126 #ifndef CONFIG_SPL_BUILD
127 static int stpmic1_nvm_rw(struct udevice *dev, u8 addr, u8 *buf, int buf_len,
130 unsigned long timeout;
131 u8 cmd = STPMIC1_NVM_CMD_READ;
132 int ret, len = buf_len;
134 if (addr < STPMIC1_NVM_START_ADDRESS)
136 if (addr + buf_len > STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE)
137 len = STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE - addr;
139 if (op == SHADOW_READ) {
140 ret = pmic_read(dev, addr, buf, len);
147 if (op == SHADOW_WRITE) {
148 ret = pmic_write(dev, addr, buf, len);
155 if (op == NVM_WRITE) {
156 cmd = STPMIC1_NVM_CMD_PROGRAM;
158 ret = pmic_write(dev, addr, buf, len);
163 ret = pmic_reg_read(dev, STPMIC1_NVM_CR);
167 ret = pmic_reg_write(dev, STPMIC1_NVM_CR, ret | cmd);
171 timeout = timer_get_us() + STPMIC1_NVM_POLL_TIMEOUT;
173 ret = pmic_reg_read(dev, STPMIC1_NVM_SR);
177 if (!(ret & STPMIC1_NVM_BUSY))
180 if (time_after(timer_get_us(), timeout))
184 if (ret & STPMIC1_NVM_BUSY)
187 if (op == NVM_READ) {
188 ret = pmic_read(dev, addr, buf, len);
196 static int stpmic1_nvm_read(struct udevice *dev, int offset,
199 enum pmic_nvm_op op = NVM_READ;
206 return stpmic1_nvm_rw(dev->parent, offset, buf, size, op);
209 static int stpmic1_nvm_write(struct udevice *dev, int offset,
210 const void *buf, int size)
212 enum pmic_nvm_op op = NVM_WRITE;
219 return stpmic1_nvm_rw(dev->parent, offset, (void *)buf, size, op);
222 static const struct misc_ops stpmic1_nvm_ops = {
223 .read = stpmic1_nvm_read,
224 .write = stpmic1_nvm_write,
227 U_BOOT_DRIVER(stpmic1_nvm) = {
228 .name = "stpmic1-nvm",
230 .ops = &stpmic1_nvm_ops,
232 #endif /* CONFIG_SPL_BUILD */
234 #ifdef CONFIG_SYSRESET
235 static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type)
237 struct udevice *pmic_dev = dev->parent;
240 if (type != SYSRESET_POWER && type != SYSRESET_POWER_OFF)
241 return -EPROTONOSUPPORT;
243 ret = pmic_reg_read(pmic_dev, STPMIC1_MAIN_CR);
247 ret |= STPMIC1_SWOFF;
248 ret &= ~STPMIC1_RREQ_EN;
249 /* request Power Cycle */
250 if (type == SYSRESET_POWER)
251 ret |= STPMIC1_RREQ_EN;
253 ret = pmic_reg_write(pmic_dev, STPMIC1_MAIN_CR, ret);
260 static struct sysreset_ops stpmic1_sysreset_ops = {
261 .request = stpmic1_sysreset_request,
264 U_BOOT_DRIVER(stpmic1_sysreset) = {
265 .name = "stpmic1-sysreset",
266 .id = UCLASS_SYSRESET,
267 .ops = &stpmic1_sysreset_ops,