1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
12 #include <dm/device.h>
14 #include <power/pmic.h>
15 #include <power/stpmic1.h>
17 #define STPMIC1_NUM_OF_REGS 0x100
19 #define STPMIC1_NVM_SIZE 8
20 #define STPMIC1_NVM_POLL_TIMEOUT 100000
21 #define STPMIC1_NVM_START_ADDRESS 0xf8
30 #if CONFIG_IS_ENABLED(DM_REGULATOR)
31 static const struct pmic_child_info stpmic1_children_info[] = {
32 { .prefix = "ldo", .driver = "stpmic1_ldo" },
33 { .prefix = "buck", .driver = "stpmic1_buck" },
34 { .prefix = "vref_ddr", .driver = "stpmic1_vref_ddr" },
35 { .prefix = "pwr_sw", .driver = "stpmic1_pwr_sw" },
36 { .prefix = "boost", .driver = "stpmic1_boost" },
39 #endif /* DM_REGULATOR */
41 static int stpmic1_reg_count(struct udevice *dev)
43 return STPMIC1_NUM_OF_REGS;
46 static int stpmic1_write(struct udevice *dev, uint reg, const uint8_t *buff,
51 ret = dm_i2c_write(dev, reg, buff, len);
53 dev_err(dev, "%s: failed to write register %#x :%d",
59 static int stpmic1_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
63 ret = dm_i2c_read(dev, reg, buff, len);
65 dev_err(dev, "%s: failed to read register %#x : %d",
71 static int stpmic1_bind(struct udevice *dev)
74 #if CONFIG_IS_ENABLED(DM_REGULATOR)
75 ofnode regulators_node;
78 regulators_node = dev_read_subnode(dev, "regulators");
79 if (!ofnode_valid(regulators_node)) {
80 dev_dbg(dev, "regulators subnode not found!");
83 dev_dbg(dev, "found regulators subnode\n");
85 children = pmic_bind_children(dev, regulators_node,
86 stpmic1_children_info);
88 dev_dbg(dev, "no child found\n");
89 #endif /* DM_REGULATOR */
91 if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
92 ret = device_bind_driver(dev, "stpmic1-nvm",
98 if (CONFIG_IS_ENABLED(SYSRESET))
99 return device_bind_driver(dev, "stpmic1-sysreset",
100 "stpmic1-sysreset", NULL);
105 static struct dm_pmic_ops stpmic1_ops = {
106 .reg_count = stpmic1_reg_count,
107 .read = stpmic1_read,
108 .write = stpmic1_write,
111 static const struct udevice_id stpmic1_ids[] = {
112 { .compatible = "st,stpmic1" },
116 U_BOOT_DRIVER(pmic_stpmic1) = {
117 .name = "stpmic1_pmic",
119 .of_match = stpmic1_ids,
120 .bind = stpmic1_bind,
124 #ifndef CONFIG_SPL_BUILD
125 static int stpmic1_nvm_rw(struct udevice *dev, u8 addr, u8 *buf, int buf_len,
128 unsigned long timeout;
129 u8 cmd = STPMIC1_NVM_CMD_READ;
130 int ret, len = buf_len;
132 if (addr < STPMIC1_NVM_START_ADDRESS)
134 if (addr + buf_len > STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE)
135 len = STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE - addr;
137 if (op == SHADOW_READ) {
138 ret = pmic_read(dev, addr, buf, len);
145 if (op == SHADOW_WRITE) {
146 ret = pmic_write(dev, addr, buf, len);
153 if (op == NVM_WRITE) {
154 cmd = STPMIC1_NVM_CMD_PROGRAM;
156 ret = pmic_write(dev, addr, buf, len);
161 ret = pmic_reg_read(dev, STPMIC1_NVM_CR);
165 ret = pmic_reg_write(dev, STPMIC1_NVM_CR, ret | cmd);
169 timeout = timer_get_us() + STPMIC1_NVM_POLL_TIMEOUT;
171 ret = pmic_reg_read(dev, STPMIC1_NVM_SR);
175 if (!(ret & STPMIC1_NVM_BUSY))
178 if (time_after(timer_get_us(), timeout))
182 if (ret & STPMIC1_NVM_BUSY)
185 if (op == NVM_READ) {
186 ret = pmic_read(dev, addr, buf, len);
194 static int stpmic1_nvm_read(struct udevice *dev, int offset,
197 enum pmic_nvm_op op = NVM_READ;
204 return stpmic1_nvm_rw(dev->parent, offset, buf, size, op);
207 static int stpmic1_nvm_write(struct udevice *dev, int offset,
208 const void *buf, int size)
210 enum pmic_nvm_op op = NVM_WRITE;
217 return stpmic1_nvm_rw(dev->parent, offset, (void *)buf, size, op);
220 static const struct misc_ops stpmic1_nvm_ops = {
221 .read = stpmic1_nvm_read,
222 .write = stpmic1_nvm_write,
225 U_BOOT_DRIVER(stpmic1_nvm) = {
226 .name = "stpmic1-nvm",
228 .ops = &stpmic1_nvm_ops,
230 #endif /* CONFIG_SPL_BUILD */
232 #ifdef CONFIG_SYSRESET
233 static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type)
235 struct udevice *pmic_dev = dev->parent;
238 if (type != SYSRESET_POWER && type != SYSRESET_POWER_OFF)
239 return -EPROTONOSUPPORT;
241 ret = pmic_reg_read(pmic_dev, STPMIC1_MAIN_CR);
245 ret |= STPMIC1_SWOFF;
246 ret &= ~STPMIC1_RREQ_EN;
247 /* request Power Cycle */
248 if (type == SYSRESET_POWER)
249 ret |= STPMIC1_RREQ_EN;
251 ret = pmic_reg_write(pmic_dev, STPMIC1_MAIN_CR, ret);
258 static struct sysreset_ops stpmic1_sysreset_ops = {
259 .request = stpmic1_sysreset_request,
262 U_BOOT_DRIVER(stpmic1_sysreset) = {
263 .name = "stpmic1-sysreset",
264 .id = UCLASS_SYSRESET,
265 .ops = &stpmic1_sysreset_ops,