drivers/power/domain/meson-ee-pwrc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2019 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <malloc.h>
  10 #include <power-domain-uclass.h>
  11 #include <regmap.h>
  12 #include <syscon.h>
  13 #include <reset.h>
  14 #include <clk.h>
  15 #include <dt-bindings/power/meson-g12a-power.h>
  16 #include <dt-bindings/power/meson-sm1-power.h>
  17 #include <linux/err.h>
  18
  19 /* AO Offsets */
  20
  21 #define AO_RTI_GEN_PWR_SLEEP0           (0x3a << 2)
  22 #define AO_RTI_GEN_PWR_ISO0             (0x3b << 2)
  23
  24 /* HHI Offsets */
  25
  26 #define HHI_MEM_PD_REG0                 (0x40 << 2)
  27 #define HHI_VPU_MEM_PD_REG0             (0x41 << 2)
  28 #define HHI_VPU_MEM_PD_REG1             (0x42 << 2)
  29 #define HHI_VPU_MEM_PD_REG3             (0x43 << 2)
  30 #define HHI_VPU_MEM_PD_REG4             (0x44 << 2)
  31 #define HHI_AUDIO_MEM_PD_REG0           (0x45 << 2)
  32 #define HHI_NANOQ_MEM_PD_REG0           (0x46 << 2)
  33 #define HHI_NANOQ_MEM_PD_REG1           (0x47 << 2)
  34 #define HHI_VPU_MEM_PD_REG2             (0x4d << 2)
  35
  36 struct meson_ee_pwrc;
  37 struct meson_ee_pwrc_domain;
  38
  39 struct meson_ee_pwrc_mem_domain {
  40         unsigned int reg;
  41         unsigned int mask;
  42 };
  43
  44 struct meson_ee_pwrc_top_domain {
  45         unsigned int sleep_reg;
  46         unsigned int sleep_mask;
  47         unsigned int iso_reg;
  48         unsigned int iso_mask;
  49 };
  50
  51 struct meson_ee_pwrc_domain_desc {
  52         char *name;
  53         unsigned int reset_names_count;
  54         unsigned int clk_names_count;
  55         struct meson_ee_pwrc_top_domain *top_pd;
  56         unsigned int mem_pd_count;
  57         struct meson_ee_pwrc_mem_domain *mem_pd;
  58         bool (*get_power)(struct power_domain *power_domain);
  59 };
  60
  61 struct meson_ee_pwrc_domain_data {
  62         unsigned int count;
  63         struct meson_ee_pwrc_domain_desc *domains;
  64 };
  65
  66 /* TOP Power Domains */
  67
  68 static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = {
  69         .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,
  70         .sleep_mask = BIT(8),
  71         .iso_reg = AO_RTI_GEN_PWR_SLEEP0,
  72         .iso_mask = BIT(9),
  73 };
  74
  75 #define SM1_EE_PD(__bit)                                        \
  76         {                                                       \
  77                 .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,             \
  78                 .sleep_mask = BIT(__bit),                       \
  79                 .iso_reg = AO_RTI_GEN_PWR_ISO0,                 \
  80                 .iso_mask = BIT(__bit),                         \
  81         }
  82
  83 static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
  84 static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
  85 static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
  86 static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
  87 static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
  88
  89 /* Memory PD Domains */
  90
  91 #define VPU_MEMPD(__reg)                                        \
  92         { __reg, GENMASK(1, 0) },                               \
  93         { __reg, GENMASK(3, 2) },                               \
  94         { __reg, GENMASK(5, 4) },                               \
  95         { __reg, GENMASK(7, 6) },                               \
  96         { __reg, GENMASK(9, 8) },                               \
  97         { __reg, GENMASK(11, 10) },                             \
  98         { __reg, GENMASK(13, 12) },                             \
  99         { __reg, GENMASK(15, 14) },                             \
 100         { __reg, GENMASK(17, 16) },                             \
 101         { __reg, GENMASK(19, 18) },                             \
 102         { __reg, GENMASK(21, 20) },                             \
 103         { __reg, GENMASK(23, 22) },                             \
 104         { __reg, GENMASK(25, 24) },                             \
 105         { __reg, GENMASK(27, 26) },                             \
 106         { __reg, GENMASK(29, 28) },                             \
 107         { __reg, GENMASK(31, 30) }
 108
 109 #define VPU_HHI_MEMPD(__reg)                                    \
 110         { __reg, BIT(8) },                                      \
 111         { __reg, BIT(9) },                                      \
 112         { __reg, BIT(10) },                                     \
 113         { __reg, BIT(11) },                                     \
 114         { __reg, BIT(12) },                                     \
 115         { __reg, BIT(13) },                                     \
 116         { __reg, BIT(14) },                                     \
 117         { __reg, BIT(15) }
 118
 119 static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
 120         VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
 121         VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
 122         VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
 123         VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
 124 };
 125
 126 static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
 127         { HHI_MEM_PD_REG0, GENMASK(3, 2) },
 128 };
 129
 130 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
 131         VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
 132         VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
 133         VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
 134         VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
 135         { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
 136         { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
 137         { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
 138         { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
 139         VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
 140 };
 141
 142 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
 143         { HHI_NANOQ_MEM_PD_REG0, 0xff },
 144         { HHI_NANOQ_MEM_PD_REG1, 0xff },
 145 };
 146
 147 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
 148         { HHI_MEM_PD_REG0, GENMASK(31, 30) },
 149 };
 150
 151 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
 152         { HHI_MEM_PD_REG0, GENMASK(29, 26) },
 153 };
 154
 155 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
 156         { HHI_MEM_PD_REG0, GENMASK(25, 18) },
 157 };
 158
 159 static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
 160         { HHI_MEM_PD_REG0, GENMASK(5, 4) },
 161         { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
 162         { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
 163         { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
 164         { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
 165         { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
 166         { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
 167         { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
 168         { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
 169         { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
 170         { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
 171         { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
 172         { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
 173 };
 174
 175 #define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks)  \
 176         {                                                               \
 177                 .name = __name,                                         \
 178                 .reset_names_count = __resets,                          \
 179                 .clk_names_count = __clks,                              \
 180                 .top_pd = __top_pd,                                     \
 181                 .mem_pd_count = ARRAY_SIZE(__mem),                      \
 182                 .mem_pd = __mem,                                        \
 183                 .get_power = __get_power,                               \
 184         }
 185
 186 #define TOP_PD(__name, __top_pd, __mem, __get_power)                    \
 187         {                                                               \
 188                 .name = __name,                                         \
 189                 .top_pd = __top_pd,                                     \
 190                 .mem_pd_count = ARRAY_SIZE(__mem),                      \
 191                 .mem_pd = __mem,                                        \
 192                 .get_power = __get_power,                               \
 193         }
 194
 195 #define MEM_PD(__name, __mem)                                           \
 196         TOP_PD(__name, NULL, __mem, NULL)
 197
 198 static bool pwrc_ee_get_power(struct power_domain *power_domain);
 199
 200 static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
 201         [PWRC_G12A_VPU_ID]  = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
 202                                      pwrc_ee_get_power, 11, 2),
 203         [PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
 204 };
 205
 206 static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
 207         [PWRC_SM1_VPU_ID]  = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
 208                                     pwrc_ee_get_power, 11, 2),
 209         [PWRC_SM1_NNA_ID]  = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
 210                                     pwrc_ee_get_power),
 211         [PWRC_SM1_USB_ID]  = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
 212                                     pwrc_ee_get_power),
 213         [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
 214                                     pwrc_ee_get_power),
 215         [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
 216                                     pwrc_ee_get_power),
 217         [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
 218         [PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
 219 };
 220
 221 struct meson_ee_pwrc_priv {
 222         struct regmap *regmap_ao;
 223         struct regmap *regmap_hhi;
 224         struct reset_ctl_bulk resets;
 225         struct clk_bulk clks;
 226         const struct meson_ee_pwrc_domain_data *data;
 227 };
 228
 229 static bool pwrc_ee_get_power(struct power_domain *power_domain)
 230 {
 231         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 232         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 233         u32 reg;
 234
 235         pwrc_domain = &priv->data->domains[power_domain->id];
 236
 237         regmap_read(priv->regmap_ao,
 238                     pwrc_domain->top_pd->sleep_reg, &reg);
 239
 240         return (reg & pwrc_domain->top_pd->sleep_mask);
 241 }
 242
 243 static int meson_ee_pwrc_request(struct power_domain *power_domain)
 244 {
 245         return 0;
 246 }
 247
 248 static int meson_ee_pwrc_free(struct power_domain *power_domain)
 249 {
 250         return 0;
 251 }
 252
 253 static int meson_ee_pwrc_off(struct power_domain *power_domain)
 254 {
 255         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 256         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 257         int i;
 258
 259         pwrc_domain = &priv->data->domains[power_domain->id];
 260
 261         if (pwrc_domain->top_pd)
 262                 regmap_update_bits(priv->regmap_ao,
 263                                    pwrc_domain->top_pd->sleep_reg,
 264                                    pwrc_domain->top_pd->sleep_mask,
 265                                    pwrc_domain->top_pd->sleep_mask);
 266         udelay(20);
 267
 268         for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
 269                 regmap_update_bits(priv->regmap_hhi,
 270                                    pwrc_domain->mem_pd[i].reg,
 271                                    pwrc_domain->mem_pd[i].mask,
 272                                    pwrc_domain->mem_pd[i].mask);
 273
 274         udelay(20);
 275
 276         if (pwrc_domain->top_pd)
 277                 regmap_update_bits(priv->regmap_ao,
 278                                    pwrc_domain->top_pd->iso_reg,
 279                                    pwrc_domain->top_pd->iso_mask,
 280                                    pwrc_domain->top_pd->iso_mask);
 281
 282         if (pwrc_domain->clk_names_count) {
 283                 mdelay(20);
 284                 clk_disable_bulk(&priv->clks);
 285         }
 286
 287         return 0;
 288 }
 289
 290 static int meson_ee_pwrc_on(struct power_domain *power_domain)
 291 {
 292         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 293         struct meson_ee_pwrc_domain_desc *pwrc_domain;
 294         int i, ret;
 295
 296         pwrc_domain = &priv->data->domains[power_domain->id];
 297
 298         if (pwrc_domain->top_pd)
 299                 regmap_update_bits(priv->regmap_ao,
 300                                    pwrc_domain->top_pd->sleep_reg,
 301                                    pwrc_domain->top_pd->sleep_mask, 0);
 302         udelay(20);
 303
 304         for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
 305                 regmap_update_bits(priv->regmap_hhi,
 306                                    pwrc_domain->mem_pd[i].reg,
 307                                    pwrc_domain->mem_pd[i].mask, 0);
 308
 309         udelay(20);
 310
 311         if (pwrc_domain->reset_names_count) {
 312                 ret = reset_assert_bulk(&priv->resets);
 313                 if (ret)
 314                         return ret;
 315         }
 316
 317         if (pwrc_domain->top_pd)
 318                 regmap_update_bits(priv->regmap_ao,
 319                                    pwrc_domain->top_pd->iso_reg,
 320                                    pwrc_domain->top_pd->iso_mask, 0);
 321
 322         if (pwrc_domain->reset_names_count) {
 323                 ret = reset_deassert_bulk(&priv->resets);
 324                 if (ret)
 325                         return ret;
 326         }
 327
 328         if (pwrc_domain->clk_names_count)
 329                 return clk_enable_bulk(&priv->clks);
 330
 331         return 0;
 332 }
 333
 334 static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain,
 335                                   struct ofnode_phandle_args *args)
 336 {
 337         struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
 338
 339         /* #power-domain-cells is 1 */
 340
 341         if (args->args_count < 1) {
 342                 debug("Invalid args_count: %d\n", args->args_count);
 343                 return -EINVAL;
 344         }
 345
 346         power_domain->id = args->args[0];
 347
 348         if (power_domain->id >= priv->data->count) {
 349                 debug("Invalid domain ID: %lu\n", power_domain->id);
 350                 return -EINVAL;
 351         }
 352
 353         return 0;
 354 }
 355
 356 struct power_domain_ops meson_ee_pwrc_ops = {
 357         .rfree = meson_ee_pwrc_free,
 358         .off = meson_ee_pwrc_off,
 359         .on = meson_ee_pwrc_on,
 360         .request = meson_ee_pwrc_request,
 361         .of_xlate = meson_ee_pwrc_of_xlate,
 362 };
 363
 364 static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
 365         .count = ARRAY_SIZE(g12a_pwrc_domains),
 366         .domains = g12a_pwrc_domains,
 367 };
 368
 369 static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
 370         .count = ARRAY_SIZE(sm1_pwrc_domains),
 371         .domains = sm1_pwrc_domains,
 372 };
 373
 374 static const struct udevice_id meson_ee_pwrc_ids[] = {
 375         {
 376                 .compatible = "amlogic,meson-g12a-pwrc",
 377                 .data = (unsigned long)&meson_ee_g12a_pwrc_data,
 378         },
 379         {
 380                 .compatible = "amlogic,meson-sm1-pwrc",
 381                 .data = (unsigned long)&meson_ee_sm1_pwrc_data,
 382         },
 383         { }
 384 };
 385
 386 static int meson_ee_pwrc_probe(struct udevice *dev)
 387 {
 388         struct meson_ee_pwrc_priv *priv = dev_get_priv(dev);
 389         u32 ao_phandle;
 390         ofnode ao_node;
 391         int ret;
 392
 393         priv->data = (void *)dev_get_driver_data(dev);
 394         if (!priv->data)
 395                 return -EINVAL;
 396
 397         priv->regmap_hhi = syscon_node_to_regmap(dev_get_parent(dev)->node);
 398         if (IS_ERR(priv->regmap_hhi))
 399                 return PTR_ERR(priv->regmap_hhi);
 400
 401         ret = ofnode_read_u32(dev->node, "amlogic,ao-sysctrl",
 402                               &ao_phandle);
 403         if (ret)
 404                 return ret;
 405
 406         ao_node = ofnode_get_by_phandle(ao_phandle);
 407         if (!ofnode_valid(ao_node))
 408                 return -EINVAL;
 409
 410         priv->regmap_ao = syscon_node_to_regmap(ao_node);
 411         if (IS_ERR(priv->regmap_ao))
 412                 return PTR_ERR(priv->regmap_ao);
 413
 414         ret = reset_get_bulk(dev, &priv->resets);
 415         if (ret)
 416                 return ret;
 417
 418         ret = clk_get_bulk(dev, &priv->clks);
 419         if (ret)
 420                 return ret;
 421
 422         return 0;
 423 }
 424
 425 U_BOOT_DRIVER(meson_ee_pwrc) = {
 426         .name = "meson_ee_pwrc",
 427         .id = UCLASS_POWER_DOMAIN,
 428         .of_match = meson_ee_pwrc_ids,
 429         .probe = meson_ee_pwrc_probe,
 430         .ops = &meson_ee_pwrc_ops,
 431         .priv_auto_alloc_size = sizeof(struct meson_ee_pwrc_priv),
 432 };