1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019 Google LLC
6 #define LOG_CATEGORY UCLASS_ACPI_PMC
13 #include <asm/intel_pinctrl.h>
16 #include <power/acpi_pmc.h>
35 TCO_STS_TIMEOUT = 1 << 3,
36 TCO_STS_SECOND_TO_STS = 1 << 17,
37 TCO1_CNT_HLT = 1 << 11,
41 static int gpe0_shift(struct acpi_pmc_upriv *upriv, int regnum)
43 return upriv->gpe0_dwx_shift_base + regnum * 4;
46 int pmc_gpe_init(struct udevice *dev)
48 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
56 if (device_get_uclass_id(dev) != UCLASS_ACPI_PMC)
57 return log_msg_ret("uclass", -EPROTONOSUPPORT);
59 mask = upriv->gpe0_dwx_mask;
61 for (i = 0; i < upriv->gpe0_count; i++) {
62 gpio_cfg_mask |= mask << gpe0_shift(upriv, i);
64 return log_msg_ret("Base GPE0 value", -EINVAL);
68 * Route the GPIOs to the GPE0 block. Determine that all values
69 * are different and if they aren't, use the reset values.
71 if (dw[0] == dw[1] || dw[1] == dw[2]) {
72 log_info("PMC: Using default GPE route");
73 gpio_cfg = readl(upriv->gpe_cfg);
74 for (i = 0; i < upriv->gpe0_count; i++)
75 dw[i] = gpio_cfg >> gpe0_shift(upriv, i);
78 for (i = 0; i < upriv->gpe0_count; i++)
79 gpio_cfg |= dw[i] << gpe0_shift(upriv, i);
80 clrsetbits_le32(upriv->gpe_cfg, gpio_cfg_mask, gpio_cfg);
83 /* Set the routes in the GPIO communities as well */
84 ret = uclass_first_device_err(UCLASS_IRQ, &itss);
86 return log_msg_ret("Cannot find itss", ret);
87 pinctrl_route_gpe(itss, dw[0], dw[1], dw[2]);
91 #endif /* CONFIG_X86 */
93 static void pmc_fill_pm_reg_info(struct udevice *dev)
95 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
98 upriv->pm1_sts = inw(upriv->acpi_base + PM1_STS);
99 upriv->pm1_en = inw(upriv->acpi_base + PM1_EN);
100 upriv->pm1_cnt = inw(upriv->acpi_base + PM1_CNT);
102 log_debug("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
103 upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt);
105 for (i = 0; i < GPE0_REG_MAX; i++) {
106 upriv->gpe0_sts[i] = inl(upriv->acpi_base + GPE0_STS + i * 4);
107 upriv->gpe0_en[i] = inl(upriv->acpi_base + GPE0_EN + i * 4);
108 log_debug("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i,
109 upriv->gpe0_sts[i], i, upriv->gpe0_en[i]);
113 int pmc_disable_tco_base(ulong tco_base)
115 struct tco_regs *regs = (struct tco_regs *)tco_base;
117 debug("tco_base %lx = %x\n", (ulong)®s->tco1_cnt, TCO1_CNT_HLT);
118 setio_32(®s->tco1_cnt, TCO1_CNT_HLT);
123 int pmc_init(struct udevice *dev)
125 const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
128 pmc_fill_pm_reg_info(dev);
132 ret = ops->init(dev);
134 return log_msg_ret("Failed to init pmc", ret);
143 int pmc_prev_sleep_state(struct udevice *dev)
145 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
146 const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
147 int prev_sleep_state = ACPI_S0; /* Default to S0 */
149 if (upriv->pm1_sts & WAK_STS) {
150 switch (acpi_sleep_from_pm1(upriv->pm1_cnt)) {
152 if (IS_ENABLED(HAVE_ACPI_RESUME))
153 prev_sleep_state = ACPI_S3;
156 prev_sleep_state = ACPI_S5;
163 outl(upriv->pm1_cnt & ~SLP_TYP, upriv->acpi_base + PM1_CNT);
166 if (!ops->prev_sleep_state)
167 return prev_sleep_state;
169 return ops->prev_sleep_state(dev, prev_sleep_state);
172 int pmc_disable_tco(struct udevice *dev)
174 const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
176 pmc_fill_pm_reg_info(dev);
177 if (!ops->disable_tco)
180 return ops->disable_tco(dev);
183 int pmc_global_reset_set_enable(struct udevice *dev, bool enable)
185 const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
187 if (!ops->global_reset_set_enable)
190 return ops->global_reset_set_enable(dev, enable);
193 void pmc_dump_info(struct udevice *dev)
195 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
198 printf("Device: %s\n", dev->name);
199 printf("ACPI base %x, pmc_bar0 %p, pmc_bar2 %p, gpe_cfg %p\n",
200 upriv->acpi_base, upriv->pmc_bar0, upriv->pmc_bar2,
202 printf("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
203 upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt);
205 for (i = 0; i < GPE0_REG_MAX; i++) {
206 printf("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i,
207 upriv->gpe0_sts[i], i, upriv->gpe0_en[i]);
210 printf("prsts: %08x\n", upriv->prsts);
211 printf("tco_sts: %04x %04x\n", upriv->tco1_sts, upriv->tco2_sts);
212 printf("gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
213 upriv->gen_pmcon1, upriv->gen_pmcon2, upriv->gen_pmcon3);
216 int pmc_ofdata_to_uc_platdata(struct udevice *dev)
218 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
221 ret = dev_read_u32(dev, "gpe0-dwx-mask", &upriv->gpe0_dwx_mask);
223 return log_msg_ret("no gpe0-dwx-mask", ret);
224 ret = dev_read_u32(dev, "gpe0-dwx-shift-base",
225 &upriv->gpe0_dwx_shift_base);
227 return log_msg_ret("no gpe0-dwx-shift-base", ret);
228 ret = dev_read_u32(dev, "gpe0-sts", &upriv->gpe0_sts_reg);
230 return log_msg_ret("no gpe0-sts", ret);
231 upriv->gpe0_sts_reg += upriv->acpi_base;
232 ret = dev_read_u32(dev, "gpe0-en", &upriv->gpe0_en_reg);
234 return log_msg_ret("no gpe0-en", ret);
235 upriv->gpe0_en_reg += upriv->acpi_base;
240 UCLASS_DRIVER(acpi_pmc) = {
241 .id = UCLASS_ACPI_PMC,
243 .per_device_auto_alloc_size = sizeof(struct acpi_pmc_upriv),