drivers/power/acpi_pmc/acpi-pmc-uclass.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Google LLC
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_ACPI_PMC
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <acpi/acpi_s3.h>
  12 #ifdef CONFIG_X86
  13 #include <asm/intel_pinctrl.h>
  14 #endif
  15 #include <asm/io.h>
  16 #include <power/acpi_pmc.h>
  17
  18 enum {
  19         PM1_STS         = 0x00,
  20         PM1_EN          = 0x02,
  21         PM1_CNT         = 0x04,
  22
  23         GPE0_STS        = 0x20,
  24         GPE0_EN         = 0x30,
  25 };
  26
  27 struct tco_regs {
  28         u32 tco_rld;
  29         u32 tco_sts;
  30         u32 tco1_cnt;
  31         u32 tco_tmr;
  32 };
  33
  34 enum {
  35         TCO_STS_TIMEOUT                 = 1 << 3,
  36         TCO_STS_SECOND_TO_STS           = 1 << 17,
  37         TCO1_CNT_HLT                    = 1 << 11,
  38 };
  39
  40 #ifdef CONFIG_X86
  41 static int gpe0_shift(struct acpi_pmc_upriv *upriv, int regnum)
  42 {
  43         return upriv->gpe0_dwx_shift_base + regnum * 4;
  44 }
  45
  46 int pmc_gpe_init(struct udevice *dev)
  47 {
  48         struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
  49         struct udevice *itss;
  50         u32 *dw;
  51         u32 gpio_cfg_mask;
  52         u32 gpio_cfg;
  53         int ret, i;
  54         u32 mask;
  55
  56         if (device_get_uclass_id(dev) != UCLASS_ACPI_PMC)
  57                 return log_msg_ret("uclass", -EPROTONOSUPPORT);
  58         dw = upriv->gpe0_dw;
  59         mask = upriv->gpe0_dwx_mask;
  60         gpio_cfg_mask = 0;
  61         for (i = 0; i < upriv->gpe0_count; i++) {
  62                 gpio_cfg_mask |= mask << gpe0_shift(upriv, i);
  63                 if (dw[i] & ~mask)
  64                         return log_msg_ret("Base GPE0 value", -EINVAL);
  65         }
  66
  67         /*
  68          * Route the GPIOs to the GPE0 block. Determine that all values
  69          * are different and if they aren't, use the reset values.
  70          */
  71         if (dw[0] == dw[1] || dw[1] == dw[2]) {
  72                 log_info("PMC: Using default GPE route");
  73                 gpio_cfg = readl(upriv->gpe_cfg);
  74                 for (i = 0; i < upriv->gpe0_count; i++)
  75                         dw[i] = gpio_cfg >> gpe0_shift(upriv, i);
  76         } else {
  77                 gpio_cfg = 0;
  78                 for (i = 0; i < upriv->gpe0_count; i++)
  79                         gpio_cfg |= dw[i] << gpe0_shift(upriv, i);
  80                 clrsetbits_le32(upriv->gpe_cfg, gpio_cfg_mask, gpio_cfg);
  81         }
  82
  83         /* Set the routes in the GPIO communities as well */
  84         ret = uclass_first_device_err(UCLASS_IRQ, &itss);
  85         if (ret)
  86                 return log_msg_ret("Cannot find itss", ret);
  87         pinctrl_route_gpe(itss, dw[0], dw[1], dw[2]);
  88
  89         return 0;
  90 }
  91 #endif /* CONFIG_X86 */
  92
  93 static void pmc_fill_pm_reg_info(struct udevice *dev)
  94 {
  95         struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
  96         int i;
  97
  98         upriv->pm1_sts = inw(upriv->acpi_base + PM1_STS);
  99         upriv->pm1_en = inw(upriv->acpi_base + PM1_EN);
 100         upriv->pm1_cnt = inw(upriv->acpi_base + PM1_CNT);
 101
 102         log_debug("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
 103                   upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt);
 104
 105         for (i = 0; i < GPE0_REG_MAX; i++) {
 106                 upriv->gpe0_sts[i] = inl(upriv->acpi_base + GPE0_STS + i * 4);
 107                 upriv->gpe0_en[i] = inl(upriv->acpi_base + GPE0_EN + i * 4);
 108                 log_debug("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i,
 109                           upriv->gpe0_sts[i], i, upriv->gpe0_en[i]);
 110         }
 111 }
 112
 113 int pmc_disable_tco_base(ulong tco_base)
 114 {
 115         struct tco_regs *regs = (struct tco_regs *)tco_base;
 116
 117         debug("tco_base %lx = %x\n", (ulong)&regs->tco1_cnt, TCO1_CNT_HLT);
 118         setio_32(&regs->tco1_cnt, TCO1_CNT_HLT);
 119
 120         return 0;
 121 }
 122
 123 int pmc_init(struct udevice *dev)
 124 {
 125         const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
 126         int ret;
 127
 128         pmc_fill_pm_reg_info(dev);
 129         if (!ops->init)
 130                 return -ENOSYS;
 131
 132         ret = ops->init(dev);
 133         if (ret)
 134                 return log_msg_ret("Failed to init pmc", ret);
 135
 136 #ifdef DEBUG
 137         pmc_dump_info(dev);
 138 #endif
 139
 140         return 0;
 141 }
 142
 143 int pmc_prev_sleep_state(struct udevice *dev)
 144 {
 145         struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
 146         const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
 147         int prev_sleep_state = ACPI_S0; /* Default to S0 */
 148
 149         if (upriv->pm1_sts & WAK_STS) {
 150                 switch (acpi_sleep_from_pm1(upriv->pm1_cnt)) {
 151                 case ACPI_S3:
 152                         if (IS_ENABLED(HAVE_ACPI_RESUME))
 153                                 prev_sleep_state = ACPI_S3;
 154                         break;
 155                 case ACPI_S5:
 156                         prev_sleep_state = ACPI_S5;
 157                         break;
 158                 default:
 159                         break;
 160                 }
 161
 162                 /* Clear SLP_TYP */
 163                 outl(upriv->pm1_cnt & ~SLP_TYP, upriv->acpi_base + PM1_CNT);
 164         }
 165
 166         if (!ops->prev_sleep_state)
 167                 return prev_sleep_state;
 168
 169         return ops->prev_sleep_state(dev, prev_sleep_state);
 170 }
 171
 172 int pmc_disable_tco(struct udevice *dev)
 173 {
 174         const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
 175
 176         pmc_fill_pm_reg_info(dev);
 177         if (!ops->disable_tco)
 178                 return -ENOSYS;
 179
 180         return ops->disable_tco(dev);
 181 }
 182
 183 int pmc_global_reset_set_enable(struct udevice *dev, bool enable)
 184 {
 185         const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
 186
 187         if (!ops->global_reset_set_enable)
 188                 return -ENOSYS;
 189
 190         return ops->global_reset_set_enable(dev, enable);
 191 }
 192
 193 void pmc_dump_info(struct udevice *dev)
 194 {
 195         struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
 196         int i;
 197
 198         printf("Device: %s\n", dev->name);
 199         printf("ACPI base %x, pmc_bar0 %p, pmc_bar2 %p, gpe_cfg %p\n",
 200                upriv->acpi_base, upriv->pmc_bar0, upriv->pmc_bar2,
 201                upriv->gpe_cfg);
 202         printf("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
 203                upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt);
 204
 205         for (i = 0; i < GPE0_REG_MAX; i++) {
 206                 printf("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i,
 207                        upriv->gpe0_sts[i], i, upriv->gpe0_en[i]);
 208         }
 209
 210         printf("prsts: %08x\n", upriv->prsts);
 211         printf("tco_sts:   %04x %04x\n", upriv->tco1_sts, upriv->tco2_sts);
 212         printf("gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
 213                upriv->gen_pmcon1, upriv->gen_pmcon2, upriv->gen_pmcon3);
 214 }
 215
 216 int pmc_ofdata_to_uc_platdata(struct udevice *dev)
 217 {
 218         struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
 219         int ret;
 220
 221         ret = dev_read_u32(dev, "gpe0-dwx-mask", &upriv->gpe0_dwx_mask);
 222         if (ret)
 223                 return log_msg_ret("no gpe0-dwx-mask", ret);
 224         ret = dev_read_u32(dev, "gpe0-dwx-shift-base",
 225                            &upriv->gpe0_dwx_shift_base);
 226         if (ret)
 227                 return log_msg_ret("no gpe0-dwx-shift-base", ret);
 228         ret = dev_read_u32(dev, "gpe0-sts", &upriv->gpe0_sts_reg);
 229         if (ret)
 230                 return log_msg_ret("no gpe0-sts", ret);
 231         upriv->gpe0_sts_reg += upriv->acpi_base;
 232         ret = dev_read_u32(dev, "gpe0-en", &upriv->gpe0_en_reg);
 233         if (ret)
 234                 return log_msg_ret("no gpe0-en", ret);
 235         upriv->gpe0_en_reg += upriv->acpi_base;
 236
 237         return 0;
 238 }
 239
 240 UCLASS_DRIVER(acpi_pmc) = {
 241         .id             = UCLASS_ACPI_PMC,
 242         .name           = "power-mgr",
 243         .per_device_auto_alloc_size     = sizeof(struct acpi_pmc_upriv),
 244 };