drivers/pinctrl/rockchip/pinctrl_rv1108.c

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  * Author: Andy Yan <andy.yan@rock-chips.com>
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <errno.h>
   9 #include <syscon.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/grf_rv1108.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/periph.h>
  15 #include <dm/pinctrl.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 struct rv1108_pinctrl_priv {
  20         struct rv1108_grf *grf;
  21 };
  22
  23 /* GRF_GPIO1B_IOMUX */
  24 enum {
  25         GPIO1B7_SHIFT           = 14,
  26         GPIO1B7_MASK            = 3 << GPIO1B7_SHIFT,
  27         GPIO1B7_GPIO            = 0,
  28         GPIO1B7_LCDC_D12,
  29         GPIO1B7_I2S_SDIO2_M0,
  30         GPIO1B7_GMAC_RXDV,
  31
  32         GPIO1B6_SHIFT           = 12,
  33         GPIO1B6_MASK            = 3 << GPIO1B6_SHIFT,
  34         GPIO1B6_GPIO            = 0,
  35         GPIO1B6_LCDC_D13,
  36         GPIO1B6_I2S_LRCLKTX_M0,
  37         GPIO1B6_GMAC_RXD1,
  38
  39         GPIO1B5_SHIFT           = 10,
  40         GPIO1B5_MASK            = 3 << GPIO1B5_SHIFT,
  41         GPIO1B5_GPIO            = 0,
  42         GPIO1B5_LCDC_D14,
  43         GPIO1B5_I2S_SDIO1_M0,
  44         GPIO1B5_GMAC_RXD0,
  45
  46         GPIO1B4_SHIFT           = 8,
  47         GPIO1B4_MASK            = 3 << GPIO1B4_SHIFT,
  48         GPIO1B4_GPIO            = 0,
  49         GPIO1B4_LCDC_D15,
  50         GPIO1B4_I2S_MCLK_M0,
  51         GPIO1B4_GMAC_TXEN,
  52
  53         GPIO1B3_SHIFT           = 6,
  54         GPIO1B3_MASK            = 3 << GPIO1B3_SHIFT,
  55         GPIO1B3_GPIO            = 0,
  56         GPIO1B3_LCDC_D16,
  57         GPIO1B3_I2S_SCLK_M0,
  58         GPIO1B3_GMAC_TXD1,
  59
  60         GPIO1B2_SHIFT           = 4,
  61         GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
  62         GPIO1B2_GPIO            = 0,
  63         GPIO1B2_LCDC_D17,
  64         GPIO1B2_I2S_SDIO_M0,
  65         GPIO1B2_GMAC_TXD0,
  66
  67         GPIO1B1_SHIFT           = 2,
  68         GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
  69         GPIO1B1_GPIO            = 0,
  70         GPIO1B1_LCDC_D9,
  71         GPIO1B1_PWM7,
  72
  73         GPIO1B0_SHIFT           = 0,
  74         GPIO1B0_MASK            = 3,
  75         GPIO1B0_GPIO            = 0,
  76         GPIO1B0_LCDC_D8,
  77         GPIO1B0_PWM6,
  78 };
  79
  80 /* GRF_GPIO1C_IOMUX */
  81 enum {
  82         GPIO1C7_SHIFT           = 14,
  83         GPIO1C7_MASK            = 3 << GPIO1C7_SHIFT,
  84         GPIO1C7_GPIO            = 0,
  85         GPIO1C7_CIF_D5,
  86         GPIO1C7_I2S_SDIO2_M1,
  87
  88         GPIO1C6_SHIFT           = 12,
  89         GPIO1C6_MASK            = 3 << GPIO1C6_SHIFT,
  90         GPIO1C6_GPIO            = 0,
  91         GPIO1C6_CIF_D4,
  92         GPIO1C6_I2S_LRCLKTX_M1,
  93
  94         GPIO1C5_SHIFT           = 10,
  95         GPIO1C5_MASK            = 3 << GPIO1C5_SHIFT,
  96         GPIO1C5_GPIO            = 0,
  97         GPIO1C5_LCDC_CLK,
  98         GPIO1C5_GMAC_CLK,
  99
 100         GPIO1C4_SHIFT           = 8,
 101         GPIO1C4_MASK            = 3 << GPIO1C4_SHIFT,
 102         GPIO1C4_GPIO            = 0,
 103         GPIO1C4_LCDC_HSYNC,
 104         GPIO1C4_GMAC_MDC,
 105
 106         GPIO1C3_SHIFT           = 6,
 107         GPIO1C3_MASK            = 3 << GPIO1C3_SHIFT,
 108         GPIO1C3_GPIO            = 0,
 109         GPIO1C3_LCDC_VSYNC,
 110         GPIO1C3_GMAC_MDIO,
 111
 112         GPIO1C2_SHIFT           = 4,
 113         GPIO1C2_MASK            = 3 << GPIO1C2_SHIFT,
 114         GPIO1C2_GPIO            = 0,
 115         GPIO1C2_LCDC_EN,
 116         GPIO1C2_I2S_SDIO3_M0,
 117         GPIO1C2_GMAC_RXER,
 118
 119         GPIO1C1_SHIFT           = 2,
 120         GPIO1C1_MASK            = 3 << GPIO1C1_SHIFT,
 121         GPIO1C1_GPIO            = 0,
 122         GPIO1C1_LCDC_D10,
 123         GPIO1C1_I2S_SDI_M0,
 124         GPIO1C1_PWM4,
 125
 126         GPIO1C0_SHIFT           = 0,
 127         GPIO1C0_MASK            = 3,
 128         GPIO1C0_GPIO            = 0,
 129         GPIO1C0_LCDC_D11,
 130         GPIO1C0_I2S_LRCLKRX_M0,
 131 };
 132
 133 /* GRF_GPIO1D_OIMUX */
 134 enum {
 135         GPIO1D7_SHIFT           = 14,
 136         GPIO1D7_MASK            = 3 << GPIO1D7_SHIFT,
 137         GPIO1D7_GPIO            = 0,
 138         GPIO1D7_HDMI_CEC,
 139         GPIO1D7_DSP_RTCK,
 140
 141         GPIO1D6_SHIFT           = 12,
 142         GPIO1D6_MASK            = 1 << GPIO1D6_SHIFT,
 143         GPIO1D6_GPIO            = 0,
 144         GPIO1D6_HDMI_HPD_M0,
 145
 146         GPIO1D5_SHIFT           = 10,
 147         GPIO1D5_MASK            = 3 << GPIO1D5_SHIFT,
 148         GPIO1D5_GPIO            = 0,
 149         GPIO1D5_UART2_RTSN,
 150         GPIO1D5_HDMI_SDA_M0,
 151
 152         GPIO1D4_SHIFT           = 8,
 153         GPIO1D4_MASK            = 3 << GPIO1D4_SHIFT,
 154         GPIO1D4_GPIO            = 0,
 155         GPIO1D4_UART2_CTSN,
 156         GPIO1D4_HDMI_SCL_M0,
 157
 158         GPIO1D3_SHIFT           = 6,
 159         GPIO1D3_MASK            = 3 << GPIO1D3_SHIFT,
 160         GPIO1D3_GPIO            = 0,
 161         GPIO1D3_UART0_SOUT,
 162         GPIO1D3_SPI_TXD_M0,
 163
 164         GPIO1D2_SHIFT           = 4,
 165         GPIO1D2_MASK            = 3 << GPIO1D2_SHIFT,
 166         GPIO1D2_GPIO            = 0,
 167         GPIO1D2_UART0_SIN,
 168         GPIO1D2_SPI_RXD_M0,
 169         GPIO1D2_DSP_TDI,
 170
 171         GPIO1D1_SHIFT           = 2,
 172         GPIO1D1_MASK            = 3 << GPIO1D1_SHIFT,
 173         GPIO1D1_GPIO            = 0,
 174         GPIO1D1_UART0_RTSN,
 175         GPIO1D1_SPI_CSN0_M0,
 176         GPIO1D1_DSP_TMS,
 177
 178         GPIO1D0_SHIFT           = 0,
 179         GPIO1D0_MASK            = 3,
 180         GPIO1D0_GPIO            = 0,
 181         GPIO1D0_UART0_CTSN,
 182         GPIO1D0_SPI_CLK_M0,
 183         GPIO1D0_DSP_TCK,
 184 };
 185
 186 /* GRF_GPIO2A_IOMUX */
 187 enum {
 188         GPIO2A7_SHIFT           = 14,
 189         GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
 190         GPIO2A7_GPIO            = 0,
 191         GPIO2A7_FLASH_D7,
 192         GPIO2A7_EMMC_D7,
 193
 194         GPIO2A6_SHIFT           = 12,
 195         GPIO2A6_MASK            = 3 << GPIO2A6_SHIFT,
 196         GPIO2A6_GPIO            = 0,
 197         GPIO2A6_FLASH_D6,
 198         GPIO2A6_EMMC_D6,
 199
 200         GPIO2A5_SHIFT           = 10,
 201         GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
 202         GPIO2A5_GPIO            = 0,
 203         GPIO2A5_FLASH_D5,
 204         GPIO2A5_EMMC_D5,
 205
 206         GPIO2A4_SHIFT           = 8,
 207         GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
 208         GPIO2A4_GPIO            = 0,
 209         GPIO2A4_FLASH_D4,
 210         GPIO2A4_EMMC_D4,
 211
 212         GPIO2A3_SHIFT           = 6,
 213         GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
 214         GPIO2A3_GPIO            = 0,
 215         GPIO2A3_FLASH_D3,
 216         GPIO2A3_EMMC_D3,
 217         GPIO2A3_SFC_HOLD_IO3,
 218
 219         GPIO2A2_SHIFT           = 4,
 220         GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
 221         GPIO2A2_GPIO            = 0,
 222         GPIO2A2_FLASH_D2,
 223         GPIO2A2_EMMC_D2,
 224         GPIO2A2_SFC_WP_IO2,
 225
 226         GPIO2A1_SHIFT           = 2,
 227         GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
 228         GPIO2A1_GPIO            = 0,
 229         GPIO2A1_FLASH_D1,
 230         GPIO2A1_EMMC_D1,
 231         GPIO2A1_SFC_SO_IO1,
 232
 233         GPIO2A0_SHIFT           = 0,
 234         GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
 235         GPIO2A0_GPIO            = 0,
 236         GPIO2A0_FLASH_D0,
 237         GPIO2A0_EMMC_D0,
 238         GPIO2A0_SFC_SI_IO0,
 239 };
 240
 241 /* GRF_GPIO2D_IOMUX */
 242 enum {
 243         GPIO2B7_SHIFT           = 14,
 244         GPIO2B7_MASK            = 3 << GPIO2B7_SHIFT,
 245         GPIO2B7_GPIO            = 0,
 246         GPIO2B7_FLASH_CS1,
 247         GPIO2B7_SFC_CLK,
 248
 249         GPIO2B6_SHIFT           = 12,
 250         GPIO2B6_MASK            = 1 << GPIO2B6_SHIFT,
 251         GPIO2B6_GPIO            = 0,
 252         GPIO2B6_EMMC_CLKO,
 253
 254         GPIO2B5_SHIFT           = 10,
 255         GPIO2B5_MASK            = 1 << GPIO2B5_SHIFT,
 256         GPIO2B5_GPIO            = 0,
 257         GPIO2B5_FLASH_CS0,
 258
 259         GPIO2B4_SHIFT           = 8,
 260         GPIO2B4_MASK            = 3 << GPIO2B4_SHIFT,
 261         GPIO2B4_GPIO            = 0,
 262         GPIO2B4_FLASH_RDY,
 263         GPIO2B4_EMMC_CMD,
 264         GPIO2B4_SFC_CSN0,
 265
 266         GPIO2B3_SHIFT           = 6,
 267         GPIO2B3_MASK            = 1 << GPIO2B3_SHIFT,
 268         GPIO2B3_GPIO            = 0,
 269         GPIO2B3_FLASH_RDN,
 270
 271         GPIO2B2_SHIFT           = 4,
 272         GPIO2B2_MASK            = 1 << GPIO2B2_SHIFT,
 273         GPIO2B2_GPIO            = 0,
 274         GPIO2B2_FLASH_WRN,
 275
 276         GPIO2B1_SHIFT           = 2,
 277         GPIO2B1_MASK            = 1 << GPIO2B1_SHIFT,
 278         GPIO2B1_GPIO            = 0,
 279         GPIO2B1_FLASH_CLE,
 280
 281         GPIO2B0_SHIFT           = 0,
 282         GPIO2B0_MASK            = 1 << GPIO2B0_SHIFT,
 283         GPIO2B0_GPIO            = 0,
 284         GPIO2B0_FLASH_ALE,
 285 };
 286
 287 /* GRF_GPIO2D_IOMUX */
 288 enum {
 289         GPIO2D7_SHIFT           = 14,
 290         GPIO2D7_MASK            = 1 << GPIO2D7_SHIFT,
 291         GPIO2D7_GPIO            = 0,
 292         GPIO2D7_SDIO_D0,
 293
 294         GPIO2D6_SHIFT           = 12,
 295         GPIO2D6_MASK            = 1 << GPIO2D6_SHIFT,
 296         GPIO2D6_GPIO            = 0,
 297         GPIO2D6_SDIO_CMD,
 298
 299         GPIO2D5_SHIFT           = 10,
 300         GPIO2D5_MASK            = 1 << GPIO2D5_SHIFT,
 301         GPIO2D5_GPIO            = 0,
 302         GPIO2D5_SDIO_CLKO,
 303
 304         GPIO2D4_SHIFT           = 8,
 305         GPIO2D4_MASK            = 1 << GPIO2D4_SHIFT,
 306         GPIO2D4_GPIO            = 0,
 307         GPIO2D4_I2C1_SCL,
 308
 309         GPIO2D3_SHIFT           = 6,
 310         GPIO2D3_MASK            = 1 << GPIO2D3_SHIFT,
 311         GPIO2D3_GPIO            = 0,
 312         GPIO2D3_I2C1_SDA,
 313
 314         GPIO2D2_SHIFT           = 4,
 315         GPIO2D2_MASK            = 3 << GPIO2D2_SHIFT,
 316         GPIO2D2_GPIO            = 0,
 317         GPIO2D2_UART2_SOUT_M0,
 318         GPIO2D2_JTAG_TCK,
 319
 320         GPIO2D1_SHIFT           = 2,
 321         GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
 322         GPIO2D1_GPIO            = 0,
 323         GPIO2D1_UART2_SIN_M0,
 324         GPIO2D1_JTAG_TMS,
 325         GPIO2D1_DSP_TMS,
 326
 327         GPIO2D0_SHIFT           = 0,
 328         GPIO2D0_MASK            = 3,
 329         GPIO2D0_GPIO            = 0,
 330         GPIO2D0_UART0_CTSN,
 331         GPIO2D0_SPI_CLK_M0,
 332         GPIO2D0_DSP_TCK,
 333 };
 334
 335 /* GRF_GPIO3A_IOMUX */
 336 enum {
 337         GPIO3A7_SHIFT           = 14,
 338         GPIO3A7_MASK            = 1 << GPIO3A7_SHIFT,
 339         GPIO3A7_GPIO            = 0,
 340
 341         GPIO3A6_SHIFT           = 12,
 342         GPIO3A6_MASK            = 1 << GPIO3A6_SHIFT,
 343         GPIO3A6_GPIO            = 0,
 344         GPIO3A6_UART1_SOUT,
 345
 346         GPIO3A5_SHIFT           = 10,
 347         GPIO3A5_MASK            = 1 << GPIO3A5_SHIFT,
 348         GPIO3A5_GPIO            = 0,
 349         GPIO3A5_UART1_SIN,
 350
 351         GPIO3A4_SHIFT           = 8,
 352         GPIO3A4_MASK            = 1 << GPIO3A4_SHIFT,
 353         GPIO3A4_GPIO            = 0,
 354         GPIO3A4_UART1_CTSN,
 355
 356         GPIO3A3_SHIFT           = 6,
 357         GPIO3A3_MASK            = 1 << GPIO3A3_SHIFT,
 358         GPIO3A3_GPIO            = 0,
 359         GPIO3A3_UART1_RTSN,
 360
 361         GPIO3A2_SHIFT           = 4,
 362         GPIO3A2_MASK            = 1 << GPIO3A2_SHIFT,
 363         GPIO3A2_GPIO            = 0,
 364         GPIO3A2_SDIO_D3,
 365
 366         GPIO3A1_SHIFT           = 2,
 367         GPIO3A1_MASK            = 1 << GPIO3A1_SHIFT,
 368         GPIO3A1_GPIO            = 0,
 369         GPIO3A1_SDIO_D2,
 370
 371         GPIO3A0_SHIFT           = 0,
 372         GPIO3A0_MASK            = 1,
 373         GPIO3A0_GPIO            = 0,
 374         GPIO3A0_SDIO_D1,
 375 };
 376
 377 /* GRF_GPIO3C_IOMUX */
 378 enum {
 379         GPIO3C7_SHIFT           = 14,
 380         GPIO3C7_MASK            = 1 << GPIO3C7_SHIFT,
 381         GPIO3C7_GPIO            = 0,
 382         GPIO3C7_CIF_CLKI,
 383
 384         GPIO3C6_SHIFT           = 12,
 385         GPIO3C6_MASK            = 1 << GPIO3C6_SHIFT,
 386         GPIO3C6_GPIO            = 0,
 387         GPIO3C6_CIF_VSYNC,
 388
 389         GPIO3C5_SHIFT           = 10,
 390         GPIO3C5_MASK            = 1 << GPIO3C5_SHIFT,
 391         GPIO3C5_GPIO            = 0,
 392         GPIO3C5_SDMMC_CMD,
 393
 394         GPIO3C4_SHIFT           = 8,
 395         GPIO3C4_MASK            = 1 << GPIO3C4_SHIFT,
 396         GPIO3C4_GPIO            = 0,
 397         GPIO3C4_SDMMC_CLKO,
 398
 399         GPIO3C3_SHIFT           = 6,
 400         GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
 401         GPIO3C3_GPIO            = 0,
 402         GPIO3C3_SDMMC_D0,
 403         GPIO3C3_UART2_SOUT_M1,
 404
 405         GPIO3C2_SHIFT           = 4,
 406         GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
 407         GPIO3C2_GPIO            = 0,
 408         GPIO3C2_SDMMC_D1,
 409         GPIO3C2_UART2_SIN_M1,
 410
 411         GPIOC1_SHIFT            = 2,
 412         GPIOC1_MASK             = 1 << GPIOC1_SHIFT,
 413         GPIOC1_GPIO             = 0,
 414         GPIOC1_SDMMC_D2,
 415
 416         GPIOC0_SHIFT            = 0,
 417         GPIOC0_MASK             = 1,
 418         GPIO3C0_GPIO            = 0,
 419         GPIO3C0_SDMMC_D3,
 420 };
 421
 422 static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id)
 423 {
 424         switch (uart_id) {
 425         case PERIPH_ID_UART0:
 426                 rk_clrsetreg(&grf->gpio3a_iomux,
 427                              GPIO3A6_MASK | GPIO3A5_MASK,
 428                              GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
 429                              GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
 430                 break;
 431         case PERIPH_ID_UART1:
 432                 rk_clrsetreg(&grf->gpio1d_iomux,
 433                              GPIO1D3_MASK | GPIO1D2_MASK | GPIO1D1_MASK |
 434                              GPIO1D0_MASK,
 435                              GPIO1D3_UART0_SOUT << GPIO1D3_SHIFT |
 436                              GPIO1D2_UART0_SIN << GPIO1D2_SHIFT |
 437                              GPIO1D1_UART0_RTSN << GPIO1D1_SHIFT |
 438                              GPIO1D0_UART0_CTSN << GPIO1D0_SHIFT);
 439                 break;
 440         case PERIPH_ID_UART2:
 441                 rk_clrsetreg(&grf->gpio2d_iomux,
 442                              GPIO2D2_MASK | GPIO2D1_MASK,
 443                              GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
 444                              GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
 445                 break;
 446         }
 447 }
 448
 449 static void pinctrl_rv1108_gmac_config(struct rv1108_grf *grf, int func)
 450 {
 451         rk_clrsetreg(&grf->gpio1b_iomux,
 452                      GPIO1B7_MASK | GPIO1B6_MASK | GPIO1B5_MASK |
 453                      GPIO1B4_MASK | GPIO1B3_MASK | GPIO1B2_MASK,
 454                      GPIO1B7_GMAC_RXDV << GPIO1B7_SHIFT |
 455                      GPIO1B6_GMAC_RXD1 << GPIO1B6_SHIFT |
 456                      GPIO1B5_GMAC_RXD0 << GPIO1B5_SHIFT |
 457                      GPIO1B4_GMAC_TXEN << GPIO1B4_SHIFT |
 458                      GPIO1B3_GMAC_TXD1 << GPIO1B3_SHIFT |
 459                      GPIO1B2_GMAC_TXD0 << GPIO1B2_SHIFT);
 460         rk_clrsetreg(&grf->gpio1c_iomux,
 461                      GPIO1C5_MASK | GPIO1C4_MASK |
 462                      GPIO1C3_MASK | GPIO1C2_MASK,
 463                      GPIO1C5_GMAC_CLK << GPIO1C5_SHIFT |
 464                      GPIO1C4_GMAC_MDC << GPIO1C4_SHIFT |
 465                      GPIO1C3_GMAC_MDIO << GPIO1C3_SHIFT |
 466                      GPIO1C2_GMAC_RXER << GPIO1C2_SHIFT);
 467         writel(0xffff57f5, &grf->gpio1b_drv);
 468 }
 469
 470 static void pinctrl_rv1108_sfc_config(struct rv1108_grf *grf)
 471 {
 472         rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK |
 473                      GPIO2A1_MASK | GPIO2A0_MASK,
 474                      GPIO2A3_SFC_HOLD_IO3 << GPIO2A3_SHIFT |
 475                      GPIO2A2_SFC_WP_IO2 << GPIO2A2_SHIFT |
 476                      GPIO2A1_SFC_SO_IO1 << GPIO2A1_SHIFT |
 477                      GPIO2A0_SFC_SI_IO0 << GPIO2A0_SHIFT);
 478         rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK,
 479                      GPIO2B7_SFC_CLK << GPIO2B7_SHIFT |
 480                      GPIO2B4_SFC_CSN0 << GPIO2B4_SHIFT);
 481 }
 482
 483 static int rv1108_pinctrl_request(struct udevice *dev, int func, int flags)
 484 {
 485         struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
 486
 487         switch (func) {
 488         case PERIPH_ID_UART0:
 489         case PERIPH_ID_UART1:
 490         case PERIPH_ID_UART2:
 491                 pinctrl_rv1108_uart_config(priv->grf, func);
 492                 break;
 493         case PERIPH_ID_GMAC:
 494                 pinctrl_rv1108_gmac_config(priv->grf, func);
 495         case PERIPH_ID_SFC:
 496                 pinctrl_rv1108_sfc_config(priv->grf);
 497         default:
 498                 return -EINVAL;
 499         }
 500
 501         return 0;
 502 }
 503
 504 static int rv1108_pinctrl_get_periph_id(struct udevice *dev,
 505                                         struct udevice *periph)
 506 {
 507         u32 cell[3];
 508         int ret;
 509
 510         ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 511         if (ret < 0)
 512                 return -EINVAL;
 513
 514         switch (cell[1]) {
 515         case 11:
 516                 return PERIPH_ID_SDCARD;
 517         case 13:
 518                 return PERIPH_ID_EMMC;
 519         case 19:
 520                 return PERIPH_ID_GMAC;
 521         case 30:
 522                 return PERIPH_ID_I2C0;
 523         case 31:
 524                 return PERIPH_ID_I2C1;
 525         case 32:
 526                 return PERIPH_ID_I2C2;
 527         case 39:
 528                 return PERIPH_ID_PWM0;
 529         case 44:
 530                 return PERIPH_ID_UART0;
 531         case 45:
 532                 return PERIPH_ID_UART1;
 533         case 46:
 534                 return PERIPH_ID_UART2;
 535         case 56:
 536                 return PERIPH_ID_SFC;
 537         }
 538
 539         return -ENOENT;
 540 }
 541
 542 static int rv1108_pinctrl_set_state_simple(struct udevice *dev,
 543                                            struct udevice *periph)
 544 {
 545         int func;
 546
 547         func = rv1108_pinctrl_get_periph_id(dev, periph);
 548         if (func < 0)
 549                 return func;
 550
 551         return rv1108_pinctrl_request(dev, func, 0);
 552 }
 553
 554 static struct pinctrl_ops rv1108_pinctrl_ops = {
 555         .set_state_simple       = rv1108_pinctrl_set_state_simple,
 556         .request                = rv1108_pinctrl_request,
 557         .get_periph_id          = rv1108_pinctrl_get_periph_id,
 558 };
 559
 560 static int rv1108_pinctrl_probe(struct udevice *dev)
 561 {
 562         struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
 563
 564         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 565
 566         return 0;
 567 }
 568
 569 static const struct udevice_id rv1108_pinctrl_ids[] = {
 570         {.compatible = "rockchip,rv1108-pinctrl" },
 571         { }
 572 };
 573
 574 U_BOOT_DRIVER(pinctrl_rv1108) = {
 575         .name           = "pinctrl_rv1108",
 576         .id             = UCLASS_PINCTRL,
 577         .of_match       = rv1108_pinctrl_ids,
 578         .priv_auto_alloc_size = sizeof(struct rv1108_pinctrl_priv),
 579         .ops            = &rv1108_pinctrl_ops,
 580         .bind           = dm_scan_fdt_dev,
 581         .probe          = rv1108_pinctrl_probe,
 582 };