2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/grf_rk3399.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/periph.h>
15 #include <asm/arch/clock.h>
16 #include <dm/pinctrl.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 struct rk3399_pinctrl_priv {
21 struct rk3399_grf_regs *grf;
22 struct rk3399_pmugrf_regs *pmugrf;
25 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
26 struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
30 rk_clrsetreg(&grf->gpio4c_iomux,
32 GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
35 rk_clrsetreg(&grf->gpio4c_iomux,
37 GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
40 rk_clrsetreg(&pmugrf->gpio1c_iomux,
41 PMUGRF_GPIO1C3_SEL_MASK,
42 PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
45 if (readl(&pmugrf->soc_con0) & (1 << 5))
46 rk_clrsetreg(&pmugrf->gpio1b_iomux,
47 PMUGRF_GPIO1B6_SEL_MASK,
48 PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
50 rk_clrsetreg(&pmugrf->gpio0a_iomux,
51 PMUGRF_GPIO0A6_SEL_MASK,
52 PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
55 debug("pwm id = %d iomux error!\n", pwm_id);
60 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
61 struct rk3399_pmugrf_regs *pmugrf,
66 rk_clrsetreg(&pmugrf->gpio1b_iomux,
67 PMUGRF_GPIO1B7_SEL_MASK,
68 PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
69 rk_clrsetreg(&pmugrf->gpio1c_iomux,
70 PMUGRF_GPIO1C0_SEL_MASK,
71 PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
79 debug("i2c id = %d iomux error!\n", i2c_id);
84 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
90 debug("lcdc id = %d iomux error!\n", lcd_id);
95 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
96 struct rk3399_pmugrf_regs *pmugrf,
97 enum periph_id spi_id, int cs)
103 rk_clrsetreg(&grf->gpio3a_iomux,
104 GRF_GPIO3A7_SEL_MASK,
105 GRF_SPI0NORCODEC_CSN0
106 << GRF_GPIO3A7_SEL_SHIFT);
109 rk_clrsetreg(&grf->gpio3b_iomux,
110 GRF_GPIO3B0_SEL_MASK,
111 GRF_SPI0NORCODEC_CSN1
112 << GRF_GPIO3B0_SEL_SHIFT);
117 rk_clrsetreg(&grf->gpio3a_iomux,
118 GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
119 | GRF_GPIO3A6_SEL_SHIFT,
120 GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
121 | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
122 | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
127 rk_clrsetreg(&pmugrf->gpio1a_iomux,
128 PMUGRF_GPIO1A7_SEL_MASK,
129 PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
130 rk_clrsetreg(&pmugrf->gpio1b_iomux,
131 PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
132 | PMUGRF_GPIO1B2_SEL_MASK,
133 PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
134 | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
135 | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
140 rk_clrsetreg(&grf->gpio2b_iomux,
141 GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
142 | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
143 GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
144 | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
145 | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
146 | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
151 rk_clrsetreg(&grf->gpio2c_iomux,
152 GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
153 | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
154 GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
155 | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
156 | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
157 | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
160 printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
166 debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
170 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
171 struct rk3399_pmugrf_regs *pmugrf,
175 case PERIPH_ID_UART2:
176 /* Using channel-C by default */
177 rk_clrsetreg(&grf->gpio4c_iomux,
178 GRF_GPIO4C3_SEL_MASK,
179 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
180 rk_clrsetreg(&grf->gpio4c_iomux,
181 GRF_GPIO4C4_SEL_MASK,
182 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
184 case PERIPH_ID_UART0:
185 case PERIPH_ID_UART1:
186 case PERIPH_ID_UART3:
187 case PERIPH_ID_UART4:
189 debug("uart id = %d iomux error!\n", uart_id);
194 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
199 case PERIPH_ID_SDCARD:
200 rk_clrsetreg(&grf->gpio4b_iomux,
201 GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
202 | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
203 | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
204 GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
205 | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
206 | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
207 | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
208 | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
209 | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
212 debug("mmc id = %d iomux error!\n", mmc_id);
217 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
218 static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
220 rk_clrsetreg(&grf->gpio3a_iomux,
221 GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
222 GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
223 GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
224 GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
225 GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
226 GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
227 GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
228 GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
229 GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
230 GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
231 GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
232 GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
233 rk_clrsetreg(&grf->gpio3b_iomux,
234 GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
235 GRF_GPIO3B3_SEL_MASK |
236 GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
237 GRF_GPIO3B6_SEL_MASK,
238 GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
239 GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
240 GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
241 GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
242 GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
243 GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
244 rk_clrsetreg(&grf->gpio3c_iomux,
245 GRF_GPIO3C1_SEL_MASK,
246 GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
248 /* Set drive strength for GMAC tx io, value 3 means 13mA */
249 rk_clrsetreg(&grf->gpio3_e[0],
250 GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK |
251 GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK,
252 3 << GRF_GPIO3A0_E_SHIFT |
253 3 << GRF_GPIO3A1_E_SHIFT |
254 3 << GRF_GPIO3A4_E_SHIFT |
255 1 << GRF_GPIO3A5_E0_SHIFT);
256 rk_clrsetreg(&grf->gpio3_e[1],
257 GRF_GPIO3A5_E12_MASK,
258 1 << GRF_GPIO3A5_E12_SHIFT);
259 rk_clrsetreg(&grf->gpio3_e[2],
261 3 << GRF_GPIO3B4_E_SHIFT);
262 rk_clrsetreg(&grf->gpio3_e[4],
264 3 << GRF_GPIO3C1_E_SHIFT);
268 #if !defined(CONFIG_SPL_BUILD)
269 static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id)
273 rk_clrsetreg(&grf->gpio4c_iomux,
274 GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK,
275 (GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) |
276 (GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT));
279 debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id);
285 static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
287 struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
289 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
296 pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
304 pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
312 pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
314 case PERIPH_ID_UART0:
315 case PERIPH_ID_UART1:
316 case PERIPH_ID_UART2:
317 case PERIPH_ID_UART3:
318 case PERIPH_ID_UART4:
319 pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
321 case PERIPH_ID_LCDC0:
322 case PERIPH_ID_LCDC1:
323 pinctrl_rk3399_lcdc_config(priv->grf, func);
325 case PERIPH_ID_SDMMC0:
326 case PERIPH_ID_SDMMC1:
327 pinctrl_rk3399_sdmmc_config(priv->grf, func);
329 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
331 pinctrl_rk3399_gmac_config(priv->grf, func);
334 #if !defined(CONFIG_SPL_BUILD)
336 pinctrl_rk3399_hdmi_config(priv->grf, func);
346 static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
347 struct udevice *periph)
349 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
353 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
354 "interrupts", cell, ARRAY_SIZE(cell));
360 return PERIPH_ID_SPI0;
362 return PERIPH_ID_SPI1;
364 return PERIPH_ID_SPI2;
366 return PERIPH_ID_SPI5;
368 return PERIPH_ID_I2C0;
369 case 59: /* Note strange order */
370 return PERIPH_ID_I2C1;
372 return PERIPH_ID_I2C2;
374 return PERIPH_ID_I2C3;
376 return PERIPH_ID_I2C4;
378 return PERIPH_ID_I2C5;
380 return PERIPH_ID_SDMMC1;
381 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
383 return PERIPH_ID_GMAC;
385 #if !defined(CONFIG_SPL_BUILD)
387 return PERIPH_ID_HDMI;
394 static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
395 struct udevice *periph)
399 func = rk3399_pinctrl_get_periph_id(dev, periph);
403 return rk3399_pinctrl_request(dev, func, 0);
406 static struct pinctrl_ops rk3399_pinctrl_ops = {
407 .set_state_simple = rk3399_pinctrl_set_state_simple,
408 .request = rk3399_pinctrl_request,
409 .get_periph_id = rk3399_pinctrl_get_periph_id,
412 static int rk3399_pinctrl_probe(struct udevice *dev)
414 struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
417 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
418 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
419 debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
424 static const struct udevice_id rk3399_pinctrl_ids[] = {
425 { .compatible = "rockchip,rk3399-pinctrl" },
429 U_BOOT_DRIVER(pinctrl_rk3399) = {
430 .name = "rockchip_rk3399_pinctrl",
431 .id = UCLASS_PINCTRL,
432 .of_match = rk3399_pinctrl_ids,
433 .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
434 .ops = &rk3399_pinctrl_ops,
435 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
436 .bind = dm_scan_fdt_dev,
438 .probe = rk3399_pinctrl_probe,