drivers/pinctrl/rockchip/pinctrl_rk3399.c

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/grf_rk3399.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/periph.h>
  15 #include <asm/arch/clock.h>
  16 #include <dm/pinctrl.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 struct rk3399_pinctrl_priv {
  21         struct rk3399_grf_regs *grf;
  22         struct rk3399_pmugrf_regs *pmugrf;
  23 };
  24
  25 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
  26                 struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
  27 {
  28         switch (pwm_id) {
  29         case PERIPH_ID_PWM0:
  30                 rk_clrsetreg(&grf->gpio4c_iomux,
  31                              GRF_GPIO4C2_SEL_MASK,
  32                              GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
  33                 break;
  34         case PERIPH_ID_PWM1:
  35                 rk_clrsetreg(&grf->gpio4c_iomux,
  36                              GRF_GPIO4C6_SEL_MASK,
  37                              GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
  38                 break;
  39         case PERIPH_ID_PWM2:
  40                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
  41                              PMUGRF_GPIO1C3_SEL_MASK,
  42                              PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
  43                 break;
  44         case PERIPH_ID_PWM3:
  45                 if (readl(&pmugrf->soc_con0) & (1 << 5))
  46                         rk_clrsetreg(&pmugrf->gpio1b_iomux,
  47                                      PMUGRF_GPIO1B6_SEL_MASK,
  48                                      PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
  49                 else
  50                         rk_clrsetreg(&pmugrf->gpio0a_iomux,
  51                                      PMUGRF_GPIO0A6_SEL_MASK,
  52                                      PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
  53                 break;
  54         default:
  55                 debug("pwm id = %d iomux error!\n", pwm_id);
  56                 break;
  57         }
  58 }
  59
  60 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
  61                                       struct rk3399_pmugrf_regs *pmugrf,
  62                                       int i2c_id)
  63 {
  64         switch (i2c_id) {
  65         case PERIPH_ID_I2C0:
  66                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
  67                              PMUGRF_GPIO1B7_SEL_MASK,
  68                              PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
  69                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
  70                              PMUGRF_GPIO1C0_SEL_MASK,
  71                              PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
  72                 break;
  73         case PERIPH_ID_I2C1:
  74         case PERIPH_ID_I2C2:
  75         case PERIPH_ID_I2C3:
  76         case PERIPH_ID_I2C4:
  77         case PERIPH_ID_I2C5:
  78         default:
  79                 debug("i2c id = %d iomux error!\n", i2c_id);
  80                 break;
  81         }
  82 }
  83
  84 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
  85 {
  86         switch (lcd_id) {
  87         case PERIPH_ID_LCDC0:
  88                 break;
  89         default:
  90                 debug("lcdc id = %d iomux error!\n", lcd_id);
  91                 break;
  92         }
  93 }
  94
  95 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
  96                                      struct rk3399_pmugrf_regs *pmugrf,
  97                                      enum periph_id spi_id, int cs)
  98 {
  99         switch (spi_id) {
 100         case PERIPH_ID_SPI0:
 101                 switch (cs) {
 102                 case 0:
 103                         rk_clrsetreg(&grf->gpio3a_iomux,
 104                                      GRF_GPIO3A7_SEL_MASK,
 105                                      GRF_SPI0NORCODEC_CSN0
 106                                      << GRF_GPIO3A7_SEL_SHIFT);
 107                         break;
 108                 case 1:
 109                         rk_clrsetreg(&grf->gpio3b_iomux,
 110                                      GRF_GPIO3B0_SEL_MASK,
 111                                      GRF_SPI0NORCODEC_CSN1
 112                                      << GRF_GPIO3B0_SEL_SHIFT);
 113                         break;
 114                 default:
 115                         goto err;
 116                 }
 117                 rk_clrsetreg(&grf->gpio3a_iomux,
 118                              GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
 119                              | GRF_GPIO3A6_SEL_SHIFT,
 120                              GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
 121                              | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
 122                              | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
 123                 break;
 124         case PERIPH_ID_SPI1:
 125                 if (cs != 0)
 126                         goto err;
 127                 rk_clrsetreg(&pmugrf->gpio1a_iomux,
 128                              PMUGRF_GPIO1A7_SEL_MASK,
 129                              PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
 130                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 131                              PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
 132                              | PMUGRF_GPIO1B2_SEL_MASK,
 133                              PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
 134                              | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
 135                              | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
 136                 break;
 137         case PERIPH_ID_SPI2:
 138                 if (cs != 0)
 139                         goto err;
 140                 rk_clrsetreg(&grf->gpio2b_iomux,
 141                              GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
 142                              | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
 143                              GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
 144                              | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
 145                              | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
 146                              | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
 147                 break;
 148         default:
 149                 goto err;
 150         }
 151
 152         return 0;
 153 err:
 154         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 155         return -ENOENT;
 156 }
 157
 158 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
 159                                        struct rk3399_pmugrf_regs *pmugrf,
 160                                        int uart_id)
 161 {
 162         switch (uart_id) {
 163         case PERIPH_ID_UART2:
 164                 /* Using channel-C by default */
 165                 rk_clrsetreg(&grf->gpio4c_iomux,
 166                              GRF_GPIO4C3_SEL_MASK,
 167                              GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
 168                 rk_clrsetreg(&grf->gpio4c_iomux,
 169                              GRF_GPIO4C4_SEL_MASK,
 170                              GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
 171                 break;
 172         case PERIPH_ID_UART0:
 173         case PERIPH_ID_UART1:
 174         case PERIPH_ID_UART3:
 175         case PERIPH_ID_UART4:
 176         default:
 177                 debug("uart id = %d iomux error!\n", uart_id);
 178                 break;
 179         }
 180 }
 181
 182 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
 183 {
 184         switch (mmc_id) {
 185         case PERIPH_ID_EMMC:
 186                 break;
 187         case PERIPH_ID_SDCARD:
 188                 rk_clrsetreg(&grf->gpio4b_iomux,
 189                              GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
 190                              | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
 191                              | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
 192                              GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
 193                              | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
 194                              | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
 195                              | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
 196                              | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
 197                              | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
 198                 break;
 199         default:
 200                 debug("mmc id = %d iomux error!\n", mmc_id);
 201                 break;
 202         }
 203 }
 204
 205 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 206 static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
 207 {
 208         rk_clrsetreg(&grf->gpio3a_iomux,
 209                      GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
 210                      GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
 211                      GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
 212                      GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
 213                      GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
 214                      GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
 215                      GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
 216                      GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
 217                      GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
 218                      GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
 219                      GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
 220                      GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
 221         rk_clrsetreg(&grf->gpio3b_iomux,
 222                      GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
 223                                             GRF_GPIO3B3_SEL_MASK |
 224                      GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
 225                      GRF_GPIO3B6_SEL_MASK,
 226                      GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
 227                      GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
 228                      GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
 229                      GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
 230                      GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
 231                      GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
 232         rk_clrsetreg(&grf->gpio3c_iomux,
 233                      GRF_GPIO3C1_SEL_MASK,
 234                      GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
 235 }
 236 #endif
 237
 238 static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
 239 {
 240         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 241
 242         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 243         switch (func) {
 244         case PERIPH_ID_PWM0:
 245         case PERIPH_ID_PWM1:
 246         case PERIPH_ID_PWM2:
 247         case PERIPH_ID_PWM3:
 248         case PERIPH_ID_PWM4:
 249                 pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
 250                 break;
 251         case PERIPH_ID_I2C0:
 252         case PERIPH_ID_I2C1:
 253         case PERIPH_ID_I2C2:
 254         case PERIPH_ID_I2C3:
 255         case PERIPH_ID_I2C4:
 256         case PERIPH_ID_I2C5:
 257                 pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
 258                 break;
 259         case PERIPH_ID_SPI0:
 260         case PERIPH_ID_SPI1:
 261         case PERIPH_ID_SPI2:
 262                 pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
 263                 break;
 264         case PERIPH_ID_UART0:
 265         case PERIPH_ID_UART1:
 266         case PERIPH_ID_UART2:
 267         case PERIPH_ID_UART3:
 268         case PERIPH_ID_UART4:
 269                 pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
 270                 break;
 271         case PERIPH_ID_LCDC0:
 272         case PERIPH_ID_LCDC1:
 273                 pinctrl_rk3399_lcdc_config(priv->grf, func);
 274                 break;
 275         case PERIPH_ID_SDMMC0:
 276         case PERIPH_ID_SDMMC1:
 277                 pinctrl_rk3399_sdmmc_config(priv->grf, func);
 278                 break;
 279 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 280         case PERIPH_ID_GMAC:
 281                 pinctrl_rk3399_gmac_config(priv->grf, func);
 282                 break;
 283 #endif
 284         default:
 285                 return -EINVAL;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
 292                                         struct udevice *periph)
 293 {
 294 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 295         u32 cell[3];
 296         int ret;
 297
 298         ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
 299                                    "interrupts", cell, ARRAY_SIZE(cell));
 300         if (ret < 0)
 301                 return -EINVAL;
 302
 303         switch (cell[1]) {
 304         case 68:
 305                 return PERIPH_ID_SPI0;
 306         case 53:
 307                 return PERIPH_ID_SPI1;
 308         case 52:
 309                 return PERIPH_ID_SPI2;
 310         case 57:
 311                 return PERIPH_ID_I2C0;
 312         case 59: /* Note strange order */
 313                 return PERIPH_ID_I2C1;
 314         case 35:
 315                 return PERIPH_ID_I2C2;
 316         case 34:
 317                 return PERIPH_ID_I2C3;
 318         case 56:
 319                 return PERIPH_ID_I2C4;
 320         case 38:
 321                 return PERIPH_ID_I2C5;
 322         case 65:
 323                 return PERIPH_ID_SDMMC1;
 324 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 325         case 12:
 326                 return PERIPH_ID_GMAC;
 327 #endif
 328         }
 329 #endif
 330         return -ENOENT;
 331 }
 332
 333 static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
 334                                            struct udevice *periph)
 335 {
 336         int func;
 337
 338         func = rk3399_pinctrl_get_periph_id(dev, periph);
 339         if (func < 0)
 340                 return func;
 341
 342         return rk3399_pinctrl_request(dev, func, 0);
 343 }
 344
 345 static struct pinctrl_ops rk3399_pinctrl_ops = {
 346         .set_state_simple       = rk3399_pinctrl_set_state_simple,
 347         .request        = rk3399_pinctrl_request,
 348         .get_periph_id  = rk3399_pinctrl_get_periph_id,
 349 };
 350
 351 static int rk3399_pinctrl_probe(struct udevice *dev)
 352 {
 353         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 354         int ret = 0;
 355
 356         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 357         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 358         debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
 359
 360         return ret;
 361 }
 362
 363 static const struct udevice_id rk3399_pinctrl_ids[] = {
 364         { .compatible = "rockchip,rk3399-pinctrl" },
 365         { }
 366 };
 367
 368 U_BOOT_DRIVER(pinctrl_rk3399) = {
 369         .name           = "rockchip_rk3399_pinctrl",
 370         .id             = UCLASS_PINCTRL,
 371         .of_match       = rk3399_pinctrl_ids,
 372         .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
 373         .ops            = &rk3399_pinctrl_ops,
 374 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 375         .bind           = dm_scan_fdt_dev,
 376 #endif
 377         .probe          = rk3399_pinctrl_probe,
 378 };