drivers/pinctrl/rockchip/pinctrl_rk3288.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  * Copyright (c) 2015 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/grf_rk3288.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/periph.h>
  18 #include <asm/arch/pmu_rk3288.h>
  19 #include <dm/pinctrl.h>
  20 #include <dm/root.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct rk3288_pinctrl_priv {
  25         struct rk3288_grf *grf;
  26         struct rk3288_pmu *pmu;
  27 };
  28
  29 static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
  30 {
  31         switch (pwm_id) {
  32         case PERIPH_ID_PWM0:
  33                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT,
  34                              GPIO7A0_PWM_0 << GPIO7A0_SHIFT);
  35                 break;
  36         case PERIPH_ID_PWM1:
  37                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT,
  38                              GPIO7A1_PWM_1 << GPIO7A1_SHIFT);
  39                 break;
  40         case PERIPH_ID_PWM2:
  41                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT,
  42                              GPIO7C6_PWM_2 << GPIO7C6_SHIFT);
  43                 break;
  44         case PERIPH_ID_PWM3:
  45                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT,
  46                              GPIO7C7_PWM_3 << GPIO7C7_SHIFT);
  47                 break;
  48         default:
  49                 debug("pwm id = %d iomux error!\n", pwm_id);
  50                 break;
  51         }
  52 }
  53
  54 static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
  55                                       struct rk3288_pmu *pmu, int i2c_id)
  56 {
  57         switch (i2c_id) {
  58         case PERIPH_ID_I2C0:
  59                 clrsetbits_le32(&pmu->gpio0b_iomux,
  60                                 GPIO0_B7_MASK << GPIO0_B7_SHIFT,
  61                                 GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
  62                 clrsetbits_le32(&pmu->gpio0b_iomux,
  63                                 GPIO0_C0_MASK << GPIO0_C0_SHIFT,
  64                                 GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
  65                 break;
  66         case PERIPH_ID_I2C1:
  67                 rk_clrsetreg(&grf->gpio8a_iomux,
  68                              GPIO8A4_MASK << GPIO8A4_SHIFT |
  69                              GPIO8A5_MASK << GPIO8A5_SHIFT,
  70                              GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT |
  71                              GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT);
  72                 break;
  73         case PERIPH_ID_I2C2:
  74                 rk_clrsetreg(&grf->gpio6b_iomux,
  75                              GPIO6B1_MASK << GPIO6B1_SHIFT |
  76                              GPIO6B2_MASK << GPIO6B2_SHIFT,
  77                              GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT |
  78                              GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT);
  79                 break;
  80         case PERIPH_ID_I2C3:
  81                 rk_clrsetreg(&grf->gpio2c_iomux,
  82                              GPIO2C1_MASK << GPIO2C1_SHIFT |
  83                              GPIO2C0_MASK << GPIO2C0_SHIFT,
  84                              GPIO2C1_I2C3CAM_SDA << GPIO2C1_SHIFT |
  85                              GPIO2C0_I2C3CAM_SCL << GPIO2C0_SHIFT);
  86                 break;
  87         case PERIPH_ID_I2C4:
  88                 rk_clrsetreg(&grf->gpio7cl_iomux,
  89                              GPIO7C1_MASK << GPIO7C1_SHIFT |
  90                              GPIO7C2_MASK << GPIO7C2_SHIFT,
  91                              GPIO7C1_I2C4TP_SDA << GPIO7C1_SHIFT |
  92                              GPIO7C2_I2C4TP_SCL << GPIO7C2_SHIFT);
  93                 break;
  94         case PERIPH_ID_I2C5:
  95                 rk_clrsetreg(&grf->gpio7cl_iomux,
  96                              GPIO7C3_MASK << GPIO7C3_SHIFT,
  97                              GPIO7C3_I2C5HDMI_SDA << GPIO7C3_SHIFT);
  98                 rk_clrsetreg(&grf->gpio7ch_iomux,
  99                              GPIO7C4_MASK << GPIO7C4_SHIFT,
 100                              GPIO7C4_I2C5HDMI_SCL << GPIO7C4_SHIFT);
 101                 break;
 102         default:
 103                 debug("i2c id = %d iomux error!\n", i2c_id);
 104                 break;
 105         }
 106 }
 107
 108 static void pinctrl_rk3288_lcdc_config(struct rk3288_grf *grf, int lcd_id)
 109 {
 110         switch (lcd_id) {
 111         case PERIPH_ID_LCDC0:
 112                 rk_clrsetreg(&grf->gpio1d_iomux,
 113                              GPIO1D3_MASK << GPIO1D0_SHIFT |
 114                              GPIO1D2_MASK << GPIO1D2_SHIFT |
 115                              GPIO1D1_MASK << GPIO1D1_SHIFT |
 116                              GPIO1D0_MASK << GPIO1D0_SHIFT,
 117                              GPIO1D3_LCDC0_DCLK << GPIO1D3_SHIFT |
 118                              GPIO1D2_LCDC0_DEN << GPIO1D2_SHIFT |
 119                              GPIO1D1_LCDC0_VSYNC << GPIO1D1_SHIFT |
 120                              GPIO1D0_LCDC0_HSYNC << GPIO1D0_SHIFT);
 121                 break;
 122         default:
 123                 debug("lcdc id = %d iomux error!\n", lcd_id);
 124                 break;
 125         }
 126 }
 127
 128 static int pinctrl_rk3288_spi_config(struct rk3288_grf *grf,
 129                                      enum periph_id spi_id, int cs)
 130 {
 131         switch (spi_id) {
 132         case PERIPH_ID_SPI0:
 133                 switch (cs) {
 134                 case 0:
 135                         rk_clrsetreg(&grf->gpio5b_iomux,
 136                                      GPIO5B5_MASK << GPIO5B5_SHIFT,
 137                                      GPIO5B5_SPI0_CSN0 << GPIO5B5_SHIFT);
 138                         break;
 139                 case 1:
 140                         rk_clrsetreg(&grf->gpio5c_iomux,
 141                                      GPIO5C0_MASK << GPIO5C0_SHIFT,
 142                                      GPIO5C0_SPI0_CSN1 << GPIO5C0_SHIFT);
 143                         break;
 144                 default:
 145                         goto err;
 146                 }
 147                 rk_clrsetreg(&grf->gpio5b_iomux,
 148                              GPIO5B7_MASK << GPIO5B7_SHIFT |
 149                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 150                              GPIO5B4_MASK << GPIO5B4_SHIFT,
 151                              GPIO5B7_SPI0_RXD << GPIO5B7_SHIFT |
 152                              GPIO5B6_SPI0_TXD << GPIO5B6_SHIFT |
 153                              GPIO5B4_SPI0_CLK << GPIO5B4_SHIFT);
 154                 break;
 155         case PERIPH_ID_SPI1:
 156                 if (cs != 0)
 157                         goto err;
 158                 rk_clrsetreg(&grf->gpio7b_iomux,
 159                              GPIO7B6_MASK << GPIO7B6_SHIFT |
 160                              GPIO7B7_MASK << GPIO7B7_SHIFT |
 161                              GPIO7B5_MASK << GPIO7B5_SHIFT |
 162                              GPIO7B4_MASK << GPIO7B4_SHIFT,
 163                              GPIO7B6_SPI1_RXD << GPIO7B6_SHIFT |
 164                              GPIO7B7_SPI1_TXD << GPIO7B7_SHIFT |
 165                              GPIO7B5_SPI1_CSN0 << GPIO7B5_SHIFT |
 166                              GPIO7B4_SPI1_CLK << GPIO7B4_SHIFT);
 167                 break;
 168         case PERIPH_ID_SPI2:
 169                 switch (cs) {
 170                 case 0:
 171                         rk_clrsetreg(&grf->gpio8a_iomux,
 172                                      GPIO8A7_MASK << GPIO8A7_SHIFT,
 173                                      GPIO8A7_SPI2_CSN0 << GPIO8A7_SHIFT);
 174                         break;
 175                 case 1:
 176                         rk_clrsetreg(&grf->gpio8a_iomux,
 177                                      GPIO8A3_MASK << GPIO8A3_SHIFT,
 178                                      GPIO8A3_SPI2_CSN1 << GPIO8A3_SHIFT);
 179                         break;
 180                 default:
 181                         goto err;
 182                 }
 183                 rk_clrsetreg(&grf->gpio8b_iomux,
 184                              GPIO8B1_MASK << GPIO8B1_SHIFT |
 185                              GPIO8B0_MASK << GPIO8B0_SHIFT,
 186                              GPIO8B1_SPI2_TXD << GPIO8B1_SHIFT |
 187                              GPIO8B0_SPI2_RXD << GPIO8B0_SHIFT);
 188                 rk_clrsetreg(&grf->gpio8a_iomux,
 189                              GPIO8A6_MASK << GPIO8A6_SHIFT,
 190                              GPIO8A6_SPI2_CLK << GPIO8A6_SHIFT);
 191                 break;
 192         default:
 193                 goto err;
 194         }
 195
 196         return 0;
 197 err:
 198         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 199         return -ENOENT;
 200 }
 201
 202 static void pinctrl_rk3288_uart_config(struct rk3288_grf *grf, int uart_id)
 203 {
 204         switch (uart_id) {
 205         case PERIPH_ID_UART_BT:
 206                 rk_clrsetreg(&grf->gpio4c_iomux,
 207                              GPIO4C3_MASK << GPIO4C3_SHIFT |
 208                              GPIO4C2_MASK << GPIO4C2_SHIFT |
 209                              GPIO4C1_MASK << GPIO4C1_SHIFT |
 210                              GPIO4C0_MASK << GPIO4C0_SHIFT,
 211                              GPIO4C3_UART0BT_RTSN << GPIO4C3_SHIFT |
 212                              GPIO4C2_UART0BT_CTSN << GPIO4C2_SHIFT |
 213                              GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
 214                              GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
 215                 break;
 216         case PERIPH_ID_UART_BB:
 217                 rk_clrsetreg(&grf->gpio5b_iomux,
 218                              GPIO5B3_MASK << GPIO5B3_SHIFT |
 219                              GPIO5B2_MASK << GPIO5B2_SHIFT |
 220                              GPIO5B1_MASK << GPIO5B1_SHIFT |
 221                              GPIO5B0_MASK << GPIO5B0_SHIFT,
 222                              GPIO5B3_UART1BB_RTSN << GPIO5B3_SHIFT |
 223                              GPIO5B2_UART1BB_CTSN << GPIO5B2_SHIFT |
 224                              GPIO5B1_UART1BB_SOUT << GPIO5B1_SHIFT |
 225                              GPIO5B0_UART1BB_SIN << GPIO5B0_SHIFT);
 226                 break;
 227         case PERIPH_ID_UART_DBG:
 228                 rk_clrsetreg(&grf->gpio7ch_iomux,
 229                              GPIO7C7_MASK << GPIO7C7_SHIFT |
 230                              GPIO7C6_MASK << GPIO7C6_SHIFT,
 231                              GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
 232                              GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 233                 break;
 234         case PERIPH_ID_UART_GPS:
 235                 rk_clrsetreg(&grf->gpio7b_iomux,
 236                              GPIO7B2_MASK << GPIO7B2_SHIFT |
 237                              GPIO7B1_MASK << GPIO7B1_SHIFT |
 238                              GPIO7B0_MASK << GPIO7B0_SHIFT,
 239                              GPIO7B2_UART3GPS_RTSN << GPIO7B2_SHIFT |
 240                              GPIO7B1_UART3GPS_CTSN << GPIO7B1_SHIFT |
 241                              GPIO7B0_UART3GPS_SOUT << GPIO7B0_SHIFT);
 242                 rk_clrsetreg(&grf->gpio7a_iomux,
 243                              GPIO7A7_MASK << GPIO7A7_SHIFT,
 244                              GPIO7A7_UART3GPS_SIN << GPIO7A7_SHIFT);
 245                 break;
 246         case PERIPH_ID_UART_EXP:
 247                 rk_clrsetreg(&grf->gpio5b_iomux,
 248                              GPIO5B5_MASK << GPIO5B5_SHIFT |
 249                              GPIO5B4_MASK << GPIO5B4_SHIFT |
 250                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 251                              GPIO5B7_MASK << GPIO5B7_SHIFT,
 252                              GPIO5B5_UART4EXP_RTSN << GPIO5B5_SHIFT |
 253                              GPIO5B4_UART4EXP_CTSN << GPIO5B4_SHIFT |
 254                              GPIO5B6_UART4EXP_SOUT << GPIO5B6_SHIFT |
 255                              GPIO5B7_UART4EXP_SIN << GPIO5B7_SHIFT);
 256                 break;
 257         default:
 258                 debug("uart id = %d iomux error!\n", uart_id);
 259                 break;
 260         }
 261 }
 262
 263 static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
 264 {
 265         switch (mmc_id) {
 266         case PERIPH_ID_EMMC:
 267                 rk_clrsetreg(&grf->gpio3a_iomux, 0xffff,
 268                              GPIO3A7_EMMC_DATA7 << GPIO3A7_SHIFT |
 269                              GPIO3A6_EMMC_DATA6 << GPIO3A6_SHIFT |
 270                              GPIO3A5_EMMC_DATA5 << GPIO3A5_SHIFT |
 271                              GPIO3A4_EMMC_DATA4 << GPIO3A4_SHIFT |
 272                              GPIO3A3_EMMC_DATA3 << GPIO3A3_SHIFT |
 273                              GPIO3A2_EMMC_DATA2 << GPIO3A2_SHIFT |
 274                              GPIO3A1_EMMC_DATA1 << GPIO3A1_SHIFT |
 275                              GPIO3A0_EMMC_DATA0 << GPIO3A0_SHIFT);
 276                 rk_clrsetreg(&grf->gpio3b_iomux, GPIO3B1_MASK << GPIO3B1_SHIFT,
 277                              GPIO3B1_EMMC_PWREN << GPIO3B1_SHIFT);
 278                 rk_clrsetreg(&grf->gpio3c_iomux,
 279                              GPIO3C0_MASK << GPIO3C0_SHIFT,
 280                              GPIO3C0_EMMC_CMD << GPIO3C0_SHIFT);
 281                 break;
 282         case PERIPH_ID_SDCARD:
 283                 rk_clrsetreg(&grf->gpio6c_iomux, 0xffff,
 284                              GPIO6C6_SDMMC0_DECTN << GPIO6C6_SHIFT |
 285                              GPIO6C5_SDMMC0_CMD << GPIO6C5_SHIFT |
 286                              GPIO6C4_SDMMC0_CLKOUT << GPIO6C4_SHIFT |
 287                              GPIO6C3_SDMMC0_DATA3 << GPIO6C3_SHIFT |
 288                              GPIO6C2_SDMMC0_DATA2 << GPIO6C2_SHIFT |
 289                              GPIO6C1_SDMMC0_DATA1 << GPIO6C1_SHIFT |
 290                              GPIO6C0_SDMMC0_DATA0 << GPIO6C0_SHIFT);
 291
 292                 /* use sdmmc0 io, disable JTAG function */
 293                 rk_clrsetreg(&grf->soc_con0, 1 << GRF_FORCE_JTAG_SHIFT, 0);
 294                 break;
 295         default:
 296                 debug("mmc id = %d iomux error!\n", mmc_id);
 297                 break;
 298         }
 299 }
 300
 301 static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
 302 {
 303         switch (hdmi_id) {
 304         case PERIPH_ID_HDMI:
 305                 rk_clrsetreg(&grf->gpio7cl_iomux, GPIO7C3_MASK << GPIO7C3_SHIFT,
 306                              GPIO7C3_EDPHDMII2C_SDA << GPIO7C3_SHIFT);
 307                 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C4_MASK << GPIO7C4_SHIFT,
 308                              GPIO7C4_EDPHDMII2C_SCL << GPIO7C4_SHIFT);
 309                 break;
 310         default:
 311                 debug("hdmi id = %d iomux error!\n", hdmi_id);
 312                 break;
 313         }
 314 }
 315
 316 static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
 317 {
 318         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 319
 320         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 321         switch (func) {
 322         case PERIPH_ID_PWM0:
 323         case PERIPH_ID_PWM1:
 324         case PERIPH_ID_PWM2:
 325         case PERIPH_ID_PWM3:
 326         case PERIPH_ID_PWM4:
 327                 pinctrl_rk3288_pwm_config(priv->grf, func);
 328                 break;
 329         case PERIPH_ID_I2C0:
 330         case PERIPH_ID_I2C1:
 331         case PERIPH_ID_I2C2:
 332         case PERIPH_ID_I2C3:
 333         case PERIPH_ID_I2C4:
 334         case PERIPH_ID_I2C5:
 335                 pinctrl_rk3288_i2c_config(priv->grf, priv->pmu, func);
 336                 break;
 337         case PERIPH_ID_SPI0:
 338         case PERIPH_ID_SPI1:
 339         case PERIPH_ID_SPI2:
 340                 pinctrl_rk3288_spi_config(priv->grf, func, flags);
 341                 break;
 342         case PERIPH_ID_UART0:
 343         case PERIPH_ID_UART1:
 344         case PERIPH_ID_UART2:
 345         case PERIPH_ID_UART3:
 346         case PERIPH_ID_UART4:
 347                 pinctrl_rk3288_uart_config(priv->grf, func);
 348                 break;
 349         case PERIPH_ID_LCDC0:
 350         case PERIPH_ID_LCDC1:
 351                 pinctrl_rk3288_lcdc_config(priv->grf, func);
 352                 break;
 353         case PERIPH_ID_SDMMC0:
 354         case PERIPH_ID_SDMMC1:
 355                 pinctrl_rk3288_sdmmc_config(priv->grf, func);
 356                 break;
 357         case PERIPH_ID_HDMI:
 358                 pinctrl_rk3288_hdmi_config(priv->grf, func);
 359                 break;
 360         default:
 361                 return -EINVAL;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
 368                                         struct udevice *periph)
 369 {
 370         u32 cell[3];
 371         int ret;
 372
 373         ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
 374                                    "interrupts", cell, ARRAY_SIZE(cell));
 375         if (ret < 0)
 376                 return -EINVAL;
 377
 378         switch (cell[1]) {
 379         case 44:
 380                 return PERIPH_ID_SPI0;
 381         case 45:
 382                 return PERIPH_ID_SPI1;
 383         case 46:
 384                 return PERIPH_ID_SPI2;
 385         case 60:
 386                 return PERIPH_ID_I2C0;
 387         case 62: /* Note strange order */
 388                 return PERIPH_ID_I2C1;
 389         case 61:
 390                 return PERIPH_ID_I2C2;
 391         case 63:
 392                 return PERIPH_ID_I2C3;
 393         case 64:
 394                 return PERIPH_ID_I2C4;
 395         case 65:
 396                 return PERIPH_ID_I2C5;
 397         }
 398
 399         return -ENOENT;
 400 }
 401
 402 static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
 403                                            struct udevice *periph)
 404 {
 405         int func;
 406
 407         func = rk3288_pinctrl_get_periph_id(dev, periph);
 408         if (func < 0)
 409                 return func;
 410         return rk3288_pinctrl_request(dev, func, 0);
 411 }
 412
 413 static struct pinctrl_ops rk3288_pinctrl_ops = {
 414         .set_state_simple       = rk3288_pinctrl_set_state_simple,
 415         .request        = rk3288_pinctrl_request,
 416         .get_periph_id  = rk3288_pinctrl_get_periph_id,
 417 };
 418
 419 static int rk3288_pinctrl_bind(struct udevice *dev)
 420 {
 421         /* scan child GPIO banks */
 422         return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
 423 }
 424
 425 static int rk3288_pinctrl_probe(struct udevice *dev)
 426 {
 427         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 428
 429         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 430         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 431         debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
 432
 433         return 0;
 434 }
 435
 436 static const struct udevice_id rk3288_pinctrl_ids[] = {
 437         { .compatible = "rockchip,rk3288-pinctrl" },
 438         { }
 439 };
 440
 441 U_BOOT_DRIVER(pinctrl_rk3288) = {
 442         .name           = "pinctrl_rk3288",
 443         .id             = UCLASS_PINCTRL,
 444         .of_match       = rk3288_pinctrl_ids,
 445         .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
 446         .ops            = &rk3288_pinctrl_ops,
 447         .bind           = rk3288_pinctrl_bind,
 448         .probe          = rk3288_pinctrl_probe,
 449 };