2 * Pinctrl driver for Rockchip RK3188 SoCs
3 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/grf_rk3188.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/periph.h>
17 #include <asm/arch/pmu_rk3188.h>
18 #include <dm/pinctrl.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 /* GRF_GPIO0D_IOMUX */
49 GPIO0D3_EMMC_RSTN_OUT,
69 /* GRF_GPIO1A_IOMUX */
116 /* GRF_GPIO1B_IOMUX */
166 /* GRF_GPIO1D_IOMUX */
209 /* GRF_GPIO3A_IOMUX */
214 GPIO3A7_SDMMC0_DATA3,
219 GPIO3A6_SDMMC0_DATA2,
224 GPIO3A5_SDMMC0_DATA1,
229 GPIO3A4_SDMMC0_DATA0,
239 GPIO3A2_SDMMC0_CLKOUT,
244 GPIO3A1_SDMMC0_PWREN,
252 /* GRF_GPIO3B_IOMUX */
291 GPIO3B1_SDMMC0_WRITE_PRT,
296 GPIO3B0_SDMMC_DETECT_N,
299 /* GRF_GPIO3C_IOMUX */
304 GPIO3C7_SDMMC1_WRITE_PRT,
305 GPIO3C7_RMII_CRS_DVALID,
311 GPIO3C6_SDMMC1_DECTN,
318 GPIO3C5_SDMMC1_CLKOUT,
325 GPIO3C4_SDMMC1_DATA3,
332 GPIO3C3_SDMMC1_DATA2,
339 GPIO3C2_SDMMC1_DATA1,
346 GPIO3C1_SDMMC1_DATA0,
358 /* GRF_GPIO3D_IOMUX */
365 GPIO3D6_HOST_DRV_VBUS,
372 GPIO3D5_OTG_DRV_VBUS,
388 GPIO3D2_SDMMC1_INT_N,
393 GPIO3D1_SDMMC1_BACKEND_PWR,
399 GPIO3D0_SDMMC1_PWR_EN,
403 struct rk3188_pinctrl_priv {
404 struct rk3188_grf *grf;
405 struct rk3188_pmu *pmu;
410 * Encode variants of iomux registers into a type variable
412 #define IOMUX_GPIO_ONLY BIT(0)
415 * @type: iomux variant using IOMUX_* constants
416 * @offset: if initialized to -1 it will be autocalculated, by specifying
417 * an initial offset value the relevant source offset can be reset
418 * to a new value for autocalculating the following iomux registers.
420 struct rockchip_iomux {
426 * @reg: register offset of the gpio bank
427 * @nr_pins: number of pins in this bank
428 * @bank_num: number of the bank, to account for holes
429 * @name: name of the bank
430 * @iomux: array describing the 4 iomux sources of the bank
432 struct rockchip_pin_bank {
437 struct rockchip_iomux iomux[4];
440 #define PIN_BANK(id, pins, label) \
453 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
459 { .type = iom0, .offset = -1 }, \
460 { .type = iom1, .offset = -1 }, \
461 { .type = iom2, .offset = -1 }, \
462 { .type = iom3, .offset = -1 }, \
466 #ifndef CONFIG_SPL_BUILD
467 static struct rockchip_pin_bank rk3188_pin_banks[] = {
468 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
469 PIN_BANK(1, 32, "gpio1"),
470 PIN_BANK(2, 32, "gpio2"),
471 PIN_BANK(3, 32, "gpio3"),
475 static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id)
479 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT,
480 GPIO3D3_PWM_0 << GPIO3D3_SHIFT);
483 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT,
484 GPIO3D4_PWM_1 << GPIO3D4_SHIFT);
487 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT,
488 GPIO3D5_PWM_2 << GPIO3D5_SHIFT);
491 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT,
492 GPIO3D6_PWM_3 << GPIO3D6_SHIFT);
495 debug("pwm id = %d iomux error!\n", pwm_id);
500 static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf,
501 struct rk3188_pmu *pmu, int i2c_id)
505 rk_clrsetreg(&grf->gpio1d_iomux,
506 GPIO1D1_MASK << GPIO1D1_SHIFT |
507 GPIO1D0_MASK << GPIO1D0_SHIFT,
508 GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT |
509 GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT);
510 /* enable new i2c controller */
511 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT,
512 1 << RKI2C0_SEL_SHIFT);
515 rk_clrsetreg(&grf->gpio1d_iomux,
516 GPIO1D3_MASK << GPIO1D3_SHIFT |
517 GPIO1D2_MASK << GPIO1D2_SHIFT,
518 GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT |
519 GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT);
520 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT,
521 1 << RKI2C1_SEL_SHIFT);
524 rk_clrsetreg(&grf->gpio1d_iomux,
525 GPIO1D5_MASK << GPIO1D5_SHIFT |
526 GPIO1D4_MASK << GPIO1D4_SHIFT,
527 GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT |
528 GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT);
529 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT,
530 1 << RKI2C2_SEL_SHIFT);
533 rk_clrsetreg(&grf->gpio3b_iomux,
534 GPIO3B7_MASK << GPIO3B7_SHIFT |
535 GPIO3B6_MASK << GPIO3B6_SHIFT,
536 GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT |
537 GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT);
538 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT,
539 1 << RKI2C3_SEL_SHIFT);
542 rk_clrsetreg(&grf->gpio1d_iomux,
543 GPIO1D7_MASK << GPIO1D7_SHIFT |
544 GPIO1D6_MASK << GPIO1D6_SHIFT,
545 GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT |
546 GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT);
547 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT,
548 1 << RKI2C4_SEL_SHIFT);
551 debug("i2c id = %d iomux error!\n", i2c_id);
556 static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf,
557 enum periph_id spi_id, int cs)
563 rk_clrsetreg(&grf->gpio1a_iomux,
564 GPIO1A7_MASK << GPIO1A7_SHIFT,
565 GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT);
568 rk_clrsetreg(&grf->gpio1b_iomux,
569 GPIO1B7_MASK << GPIO1B7_SHIFT,
570 GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT);
575 rk_clrsetreg(&grf->gpio1a_iomux,
576 GPIO1A4_MASK << GPIO1A4_SHIFT |
577 GPIO1A5_MASK << GPIO1A5_SHIFT |
578 GPIO1A6_MASK << GPIO1A6_SHIFT,
579 GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT |
580 GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT |
581 GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT);
586 rk_clrsetreg(&grf->gpio0d_iomux,
587 GPIO0D7_MASK << GPIO0D7_SHIFT,
588 GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT);
591 rk_clrsetreg(&grf->gpio1b_iomux,
592 GPIO1B6_MASK << GPIO1B6_SHIFT,
593 GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT);
598 rk_clrsetreg(&grf->gpio0d_iomux,
599 GPIO0D4_MASK << GPIO0D4_SHIFT |
600 GPIO0D5_MASK << GPIO0D5_SHIFT |
601 GPIO0D6_MASK << GPIO0D6_SHIFT,
602 GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT |
603 GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT |
604 GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT);
612 debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
616 static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id)
619 case PERIPH_ID_UART0:
620 rk_clrsetreg(&grf->gpio1a_iomux,
621 GPIO1A3_MASK << GPIO1A3_SHIFT |
622 GPIO1A2_MASK << GPIO1A2_SHIFT |
623 GPIO1A1_MASK << GPIO1A1_SHIFT |
624 GPIO1A0_MASK << GPIO1A0_SHIFT,
625 GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT |
626 GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT |
627 GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT |
628 GPIO1A0_UART0_SIN << GPIO1A0_SHIFT);
630 case PERIPH_ID_UART1:
631 rk_clrsetreg(&grf->gpio1a_iomux,
632 GPIO1A7_MASK << GPIO1A7_SHIFT |
633 GPIO1A6_MASK << GPIO1A6_SHIFT |
634 GPIO1A5_MASK << GPIO1A5_SHIFT |
635 GPIO1A4_MASK << GPIO1A4_SHIFT,
636 GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT |
637 GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT |
638 GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT |
639 GPIO1A4_UART1_SIN << GPIO1A4_SHIFT);
641 case PERIPH_ID_UART2:
642 rk_clrsetreg(&grf->gpio1b_iomux,
643 GPIO1B1_MASK << GPIO1B1_SHIFT |
644 GPIO1B0_MASK << GPIO1B0_SHIFT,
645 GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
646 GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
648 case PERIPH_ID_UART3:
649 rk_clrsetreg(&grf->gpio1b_iomux,
650 GPIO1B5_MASK << GPIO1B5_SHIFT |
651 GPIO1B4_MASK << GPIO1B4_SHIFT |
652 GPIO1B3_MASK << GPIO1B3_SHIFT |
653 GPIO1B2_MASK << GPIO1B2_SHIFT,
654 GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT |
655 GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT |
656 GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT |
657 GPIO1B2_UART3_SIN << GPIO1B2_SHIFT);
660 debug("uart id = %d iomux error!\n", uart_id);
665 static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id)
669 rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT,
670 1 << EMMC_FLASH_SEL_SHIFT);
671 rk_clrsetreg(&grf->gpio0d_iomux,
672 GPIO0D2_MASK << GPIO0D2_SHIFT |
673 GPIO0D0_MASK << GPIO0D0_SHIFT,
674 GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT |
675 GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT);
677 case PERIPH_ID_SDCARD:
678 rk_clrsetreg(&grf->gpio3b_iomux,
679 GPIO3B0_MASK << GPIO3B0_SHIFT,
680 GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT);
681 rk_clrsetreg(&grf->gpio3a_iomux,
682 GPIO3A7_MASK << GPIO3A7_SHIFT |
683 GPIO3A6_MASK << GPIO3A6_SHIFT |
684 GPIO3A5_MASK << GPIO3A5_SHIFT |
685 GPIO3A4_MASK << GPIO3A4_SHIFT |
686 GPIO3A3_MASK << GPIO3A3_SHIFT |
687 GPIO3A3_MASK << GPIO3A2_SHIFT,
688 GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT |
689 GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT |
690 GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT |
691 GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT |
692 GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT |
693 GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT);
696 debug("mmc id = %d iomux error!\n", mmc_id);
701 static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags)
703 struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
705 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
712 pinctrl_rk3188_pwm_config(priv->grf, func);
720 pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func);
725 pinctrl_rk3188_spi_config(priv->grf, func, flags);
727 case PERIPH_ID_UART0:
728 case PERIPH_ID_UART1:
729 case PERIPH_ID_UART2:
730 case PERIPH_ID_UART3:
731 case PERIPH_ID_UART4:
732 pinctrl_rk3188_uart_config(priv->grf, func);
735 case PERIPH_ID_SDMMC0:
736 case PERIPH_ID_SDMMC1:
737 pinctrl_rk3188_sdmmc_config(priv->grf, func);
746 static int rk3188_pinctrl_get_periph_id(struct udevice *dev,
747 struct udevice *periph)
749 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
753 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
759 return PERIPH_ID_SPI0;
761 return PERIPH_ID_SPI1;
763 return PERIPH_ID_SPI2;
765 return PERIPH_ID_I2C0;
766 case 62: /* Note strange order */
767 return PERIPH_ID_I2C1;
769 return PERIPH_ID_I2C2;
771 return PERIPH_ID_I2C3;
773 return PERIPH_ID_I2C4;
775 return PERIPH_ID_I2C5;
782 static int rk3188_pinctrl_set_state_simple(struct udevice *dev,
783 struct udevice *periph)
787 func = rk3188_pinctrl_get_periph_id(dev, periph);
790 return rk3188_pinctrl_request(dev, func, 0);
793 #ifndef CONFIG_SPL_BUILD
794 int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv,
795 int banknum, int ind, u32 **addrp, uint *shiftp,
798 struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum];
802 for (muxnum = 0; muxnum < 4; muxnum++) {
803 struct rockchip_iomux *mux = &bank->iomux[muxnum];
810 addr = &priv->grf->gpio0c_iomux - 2;
816 debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
825 static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
828 struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
834 ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
838 return (readl(addr) & mask) >> shift;
841 static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
842 int muxval, int flags)
844 struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
845 uint shift, ind = index;
850 debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
851 ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
855 rk_clrsetreg(addr, mask << shift, muxval << shift);
857 /* Handle pullup/pulldown */
861 if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
863 else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
868 if (banknum == 0 && index < 12) {
869 addr = &priv->pmu->gpio0_p[ind];
870 shift = (index & 7) * 2;
871 } else if (banknum == 0 && index >= 12) {
872 addr = &priv->grf->gpio0_p[ind - 1];
874 * The bits in the grf-registers have an inverse
875 * ordering with the lowest pin being in bits 15:14
876 * and the highest pin in bits 1:0 .
878 shift = (7 - (index & 7)) * 2;
880 addr = &priv->grf->gpio1_p[banknum - 1][ind];
881 shift = (7 - (index & 7)) * 2;
883 debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
885 rk_clrsetreg(addr, 3 << shift, val << shift);
891 static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config)
893 const void *blob = gd->fdt_blob;
894 int pcfg_node, ret, flags, count, i;
897 debug("%s: %s %s\n", __func__, dev->name, config->name);
898 ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
899 "rockchip,pins", cell,
902 debug("%s: bad array %d\n", __func__, ret);
906 for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
907 pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
910 flags = pinctrl_decode_pin_config(blob, pcfg_node);
914 ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
924 static struct pinctrl_ops rk3188_pinctrl_ops = {
925 #ifndef CONFIG_SPL_BUILD
926 .set_state = rk3188_pinctrl_set_state,
927 .get_gpio_mux = rk3188_pinctrl_get_gpio_mux,
929 .set_state_simple = rk3188_pinctrl_set_state_simple,
930 .request = rk3188_pinctrl_request,
931 .get_periph_id = rk3188_pinctrl_get_periph_id,
934 #ifndef CONFIG_SPL_BUILD
935 static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv,
936 struct rockchip_pin_bank *banks,
939 struct rockchip_pin_bank *bank;
940 uint reg, muxnum, banknum;
943 for (banknum = 0; banknum < count; banknum++) {
944 bank = &banks[banknum];
946 debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
947 for (muxnum = 0; muxnum < 4; muxnum++) {
948 struct rockchip_iomux *mux = &bank->iomux[muxnum];
959 static int rk3188_pinctrl_probe(struct udevice *dev)
961 struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
964 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
965 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
966 debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
967 #ifndef CONFIG_SPL_BUILD
968 ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks,
969 ARRAY_SIZE(rk3188_pin_banks));
975 static const struct udevice_id rk3188_pinctrl_ids[] = {
976 { .compatible = "rockchip,rk3188-pinctrl" },
980 U_BOOT_DRIVER(pinctrl_rk3188) = {
981 .name = "rockchip_rk3188_pinctrl",
982 .id = UCLASS_PINCTRL,
983 .of_match = rk3188_pinctrl_ids,
984 .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv),
985 .ops = &rk3188_pinctrl_ops,
986 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
987 .bind = dm_scan_fdt_dev,
989 .probe = rk3188_pinctrl_probe,