drivers/pinctrl/rockchip/pinctrl_rk3188.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Pinctrl driver for Rockchip RK3188 SoCs
   4  * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/grf_rk3188.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/periph.h>
  16 #include <asm/arch/pmu_rk3188.h>
  17 #include <dm/pinctrl.h>
  18 #include <dm/root.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 /* GRF_GPIO0D_IOMUX */
  23 enum {
  24         GPIO0D7_SHIFT           = 14,
  25         GPIO0D7_MASK            = 1,
  26         GPIO0D7_GPIO            = 0,
  27         GPIO0D7_SPI1_CSN0,
  28
  29         GPIO0D6_SHIFT           = 12,
  30         GPIO0D6_MASK            = 1,
  31         GPIO0D6_GPIO            = 0,
  32         GPIO0D6_SPI1_CLK,
  33
  34         GPIO0D5_SHIFT           = 10,
  35         GPIO0D5_MASK            = 1,
  36         GPIO0D5_GPIO            = 0,
  37         GPIO0D5_SPI1_TXD,
  38
  39         GPIO0D4_SHIFT           = 8,
  40         GPIO0D4_MASK            = 1,
  41         GPIO0D4_GPIO            = 0,
  42         GPIO0D4_SPI0_RXD,
  43
  44         GPIO0D3_SHIFT           = 6,
  45         GPIO0D3_MASK            = 3,
  46         GPIO0D3_GPIO            = 0,
  47         GPIO0D3_FLASH_CSN3,
  48         GPIO0D3_EMMC_RSTN_OUT,
  49
  50         GPIO0D2_SHIFT           = 4,
  51         GPIO0D2_MASK            = 3,
  52         GPIO0D2_GPIO            = 0,
  53         GPIO0D2_FLASH_CSN2,
  54         GPIO0D2_EMMC_CMD,
  55
  56         GPIO0D1_SHIFT           = 2,
  57         GPIO0D1_MASK            = 1,
  58         GPIO0D1_GPIO            = 0,
  59         GPIO0D1_FLASH_CSN1,
  60
  61         GPIO0D0_SHIFT           = 0,
  62         GPIO0D0_MASK            = 3,
  63         GPIO0D0_GPIO            = 0,
  64         GPIO0D0_FLASH_DQS,
  65         GPIO0D0_EMMC_CLKOUT
  66 };
  67
  68 /* GRF_GPIO1A_IOMUX */
  69 enum {
  70         GPIO1A7_SHIFT           = 14,
  71         GPIO1A7_MASK            = 3,
  72         GPIO1A7_GPIO            = 0,
  73         GPIO1A7_UART1_RTS_N,
  74         GPIO1A7_SPI0_CSN0,
  75
  76         GPIO1A6_SHIFT           = 12,
  77         GPIO1A6_MASK            = 3,
  78         GPIO1A6_GPIO            = 0,
  79         GPIO1A6_UART1_CTS_N,
  80         GPIO1A6_SPI0_CLK,
  81
  82         GPIO1A5_SHIFT           = 10,
  83         GPIO1A5_MASK            = 3,
  84         GPIO1A5_GPIO            = 0,
  85         GPIO1A5_UART1_SOUT,
  86         GPIO1A5_SPI0_TXD,
  87
  88         GPIO1A4_SHIFT           = 8,
  89         GPIO1A4_MASK            = 3,
  90         GPIO1A4_GPIO            = 0,
  91         GPIO1A4_UART1_SIN,
  92         GPIO1A4_SPI0_RXD,
  93
  94         GPIO1A3_SHIFT           = 6,
  95         GPIO1A3_MASK            = 1,
  96         GPIO1A3_GPIO            = 0,
  97         GPIO1A3_UART0_RTS_N,
  98
  99         GPIO1A2_SHIFT           = 4,
 100         GPIO1A2_MASK            = 1,
 101         GPIO1A2_GPIO            = 0,
 102         GPIO1A2_UART0_CTS_N,
 103
 104         GPIO1A1_SHIFT           = 2,
 105         GPIO1A1_MASK            = 1,
 106         GPIO1A1_GPIO            = 0,
 107         GPIO1A1_UART0_SOUT,
 108
 109         GPIO1A0_SHIFT           = 0,
 110         GPIO1A0_MASK            = 1,
 111         GPIO1A0_GPIO            = 0,
 112         GPIO1A0_UART0_SIN,
 113 };
 114
 115 /* GRF_GPIO1B_IOMUX */
 116 enum {
 117         GPIO1B7_SHIFT           = 14,
 118         GPIO1B7_MASK            = 1,
 119         GPIO1B7_GPIO            = 0,
 120         GPIO1B7_SPI0_CSN1,
 121
 122         GPIO1B6_SHIFT           = 12,
 123         GPIO1B6_MASK            = 3,
 124         GPIO1B6_GPIO            = 0,
 125         GPIO1B6_SPDIF_TX,
 126         GPIO1B6_SPI1_CSN1,
 127
 128         GPIO1B5_SHIFT           = 10,
 129         GPIO1B5_MASK            = 3,
 130         GPIO1B5_GPIO            = 0,
 131         GPIO1B5_UART3_RTS_N,
 132         GPIO1B5_RESERVED,
 133
 134         GPIO1B4_SHIFT           = 8,
 135         GPIO1B4_MASK            = 3,
 136         GPIO1B4_GPIO            = 0,
 137         GPIO1B4_UART3_CTS_N,
 138         GPIO1B4_GPS_RFCLK,
 139
 140         GPIO1B3_SHIFT           = 6,
 141         GPIO1B3_MASK            = 3,
 142         GPIO1B3_GPIO            = 0,
 143         GPIO1B3_UART3_SOUT,
 144         GPIO1B3_GPS_SIG,
 145
 146         GPIO1B2_SHIFT           = 4,
 147         GPIO1B2_MASK            = 3,
 148         GPIO1B2_GPIO            = 0,
 149         GPIO1B2_UART3_SIN,
 150         GPIO1B2_GPS_MAG,
 151
 152         GPIO1B1_SHIFT           = 2,
 153         GPIO1B1_MASK            = 3,
 154         GPIO1B1_GPIO            = 0,
 155         GPIO1B1_UART2_SOUT,
 156         GPIO1B1_JTAG_TDO,
 157
 158         GPIO1B0_SHIFT           = 0,
 159         GPIO1B0_MASK            = 3,
 160         GPIO1B0_GPIO            = 0,
 161         GPIO1B0_UART2_SIN,
 162         GPIO1B0_JTAG_TDI,
 163 };
 164
 165 /* GRF_GPIO1D_IOMUX */
 166 enum {
 167         GPIO1D7_SHIFT           = 14,
 168         GPIO1D7_MASK            = 1,
 169         GPIO1D7_GPIO            = 0,
 170         GPIO1D7_I2C4_SCL,
 171
 172         GPIO1D6_SHIFT           = 12,
 173         GPIO1D6_MASK            = 1,
 174         GPIO1D6_GPIO            = 0,
 175         GPIO1D6_I2C4_SDA,
 176
 177         GPIO1D5_SHIFT           = 10,
 178         GPIO1D5_MASK            = 1,
 179         GPIO1D5_GPIO            = 0,
 180         GPIO1D5_I2C2_SCL,
 181
 182         GPIO1D4_SHIFT           = 8,
 183         GPIO1D4_MASK            = 1,
 184         GPIO1D4_GPIO            = 0,
 185         GPIO1D4_I2C2_SDA,
 186
 187         GPIO1D3_SHIFT           = 6,
 188         GPIO1D3_MASK            = 1,
 189         GPIO1D3_GPIO            = 0,
 190         GPIO1D3_I2C1_SCL,
 191
 192         GPIO1D2_SHIFT           = 4,
 193         GPIO1D2_MASK            = 1,
 194         GPIO1D2_GPIO            = 0,
 195         GPIO1D2_I2C1_SDA,
 196
 197         GPIO1D1_SHIFT           = 2,
 198         GPIO1D1_MASK            = 1,
 199         GPIO1D1_GPIO            = 0,
 200         GPIO1D1_I2C0_SCL,
 201
 202         GPIO1D0_SHIFT           = 0,
 203         GPIO1D0_MASK            = 1,
 204         GPIO1D0_GPIO            = 0,
 205         GPIO1D0_I2C0_SDA,
 206 };
 207
 208 /* GRF_GPIO3A_IOMUX */
 209 enum {
 210         GPIO3A7_SHIFT           = 14,
 211         GPIO3A7_MASK            = 1,
 212         GPIO3A7_GPIO            = 0,
 213         GPIO3A7_SDMMC0_DATA3,
 214
 215         GPIO3A6_SHIFT           = 12,
 216         GPIO3A6_MASK            = 1,
 217         GPIO3A6_GPIO            = 0,
 218         GPIO3A6_SDMMC0_DATA2,
 219
 220         GPIO3A5_SHIFT           = 10,
 221         GPIO3A5_MASK            = 1,
 222         GPIO3A5_GPIO            = 0,
 223         GPIO3A5_SDMMC0_DATA1,
 224
 225         GPIO3A4_SHIFT           = 8,
 226         GPIO3A4_MASK            = 1,
 227         GPIO3A4_GPIO            = 0,
 228         GPIO3A4_SDMMC0_DATA0,
 229
 230         GPIO3A3_SHIFT           = 6,
 231         GPIO3A3_MASK            = 1,
 232         GPIO3A3_GPIO            = 0,
 233         GPIO3A3_SDMMC0_CMD,
 234
 235         GPIO3A2_SHIFT           = 4,
 236         GPIO3A2_MASK            = 1,
 237         GPIO3A2_GPIO            = 0,
 238         GPIO3A2_SDMMC0_CLKOUT,
 239
 240         GPIO3A1_SHIFT           = 2,
 241         GPIO3A1_MASK            = 1,
 242         GPIO3A1_GPIO            = 0,
 243         GPIO3A1_SDMMC0_PWREN,
 244
 245         GPIO3A0_SHIFT           = 0,
 246         GPIO3A0_MASK            = 1,
 247         GPIO3A0_GPIO            = 0,
 248         GPIO3A0_SDMMC0_RSTN,
 249 };
 250
 251 /* GRF_GPIO3B_IOMUX */
 252 enum {
 253         GPIO3B7_SHIFT           = 14,
 254         GPIO3B7_MASK            = 3,
 255         GPIO3B7_GPIO            = 0,
 256         GPIO3B7_CIF_DATA11,
 257         GPIO3B7_I2C3_SCL,
 258
 259         GPIO3B6_SHIFT           = 12,
 260         GPIO3B6_MASK            = 3,
 261         GPIO3B6_GPIO            = 0,
 262         GPIO3B6_CIF_DATA10,
 263         GPIO3B6_I2C3_SDA,
 264
 265         GPIO3B5_SHIFT           = 10,
 266         GPIO3B5_MASK            = 3,
 267         GPIO3B5_GPIO            = 0,
 268         GPIO3B5_CIF_DATA1,
 269         GPIO3B5_HSADC_DATA9,
 270
 271         GPIO3B4_SHIFT           = 8,
 272         GPIO3B4_MASK            = 3,
 273         GPIO3B4_GPIO            = 0,
 274         GPIO3B4_CIF_DATA0,
 275         GPIO3B4_HSADC_DATA8,
 276
 277         GPIO3B3_SHIFT           = 6,
 278         GPIO3B3_MASK            = 1,
 279         GPIO3B3_GPIO            = 0,
 280         GPIO3B3_CIF_CLKOUT,
 281
 282         GPIO3B2_SHIFT           = 4,
 283         GPIO3B2_MASK            = 1,
 284         GPIO3B2_GPIO            = 0,
 285         /* no muxes */
 286
 287         GPIO3B1_SHIFT           = 2,
 288         GPIO3B1_MASK            = 1,
 289         GPIO3B1_GPIO            = 0,
 290         GPIO3B1_SDMMC0_WRITE_PRT,
 291
 292         GPIO3B0_SHIFT           = 0,
 293         GPIO3B0_MASK            = 1,
 294         GPIO3B0_GPIO            = 0,
 295         GPIO3B0_SDMMC_DETECT_N,
 296 };
 297
 298 /* GRF_GPIO3C_IOMUX */
 299 enum {
 300         GPIO3C7_SHIFT           = 14,
 301         GPIO3C7_MASK            = 3,
 302         GPIO3C7_GPIO            = 0,
 303         GPIO3C7_SDMMC1_WRITE_PRT,
 304         GPIO3C7_RMII_CRS_DVALID,
 305         GPIO3C7_RESERVED,
 306
 307         GPIO3C6_SHIFT           = 12,
 308         GPIO3C6_MASK            = 3,
 309         GPIO3C6_GPIO            = 0,
 310         GPIO3C6_SDMMC1_DECTN,
 311         GPIO3C6_RMII_RX_ERR,
 312         GPIO3C6_RESERVED,
 313
 314         GPIO3C5_SHIFT           = 10,
 315         GPIO3C5_MASK            = 3,
 316         GPIO3C5_GPIO            = 0,
 317         GPIO3C5_SDMMC1_CLKOUT,
 318         GPIO3C5_RMII_CLKOUT,
 319         GPIO3C5_RMII_CLKIN,
 320
 321         GPIO3C4_SHIFT           = 8,
 322         GPIO3C4_MASK            = 3,
 323         GPIO3C4_GPIO            = 0,
 324         GPIO3C4_SDMMC1_DATA3,
 325         GPIO3C4_RMII_RXD1,
 326         GPIO3C4_RESERVED,
 327
 328         GPIO3C3_SHIFT           = 6,
 329         GPIO3C3_MASK            = 3,
 330         GPIO3C3_GPIO            = 0,
 331         GPIO3C3_SDMMC1_DATA2,
 332         GPIO3C3_RMII_RXD0,
 333         GPIO3C3_RESERVED,
 334
 335         GPIO3C2_SHIFT           = 4,
 336         GPIO3C2_MASK            = 3,
 337         GPIO3C2_GPIO            = 0,
 338         GPIO3C2_SDMMC1_DATA1,
 339         GPIO3C2_RMII_TXD0,
 340         GPIO3C2_RESERVED,
 341
 342         GPIO3C1_SHIFT           = 2,
 343         GPIO3C1_MASK            = 3,
 344         GPIO3C1_GPIO            = 0,
 345         GPIO3C1_SDMMC1_DATA0,
 346         GPIO3C1_RMII_TXD1,
 347         GPIO3C1_RESERVED,
 348
 349         GPIO3C0_SHIFT           = 0,
 350         GPIO3C0_MASK            = 3,
 351         GPIO3C0_GPIO            = 0,
 352         GPIO3C0_SDMMC1_CMD,
 353         GPIO3C0_RMII_TX_EN,
 354         GPIO3C0_RESERVED,
 355 };
 356
 357 /* GRF_GPIO3D_IOMUX */
 358 enum {
 359         GPIO3D6_SHIFT           = 12,
 360         GPIO3D6_MASK            = 3,
 361         GPIO3D6_GPIO            = 0,
 362         GPIO3D6_PWM_3,
 363         GPIO3D6_JTAG_TMS,
 364         GPIO3D6_HOST_DRV_VBUS,
 365
 366         GPIO3D5_SHIFT           = 10,
 367         GPIO3D5_MASK            = 3,
 368         GPIO3D5_GPIO            = 0,
 369         GPIO3D5_PWM_2,
 370         GPIO3D5_JTAG_TCK,
 371         GPIO3D5_OTG_DRV_VBUS,
 372
 373         GPIO3D4_SHIFT           = 8,
 374         GPIO3D4_MASK            = 3,
 375         GPIO3D4_GPIO            = 0,
 376         GPIO3D4_PWM_1,
 377         GPIO3D4_JTAG_TRSTN,
 378
 379         GPIO3D3_SHIFT           = 6,
 380         GPIO3D3_MASK            = 3,
 381         GPIO3D3_GPIO            = 0,
 382         GPIO3D3_PWM_0,
 383
 384         GPIO3D2_SHIFT           = 4,
 385         GPIO3D2_MASK            = 3,
 386         GPIO3D2_GPIO            = 0,
 387         GPIO3D2_SDMMC1_INT_N,
 388
 389         GPIO3D1_SHIFT           = 2,
 390         GPIO3D1_MASK            = 3,
 391         GPIO3D1_GPIO            = 0,
 392         GPIO3D1_SDMMC1_BACKEND_PWR,
 393         GPIO3D1_MII_MDCLK,
 394
 395         GPIO3D0_SHIFT           = 0,
 396         GPIO3D0_MASK            = 3,
 397         GPIO3D0_GPIO            = 0,
 398         GPIO3D0_SDMMC1_PWR_EN,
 399         GPIO3D0_MII_MD,
 400 };
 401
 402 struct rk3188_pinctrl_priv {
 403         struct rk3188_grf *grf;
 404         struct rk3188_pmu *pmu;
 405         int num_banks;
 406 };
 407
 408 /**
 409  * Encode variants of iomux registers into a type variable
 410  */
 411 #define IOMUX_GPIO_ONLY         BIT(0)
 412
 413 /**
 414  * @type: iomux variant using IOMUX_* constants
 415  * @offset: if initialized to -1 it will be autocalculated, by specifying
 416  *          an initial offset value the relevant source offset can be reset
 417  *          to a new value for autocalculating the following iomux registers.
 418  */
 419 struct rockchip_iomux {
 420         u8 type;
 421         s16 offset;
 422 };
 423
 424 /**
 425  * @reg: register offset of the gpio bank
 426  * @nr_pins: number of pins in this bank
 427  * @bank_num: number of the bank, to account for holes
 428  * @name: name of the bank
 429  * @iomux: array describing the 4 iomux sources of the bank
 430  */
 431 struct rockchip_pin_bank {
 432         u16 reg;
 433         u8 nr_pins;
 434         u8 bank_num;
 435         char *name;
 436         struct rockchip_iomux iomux[4];
 437 };
 438
 439 #define PIN_BANK(id, pins, label)                       \
 440         {                                               \
 441                 .bank_num       = id,                   \
 442                 .nr_pins        = pins,                 \
 443                 .name           = label,                \
 444                 .iomux          = {                     \
 445                         { .offset = -1 },               \
 446                         { .offset = -1 },               \
 447                         { .offset = -1 },               \
 448                         { .offset = -1 },               \
 449                 },                                      \
 450         }
 451
 452 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 453         {                                                               \
 454                 .bank_num       = id,                                   \
 455                 .nr_pins        = pins,                                 \
 456                 .name           = label,                                \
 457                 .iomux          = {                                     \
 458                         { .type = iom0, .offset = -1 },                 \
 459                         { .type = iom1, .offset = -1 },                 \
 460                         { .type = iom2, .offset = -1 },                 \
 461                         { .type = iom3, .offset = -1 },                 \
 462                 },                                                      \
 463         }
 464
 465 #ifndef CONFIG_SPL_BUILD
 466 static struct rockchip_pin_bank rk3188_pin_banks[] = {
 467         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
 468         PIN_BANK(1, 32, "gpio1"),
 469         PIN_BANK(2, 32, "gpio2"),
 470         PIN_BANK(3, 32, "gpio3"),
 471 };
 472 #endif
 473
 474 static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id)
 475 {
 476         switch (pwm_id) {
 477         case PERIPH_ID_PWM0:
 478                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT,
 479                              GPIO3D3_PWM_0 << GPIO3D3_SHIFT);
 480                 break;
 481         case PERIPH_ID_PWM1:
 482                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT,
 483                              GPIO3D4_PWM_1 << GPIO3D4_SHIFT);
 484                 break;
 485         case PERIPH_ID_PWM2:
 486                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT,
 487                              GPIO3D5_PWM_2 << GPIO3D5_SHIFT);
 488                 break;
 489         case PERIPH_ID_PWM3:
 490                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT,
 491                              GPIO3D6_PWM_3 << GPIO3D6_SHIFT);
 492                 break;
 493         default:
 494                 debug("pwm id = %d iomux error!\n", pwm_id);
 495                 break;
 496         }
 497 }
 498
 499 static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf,
 500                                       struct rk3188_pmu *pmu, int i2c_id)
 501 {
 502         switch (i2c_id) {
 503         case PERIPH_ID_I2C0:
 504                 rk_clrsetreg(&grf->gpio1d_iomux,
 505                                 GPIO1D1_MASK << GPIO1D1_SHIFT |
 506                                 GPIO1D0_MASK << GPIO1D0_SHIFT,
 507                                 GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT |
 508                                 GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT);
 509                 /* enable new i2c controller */
 510                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT,
 511                                              1 << RKI2C0_SEL_SHIFT);
 512                 break;
 513         case PERIPH_ID_I2C1:
 514                 rk_clrsetreg(&grf->gpio1d_iomux,
 515                                 GPIO1D3_MASK << GPIO1D3_SHIFT |
 516                                 GPIO1D2_MASK << GPIO1D2_SHIFT,
 517                                 GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT |
 518                                 GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT);
 519                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT,
 520                                              1 << RKI2C1_SEL_SHIFT);
 521                 break;
 522         case PERIPH_ID_I2C2:
 523                 rk_clrsetreg(&grf->gpio1d_iomux,
 524                                 GPIO1D5_MASK << GPIO1D5_SHIFT |
 525                                 GPIO1D4_MASK << GPIO1D4_SHIFT,
 526                                 GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT |
 527                                 GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT);
 528                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT,
 529                                              1 << RKI2C2_SEL_SHIFT);
 530                 break;
 531         case PERIPH_ID_I2C3:
 532                 rk_clrsetreg(&grf->gpio3b_iomux,
 533                                 GPIO3B7_MASK << GPIO3B7_SHIFT |
 534                                 GPIO3B6_MASK << GPIO3B6_SHIFT,
 535                                 GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT |
 536                                 GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT);
 537                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT,
 538                                              1 << RKI2C3_SEL_SHIFT);
 539                 break;
 540         case PERIPH_ID_I2C4:
 541                 rk_clrsetreg(&grf->gpio1d_iomux,
 542                                 GPIO1D7_MASK << GPIO1D7_SHIFT |
 543                                 GPIO1D6_MASK << GPIO1D6_SHIFT,
 544                                 GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT |
 545                                 GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT);
 546                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT,
 547                                              1 << RKI2C4_SEL_SHIFT);
 548                 break;
 549         default:
 550                 debug("i2c id = %d iomux error!\n", i2c_id);
 551                 break;
 552         }
 553 }
 554
 555 static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf,
 556                                      enum periph_id spi_id, int cs)
 557 {
 558         switch (spi_id) {
 559         case PERIPH_ID_SPI0:
 560                 switch (cs) {
 561                 case 0:
 562                         rk_clrsetreg(&grf->gpio1a_iomux,
 563                                      GPIO1A7_MASK << GPIO1A7_SHIFT,
 564                                      GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT);
 565                         break;
 566                 case 1:
 567                         rk_clrsetreg(&grf->gpio1b_iomux,
 568                                      GPIO1B7_MASK << GPIO1B7_SHIFT,
 569                                      GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT);
 570                         break;
 571                 default:
 572                         goto err;
 573                 }
 574                 rk_clrsetreg(&grf->gpio1a_iomux,
 575                              GPIO1A4_MASK << GPIO1A4_SHIFT |
 576                              GPIO1A5_MASK << GPIO1A5_SHIFT |
 577                              GPIO1A6_MASK << GPIO1A6_SHIFT,
 578                              GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT |
 579                              GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT |
 580                              GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT);
 581                 break;
 582         case PERIPH_ID_SPI1:
 583                 switch (cs) {
 584                 case 0:
 585                         rk_clrsetreg(&grf->gpio0d_iomux,
 586                                      GPIO0D7_MASK << GPIO0D7_SHIFT,
 587                                      GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT);
 588                         break;
 589                 case 1:
 590                         rk_clrsetreg(&grf->gpio1b_iomux,
 591                                      GPIO1B6_MASK << GPIO1B6_SHIFT,
 592                                      GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT);
 593                         break;
 594                 default:
 595                         goto err;
 596                 }
 597                 rk_clrsetreg(&grf->gpio0d_iomux,
 598                              GPIO0D4_MASK << GPIO0D4_SHIFT |
 599                              GPIO0D5_MASK << GPIO0D5_SHIFT |
 600                              GPIO0D6_MASK << GPIO0D6_SHIFT,
 601                              GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT |
 602                              GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT |
 603                              GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT);
 604                 break;
 605         default:
 606                 goto err;
 607         }
 608
 609         return 0;
 610 err:
 611         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 612         return -ENOENT;
 613 }
 614
 615 static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id)
 616 {
 617         switch (uart_id) {
 618         case PERIPH_ID_UART0:
 619                 rk_clrsetreg(&grf->gpio1a_iomux,
 620                              GPIO1A3_MASK << GPIO1A3_SHIFT |
 621                              GPIO1A2_MASK << GPIO1A2_SHIFT |
 622                              GPIO1A1_MASK << GPIO1A1_SHIFT |
 623                              GPIO1A0_MASK << GPIO1A0_SHIFT,
 624                              GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT |
 625                              GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT |
 626                              GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT |
 627                              GPIO1A0_UART0_SIN << GPIO1A0_SHIFT);
 628                 break;
 629         case PERIPH_ID_UART1:
 630                 rk_clrsetreg(&grf->gpio1a_iomux,
 631                              GPIO1A7_MASK << GPIO1A7_SHIFT |
 632                              GPIO1A6_MASK << GPIO1A6_SHIFT |
 633                              GPIO1A5_MASK << GPIO1A5_SHIFT |
 634                              GPIO1A4_MASK << GPIO1A4_SHIFT,
 635                              GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT |
 636                              GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT |
 637                              GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT |
 638                              GPIO1A4_UART1_SIN << GPIO1A4_SHIFT);
 639                 break;
 640         case PERIPH_ID_UART2:
 641                 rk_clrsetreg(&grf->gpio1b_iomux,
 642                              GPIO1B1_MASK << GPIO1B1_SHIFT |
 643                              GPIO1B0_MASK << GPIO1B0_SHIFT,
 644                              GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
 645                              GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
 646                 break;
 647         case PERIPH_ID_UART3:
 648                 rk_clrsetreg(&grf->gpio1b_iomux,
 649                              GPIO1B5_MASK << GPIO1B5_SHIFT |
 650                              GPIO1B4_MASK << GPIO1B4_SHIFT |
 651                              GPIO1B3_MASK << GPIO1B3_SHIFT |
 652                              GPIO1B2_MASK << GPIO1B2_SHIFT,
 653                              GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT |
 654                              GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT |
 655                              GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT |
 656                              GPIO1B2_UART3_SIN << GPIO1B2_SHIFT);
 657                 break;
 658         default:
 659                 debug("uart id = %d iomux error!\n", uart_id);
 660                 break;
 661         }
 662 }
 663
 664 static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id)
 665 {
 666         switch (mmc_id) {
 667         case PERIPH_ID_EMMC:
 668                 rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT,
 669                                              1 << EMMC_FLASH_SEL_SHIFT);
 670                 rk_clrsetreg(&grf->gpio0d_iomux,
 671                              GPIO0D2_MASK << GPIO0D2_SHIFT |
 672                              GPIO0D0_MASK << GPIO0D0_SHIFT,
 673                              GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT |
 674                              GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT);
 675                 break;
 676         case PERIPH_ID_SDCARD:
 677                 rk_clrsetreg(&grf->gpio3b_iomux,
 678                              GPIO3B0_MASK << GPIO3B0_SHIFT,
 679                              GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT);
 680                 rk_clrsetreg(&grf->gpio3a_iomux,
 681                              GPIO3A7_MASK << GPIO3A7_SHIFT |
 682                              GPIO3A6_MASK << GPIO3A6_SHIFT |
 683                              GPIO3A5_MASK << GPIO3A5_SHIFT |
 684                              GPIO3A4_MASK << GPIO3A4_SHIFT |
 685                              GPIO3A3_MASK << GPIO3A3_SHIFT |
 686                              GPIO3A3_MASK << GPIO3A2_SHIFT,
 687                              GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT |
 688                              GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT |
 689                              GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT |
 690                              GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT |
 691                              GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT |
 692                              GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT);
 693                 break;
 694         default:
 695                 debug("mmc id = %d iomux error!\n", mmc_id);
 696                 break;
 697         }
 698 }
 699
 700 static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags)
 701 {
 702         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 703
 704         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 705         switch (func) {
 706         case PERIPH_ID_PWM0:
 707         case PERIPH_ID_PWM1:
 708         case PERIPH_ID_PWM2:
 709         case PERIPH_ID_PWM3:
 710         case PERIPH_ID_PWM4:
 711                 pinctrl_rk3188_pwm_config(priv->grf, func);
 712                 break;
 713         case PERIPH_ID_I2C0:
 714         case PERIPH_ID_I2C1:
 715         case PERIPH_ID_I2C2:
 716         case PERIPH_ID_I2C3:
 717         case PERIPH_ID_I2C4:
 718         case PERIPH_ID_I2C5:
 719                 pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func);
 720                 break;
 721         case PERIPH_ID_SPI0:
 722         case PERIPH_ID_SPI1:
 723         case PERIPH_ID_SPI2:
 724                 pinctrl_rk3188_spi_config(priv->grf, func, flags);
 725                 break;
 726         case PERIPH_ID_UART0:
 727         case PERIPH_ID_UART1:
 728         case PERIPH_ID_UART2:
 729         case PERIPH_ID_UART3:
 730         case PERIPH_ID_UART4:
 731                 pinctrl_rk3188_uart_config(priv->grf, func);
 732                 break;
 733                 break;
 734         case PERIPH_ID_SDMMC0:
 735         case PERIPH_ID_SDMMC1:
 736                 pinctrl_rk3188_sdmmc_config(priv->grf, func);
 737                 break;
 738         default:
 739                 return -EINVAL;
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int rk3188_pinctrl_get_periph_id(struct udevice *dev,
 746                                         struct udevice *periph)
 747 {
 748 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 749         u32 cell[3];
 750         int ret;
 751
 752         ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 753         if (ret < 0)
 754                 return -EINVAL;
 755
 756         switch (cell[1]) {
 757         case 44:
 758                 return PERIPH_ID_SPI0;
 759         case 45:
 760                 return PERIPH_ID_SPI1;
 761         case 46:
 762                 return PERIPH_ID_SPI2;
 763         case 60:
 764                 return PERIPH_ID_I2C0;
 765         case 62: /* Note strange order */
 766                 return PERIPH_ID_I2C1;
 767         case 61:
 768                 return PERIPH_ID_I2C2;
 769         case 63:
 770                 return PERIPH_ID_I2C3;
 771         case 64:
 772                 return PERIPH_ID_I2C4;
 773         case 65:
 774                 return PERIPH_ID_I2C5;
 775         }
 776 #endif
 777
 778         return -ENOENT;
 779 }
 780
 781 static int rk3188_pinctrl_set_state_simple(struct udevice *dev,
 782                                            struct udevice *periph)
 783 {
 784         int func;
 785
 786         func = rk3188_pinctrl_get_periph_id(dev, periph);
 787         if (func < 0)
 788                 return func;
 789         return rk3188_pinctrl_request(dev, func, 0);
 790 }
 791
 792 #ifndef CONFIG_SPL_BUILD
 793 int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv,
 794                                 int banknum, int ind, u32 **addrp, uint *shiftp,
 795                                 uint *maskp)
 796 {
 797         struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum];
 798         uint muxnum;
 799         u32 *addr;
 800
 801         for (muxnum = 0; muxnum < 4; muxnum++) {
 802                 struct rockchip_iomux *mux = &bank->iomux[muxnum];
 803
 804                 if (ind >= 8) {
 805                         ind -= 8;
 806                         continue;
 807                 }
 808
 809                 addr = &priv->grf->gpio0c_iomux - 2;
 810                 addr += mux->offset;
 811                 *shiftp = ind & 7;
 812                 *maskp = 3;
 813                 *shiftp *= 2;
 814
 815                 debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
 816                       *maskp, *shiftp);
 817                 *addrp = addr;
 818                 return 0;
 819         }
 820
 821         return -EINVAL;
 822 }
 823
 824 static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
 825                                        int index)
 826 {
 827         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 828         uint shift;
 829         uint mask;
 830         u32 *addr;
 831         int ret;
 832
 833         ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 834                                           &mask);
 835         if (ret)
 836                 return ret;
 837         return (readl(addr) & mask) >> shift;
 838 }
 839
 840 static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 841                                    int muxval, int flags)
 842 {
 843         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 844         uint shift, ind = index;
 845         uint mask;
 846         u32 *addr;
 847         int ret;
 848
 849         debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
 850         ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 851                                           &mask);
 852         if (ret)
 853                 return ret;
 854         rk_clrsetreg(addr, mask << shift, muxval << shift);
 855
 856         /* Handle pullup/pulldown */
 857         if (flags) {
 858                 uint val = 0;
 859
 860                 if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
 861                         val = 1;
 862                 else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
 863                         val = 2;
 864
 865                 ind = index >> 3;
 866
 867                 if (banknum == 0 && index < 12) {
 868                         addr = &priv->pmu->gpio0_p[ind];
 869                         shift = (index & 7) * 2;
 870                 } else if (banknum == 0 && index >= 12) {
 871                         addr = &priv->grf->gpio0_p[ind - 1];
 872                         /*
 873                          * The bits in the grf-registers have an inverse
 874                          * ordering with the lowest pin being in bits 15:14
 875                          * and the highest pin in bits 1:0 .
 876                          */
 877                         shift = (7 - (index & 7)) * 2;
 878                 } else {
 879                         addr = &priv->grf->gpio1_p[banknum - 1][ind];
 880                         shift = (7 - (index & 7)) * 2;
 881                 }
 882                 debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
 883                       shift);
 884                 rk_clrsetreg(addr, 3 << shift, val << shift);
 885         }
 886
 887         return 0;
 888 }
 889
 890 static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 891 {
 892         const void *blob = gd->fdt_blob;
 893         int pcfg_node, ret, flags, count, i;
 894         u32 cell[60], *ptr;
 895
 896         debug("%s: %s %s\n", __func__, dev->name, config->name);
 897         ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
 898                                          "rockchip,pins", cell,
 899                                          ARRAY_SIZE(cell));
 900         if (ret < 0) {
 901                 debug("%s: bad array %d\n", __func__, ret);
 902                 return -EINVAL;
 903         }
 904         count = ret;
 905         for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
 906                 pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
 907                 if (pcfg_node < 0)
 908                         return -EINVAL;
 909                 flags = pinctrl_decode_pin_config(blob, pcfg_node);
 910                 if (flags < 0)
 911                         return flags;
 912
 913                 ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
 914                                               flags);
 915                 if (ret)
 916                         return ret;
 917         }
 918
 919         return 0;
 920 }
 921 #endif
 922
 923 static struct pinctrl_ops rk3188_pinctrl_ops = {
 924 #ifndef CONFIG_SPL_BUILD
 925         .set_state      = rk3188_pinctrl_set_state,
 926         .get_gpio_mux   = rk3188_pinctrl_get_gpio_mux,
 927 #endif
 928         .set_state_simple       = rk3188_pinctrl_set_state_simple,
 929         .request        = rk3188_pinctrl_request,
 930         .get_periph_id  = rk3188_pinctrl_get_periph_id,
 931 };
 932
 933 #ifndef CONFIG_SPL_BUILD
 934 static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv,
 935                                        struct rockchip_pin_bank *banks,
 936                                        int count)
 937 {
 938         struct rockchip_pin_bank *bank;
 939         uint reg, muxnum, banknum;
 940
 941         reg = 0;
 942         for (banknum = 0; banknum < count; banknum++) {
 943                 bank = &banks[banknum];
 944                 bank->reg = reg;
 945                 debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
 946                 for (muxnum = 0; muxnum < 4; muxnum++) {
 947                         struct rockchip_iomux *mux = &bank->iomux[muxnum];
 948
 949                         mux->offset = reg;
 950                         reg += 1;
 951                 }
 952         }
 953
 954         return 0;
 955 }
 956 #endif
 957
 958 static int rk3188_pinctrl_probe(struct udevice *dev)
 959 {
 960         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 961         int ret = 0;
 962
 963         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 964         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 965         debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
 966 #ifndef CONFIG_SPL_BUILD
 967         ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks,
 968                                           ARRAY_SIZE(rk3188_pin_banks));
 969 #endif
 970
 971         return ret;
 972 }
 973
 974 static const struct udevice_id rk3188_pinctrl_ids[] = {
 975         { .compatible = "rockchip,rk3188-pinctrl" },
 976         { }
 977 };
 978
 979 U_BOOT_DRIVER(pinctrl_rk3188) = {
 980         .name           = "rockchip_rk3188_pinctrl",
 981         .id             = UCLASS_PINCTRL,
 982         .of_match       = rk3188_pinctrl_ids,
 983         .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv),
 984         .ops            = &rk3188_pinctrl_ops,
 985 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 986         .bind           = dm_scan_fdt_dev,
 987 #endif
 988         .probe          = rk3188_pinctrl_probe,
 989 };