1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
8 #include <dm/pinctrl.h>
13 #include "pinctrl-rockchip.h"
15 #define MAX_ROCKCHIP_PINS_ENTRIES 30
16 #define MAX_ROCKCHIP_GPIO_PER_BANK 32
17 #define RK_FUNC_GPIO 0
19 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
21 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
22 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
24 if (bank >= ctrl->nr_banks) {
25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
29 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
30 debug("pin conf pin %d >= %d\n", pin,
31 MAX_ROCKCHIP_GPIO_PER_BANK);
38 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
39 int *reg, u8 *bit, int *mask)
41 struct rockchip_pinctrl_priv *priv = bank->priv;
42 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
43 struct rockchip_mux_recalced_data *data;
46 for (i = 0; i < ctrl->niomux_recalced; i++) {
47 data = &ctrl->iomux_recalced[i];
48 if (data->num == bank->bank_num &&
53 if (i >= ctrl->niomux_recalced)
61 bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
62 int mux, u32 *reg, u32 *value)
64 struct rockchip_pinctrl_priv *priv = bank->priv;
65 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
66 struct rockchip_mux_route_data *data;
69 for (i = 0; i < ctrl->niomux_routes; i++) {
70 data = &ctrl->iomux_routes[i];
71 if (data->bank_num == bank->bank_num &&
72 data->pin == pin && data->func == mux)
76 if (i >= ctrl->niomux_routes)
79 *reg = data->route_offset;
80 *value = data->route_val;
85 int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
89 if (mux_type & IOMUX_WIDTH_4BIT) {
94 } else if (mux_type & IOMUX_WIDTH_3BIT) {
96 * pin0 ~ pin4 are at first register, and
97 * pin5 ~ pin7 are at second register.
101 *bit = (pin % 8 % 5) * 3;
104 *bit = (pin % 8) * 2;
111 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
113 struct rockchip_pinctrl_priv *priv = bank->priv;
114 int iomux_num = (pin / 8);
115 struct regmap *regmap;
117 int reg, ret, mask, mux_type;
123 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
124 debug("pin %d is unrouted\n", pin);
128 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
131 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
132 ? priv->regmap_pmu : priv->regmap_base;
134 /* get basic quadrupel of mux registers and the correct reg inside */
135 mux_type = bank->iomux[iomux_num].type;
136 reg = bank->iomux[iomux_num].offset;
137 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
139 if (bank->recalced_mask & BIT(pin))
140 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
142 ret = regmap_read(regmap, reg, &val);
146 return ((val >> bit) & mask);
149 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
151 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
152 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
154 return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
157 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
160 int iomux_num = (pin / 8);
165 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
166 debug("pin %d is unrouted\n", pin);
170 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
171 if (mux != IOMUX_GPIO_ONLY) {
172 debug("pin %d only supports a gpio mux\n", pin);
181 * Set a new mux function for a pin.
183 * The register is divided into the upper and lower 16 bit. When changing
184 * a value, the previous register value is not read and changed. Instead
185 * it seems the changed bits are marked in the upper 16 bit, while the
186 * changed value gets set in the same offset in the lower 16 bit.
187 * All pin settings seem to be 2 bit wide in both the upper and lower
189 * @bank: pin bank to change
190 * @pin: pin to change
191 * @mux: new mux function to set
193 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
195 struct rockchip_pinctrl_priv *priv = bank->priv;
196 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
197 int iomux_num = (pin / 8);
200 ret = rockchip_verify_mux(bank, pin, mux);
204 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
207 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
212 ret = ctrl->set_mux(bank, pin, mux);
217 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
218 { 2, 4, 8, 12, -1, -1, -1, -1 },
219 { 3, 6, 9, 12, -1, -1, -1, -1 },
220 { 5, 10, 15, 20, -1, -1, -1, -1 },
221 { 4, 6, 8, 10, 12, 14, 16, 18 },
222 { 4, 7, 10, 13, 16, 19, 22, 26 }
225 int rockchip_translate_drive_value(int type, int strength)
230 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
231 if (rockchip_perpin_drv_list[type][i] == strength) {
234 } else if (rockchip_perpin_drv_list[type][i] < 0) {
235 ret = rockchip_perpin_drv_list[type][i];
243 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
244 int pin_num, int strength)
246 struct rockchip_pinctrl_priv *priv = bank->priv;
247 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
249 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
252 if (!ctrl->set_drive)
255 return ctrl->set_drive(bank, pin_num, strength);
258 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
260 PIN_CONFIG_BIAS_DISABLE,
261 PIN_CONFIG_BIAS_PULL_UP,
262 PIN_CONFIG_BIAS_PULL_DOWN,
263 PIN_CONFIG_BIAS_BUS_HOLD
266 PIN_CONFIG_BIAS_DISABLE,
267 PIN_CONFIG_BIAS_PULL_DOWN,
268 PIN_CONFIG_BIAS_DISABLE,
269 PIN_CONFIG_BIAS_PULL_UP
273 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
274 int pin_num, int pull)
276 struct rockchip_pinctrl_priv *priv = bank->priv;
277 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
278 struct regmap *regmap;
279 int reg, ret, i, pull_type;
283 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
286 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
288 switch (ctrl->type) {
291 data = BIT(bit + 16);
292 if (pull == PIN_CONFIG_BIAS_DISABLE)
294 ret = regmap_write(regmap, reg, data);
301 pull_type = bank->pull_type[pin_num / 8];
303 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
305 if (rockchip_pull_list[pull_type][i] == pull) {
312 debug("unsupported pull setting %d\n", pull);
316 /* enable the write to the equivalent lower bits */
317 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
318 data |= (ret << bit);
320 ret = regmap_write(regmap, reg, data);
323 debug("unsupported pinctrl type\n");
330 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
331 int pin_num, int enable)
333 struct rockchip_pinctrl_priv *priv = bank->priv;
334 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
335 struct regmap *regmap;
340 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
343 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
347 /* enable the write to the equivalent lower bits */
348 data = BIT(bit + 16) | (enable << bit);
350 return regmap_write(regmap, reg, data);
354 * Pinconf_ops handling
356 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
359 switch (ctrl->type) {
362 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
363 pull == PIN_CONFIG_BIAS_DISABLE);
369 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
375 /* set the pin config settings for a specified pin */
376 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
377 u32 pin, u32 param, u32 arg)
379 struct rockchip_pinctrl_priv *priv = bank->priv;
380 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
384 case PIN_CONFIG_BIAS_DISABLE:
385 rc = rockchip_set_pull(bank, pin, param);
390 case PIN_CONFIG_BIAS_PULL_UP:
391 case PIN_CONFIG_BIAS_PULL_DOWN:
392 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
393 case PIN_CONFIG_BIAS_BUS_HOLD:
394 if (!rockchip_pinconf_pull_valid(ctrl, param))
400 rc = rockchip_set_pull(bank, pin, param);
405 case PIN_CONFIG_DRIVE_STRENGTH:
406 rc = rockchip_set_drive_perpin(bank, pin, arg);
411 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
412 if (!ctrl->schmitt_calc_reg)
415 rc = rockchip_set_schmitt(bank, pin, arg);
427 static const struct pinconf_param rockchip_conf_params[] = {
428 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
429 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
430 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
431 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
432 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
433 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
434 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
435 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
438 static int rockchip_pinconf_prop_name_to_param(const char *property,
441 const struct pinconf_param *p, *end;
443 p = rockchip_conf_params;
444 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
446 /* See if this pctldev supports this parameter */
447 for (; p < end; p++) {
448 if (!strcmp(property, p->property)) {
449 *default_value = p->default_value;
458 static int rockchip_pinctrl_set_state(struct udevice *dev,
459 struct udevice *config)
461 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
462 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
463 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
464 u32 bank, pin, mux, conf, arg, default_val;
466 const char *prop_name;
471 #ifdef CONFIG_OF_LIVE
472 const struct device_node *np;
475 int property_offset, pcfg_node;
476 const void *blob = gd->fdt_blob;
478 data = dev_read_prop(config, "rockchip,pins", &count);
480 debug("%s: bad array size %d\n", __func__, count);
484 count /= sizeof(u32);
485 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
486 debug("%s: unsupported pins array count %d\n",
491 for (i = 0; i < count; i++)
492 cells[i] = fdt32_to_cpu(data[i]);
494 for (i = 0; i < (count >> 2); i++) {
495 bank = cells[4 * i + 0];
496 pin = cells[4 * i + 1];
497 mux = cells[4 * i + 2];
498 conf = cells[4 * i + 3];
500 ret = rockchip_verify_config(dev, bank, pin);
504 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
508 node = ofnode_get_by_phandle(conf);
509 if (!ofnode_valid(node))
511 #ifdef CONFIG_OF_LIVE
512 np = ofnode_to_np(node);
513 for (pp = np->properties; pp; pp = pp->next) {
514 prop_name = pp->name;
515 prop_len = pp->length;
518 pcfg_node = ofnode_to_offset(node);
519 fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
520 value = fdt_getprop_by_offset(blob, property_offset,
521 &prop_name, &prop_len);
525 param = rockchip_pinconf_prop_name_to_param(prop_name,
530 if (prop_len >= sizeof(fdt32_t))
531 arg = fdt32_to_cpu(*(fdt32_t *)value);
535 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
538 debug("%s: rockchip_pinconf_set fail: %d\n",
548 const struct pinctrl_ops rockchip_pinctrl_ops = {
549 .set_state = rockchip_pinctrl_set_state,
550 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
553 /* retrieve the soc specific data */
554 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
556 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
557 struct rockchip_pin_ctrl *ctrl =
558 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
559 struct rockchip_pin_bank *bank;
560 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
562 grf_offs = ctrl->grf_mux_offset;
563 pmu_offs = ctrl->pmu_mux_offset;
564 drv_pmu_offs = ctrl->pmu_drv_offset;
565 drv_grf_offs = ctrl->grf_drv_offset;
566 bank = ctrl->pin_banks;
568 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
572 bank->pin_base = ctrl->nr_pins;
573 ctrl->nr_pins += bank->nr_pins;
575 /* calculate iomux and drv offsets */
576 for (j = 0; j < 4; j++) {
577 struct rockchip_iomux *iom = &bank->iomux[j];
578 struct rockchip_drv *drv = &bank->drv[j];
581 if (bank_pins >= bank->nr_pins)
584 /* preset iomux offset value, set new start value */
585 if (iom->offset >= 0) {
586 if (iom->type & IOMUX_SOURCE_PMU)
587 pmu_offs = iom->offset;
589 grf_offs = iom->offset;
590 } else { /* set current iomux offset */
591 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
595 /* preset drv offset value, set new start value */
596 if (drv->offset >= 0) {
597 if (iom->type & IOMUX_SOURCE_PMU)
598 drv_pmu_offs = drv->offset;
600 drv_grf_offs = drv->offset;
601 } else { /* set current drv offset */
602 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
603 drv_pmu_offs : drv_grf_offs;
606 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
607 i, j, iom->offset, drv->offset);
610 * Increase offset according to iomux width.
611 * 4bit iomux'es are spread over two registers.
613 inc = (iom->type & (IOMUX_WIDTH_4BIT |
614 IOMUX_WIDTH_3BIT)) ? 8 : 4;
615 if (iom->type & IOMUX_SOURCE_PMU)
621 * Increase offset according to drv width.
622 * 3bit drive-strenth'es are spread over two registers.
624 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
625 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
630 if (iom->type & IOMUX_SOURCE_PMU)
638 /* calculate the per-bank recalced_mask */
639 for (j = 0; j < ctrl->niomux_recalced; j++) {
642 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
643 pin = ctrl->iomux_recalced[j].pin;
644 bank->recalced_mask |= BIT(pin);
648 /* calculate the per-bank route_mask */
649 for (j = 0; j < ctrl->niomux_routes; j++) {
652 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
653 pin = ctrl->iomux_routes[j].pin;
654 bank->route_mask |= BIT(pin);
662 int rockchip_pinctrl_probe(struct udevice *dev)
664 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
665 struct rockchip_pin_ctrl *ctrl;
666 struct udevice *syscon;
667 struct regmap *regmap;
670 /* get rockchip grf syscon phandle */
671 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
674 debug("unable to find rockchip,grf syscon device (%d)\n", ret);
678 /* get grf-reg base address */
679 regmap = syscon_get_regmap(syscon);
681 debug("unable to find rockchip grf regmap\n");
684 priv->regmap_base = regmap;
686 /* option: get pmu-reg base address */
687 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
690 /* get pmugrf-reg base address */
691 regmap = syscon_get_regmap(syscon);
693 debug("unable to find rockchip pmu regmap\n");
696 priv->regmap_pmu = regmap;
699 ctrl = rockchip_pinctrl_get_soc_data(dev);
701 debug("driver data not available\n");