drivers/pinctrl/rockchip/pinctrl-rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/pinctrl.h>
   9 #include <regmap.h>
  10 #include <syscon.h>
  11
  12 #include "pinctrl-rockchip.h"
  13
  14 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
  15         {
  16                 /* uart2dbga_rx */
  17                 .bank_num = 4,
  18                 .pin = 8,
  19                 .func = 2,
  20                 .route_offset = 0xe21c,
  21                 .route_val = BIT(16 + 10) | BIT(16 + 11),
  22         }, {
  23                 /* uart2dbgb_rx */
  24                 .bank_num = 4,
  25                 .pin = 16,
  26                 .func = 2,
  27                 .route_offset = 0xe21c,
  28                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
  29         }, {
  30                 /* uart2dbgc_rx */
  31                 .bank_num = 4,
  32                 .pin = 19,
  33                 .func = 1,
  34                 .route_offset = 0xe21c,
  35                 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
  36         }, {
  37                 /* pcie_clkreqn */
  38                 .bank_num = 2,
  39                 .pin = 26,
  40                 .func = 2,
  41                 .route_offset = 0xe21c,
  42                 .route_val = BIT(16 + 14),
  43         }, {
  44                 /* pcie_clkreqnb */
  45                 .bank_num = 4,
  46                 .pin = 24,
  47                 .func = 1,
  48                 .route_offset = 0xe21c,
  49                 .route_val = BIT(16 + 14) | BIT(14),
  50         },
  51 };
  52
  53 #define RK3399_PULL_GRF_OFFSET          0xe040
  54 #define RK3399_PULL_PMU_OFFSET          0x40
  55
  56 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  57                                          int pin_num, struct regmap **regmap,
  58                                          int *reg, u8 *bit)
  59 {
  60         struct rockchip_pinctrl_priv *priv = bank->priv;
  61
  62         /* The bank0:16 and bank1:32 pins are located in PMU */
  63         if (bank->bank_num == 0 || bank->bank_num == 1) {
  64                 *regmap = priv->regmap_pmu;
  65                 *reg = RK3399_PULL_PMU_OFFSET;
  66
  67                 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
  68
  69                 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
  70                 *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
  71                 *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
  72         } else {
  73                 *regmap = priv->regmap_base;
  74                 *reg = RK3399_PULL_GRF_OFFSET;
  75
  76                 /* correct the offset, as we're starting with the 3rd bank */
  77                 *reg -= 0x20;
  78                 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
  79                 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
  80
  81                 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
  82                 *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
  83         }
  84 }
  85
  86 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  87                                         int pin_num, struct regmap **regmap,
  88                                         int *reg, u8 *bit)
  89 {
  90         struct rockchip_pinctrl_priv *priv = bank->priv;
  91         int drv_num = (pin_num / 8);
  92
  93         /*  The bank0:16 and bank1:32 pins are located in PMU */
  94         if (bank->bank_num == 0 || bank->bank_num == 1)
  95                 *regmap = priv->regmap_pmu;
  96         else
  97                 *regmap = priv->regmap_base;
  98
  99         *reg = bank->drv[drv_num].offset;
 100         if (bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO ||
 101             bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)
 102                 *bit = (pin_num % 8) * 3;
 103         else
 104                 *bit = (pin_num % 8) * 2;
 105 }
 106
 107 static struct rockchip_pin_bank rk3399_pin_banks[] = {
 108         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
 109                                                          IOMUX_SOURCE_PMU,
 110                                                          IOMUX_SOURCE_PMU,
 111                                                          IOMUX_SOURCE_PMU,
 112                                                          IOMUX_SOURCE_PMU,
 113                                                          DRV_TYPE_IO_1V8_ONLY,
 114                                                          DRV_TYPE_IO_1V8_ONLY,
 115                                                          DRV_TYPE_IO_DEFAULT,
 116                                                          DRV_TYPE_IO_DEFAULT,
 117                                                          0x80,
 118                                                          0x88,
 119                                                          -1,
 120                                                          -1,
 121                                                          PULL_TYPE_IO_1V8_ONLY,
 122                                                          PULL_TYPE_IO_1V8_ONLY,
 123                                                          PULL_TYPE_IO_DEFAULT,
 124                                                          PULL_TYPE_IO_DEFAULT
 125                                                         ),
 126         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
 127                                         IOMUX_SOURCE_PMU,
 128                                         IOMUX_SOURCE_PMU,
 129                                         IOMUX_SOURCE_PMU,
 130                                         DRV_TYPE_IO_1V8_OR_3V0,
 131                                         DRV_TYPE_IO_1V8_OR_3V0,
 132                                         DRV_TYPE_IO_1V8_OR_3V0,
 133                                         DRV_TYPE_IO_1V8_OR_3V0,
 134                                         0xa0,
 135                                         0xa8,
 136                                         0xb0,
 137                                         0xb8
 138                                         ),
 139         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
 140                                       DRV_TYPE_IO_1V8_OR_3V0,
 141                                       DRV_TYPE_IO_1V8_ONLY,
 142                                       DRV_TYPE_IO_1V8_ONLY,
 143                                       PULL_TYPE_IO_DEFAULT,
 144                                       PULL_TYPE_IO_DEFAULT,
 145                                       PULL_TYPE_IO_1V8_ONLY,
 146                                       PULL_TYPE_IO_1V8_ONLY
 147                                       ),
 148         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
 149                            DRV_TYPE_IO_3V3_ONLY,
 150                            DRV_TYPE_IO_3V3_ONLY,
 151                            DRV_TYPE_IO_1V8_OR_3V0
 152                            ),
 153         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
 154                            DRV_TYPE_IO_1V8_3V0_AUTO,
 155                            DRV_TYPE_IO_1V8_OR_3V0,
 156                            DRV_TYPE_IO_1V8_OR_3V0
 157                            ),
 158 };
 159
 160 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
 161                 .pin_banks              = rk3399_pin_banks,
 162                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
 163                 .label                  = "RK3399-GPIO",
 164                 .type                   = RK3399,
 165                 .grf_mux_offset         = 0xe000,
 166                 .pmu_mux_offset         = 0x0,
 167                 .grf_drv_offset         = 0xe100,
 168                 .pmu_drv_offset         = 0x80,
 169                 .iomux_routes           = rk3399_mux_route_data,
 170                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
 171                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
 172                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
 173 };
 174
 175 static const struct udevice_id rk3399_pinctrl_ids[] = {
 176         {
 177                 .compatible = "rockchip,rk3399-pinctrl",
 178                 .data = (ulong)&rk3399_pin_ctrl
 179         },
 180         { }
 181 };
 182
 183 U_BOOT_DRIVER(pinctrl_rk3399) = {
 184         .name           = "rockchip_rk3399_pinctrl",
 185         .id             = UCLASS_PINCTRL,
 186         .of_match       = rk3399_pinctrl_ids,
 187         .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
 188         .ops            = &rockchip_pinctrl_ops,
 189 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 190         .bind           = dm_scan_fdt_dev,
 191 #endif
 192         .probe          = rockchip_pinctrl_probe,
 193 };