drivers/pinctrl/rockchip/pinctrl-rk3368.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/pinctrl.h>
   9 #include <regmap.h>
  10 #include <syscon.h>
  11
  12 #include "pinctrl-rockchip.h"
  13
  14 static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
  15 {
  16         struct rockchip_pinctrl_priv *priv = bank->priv;
  17         int iomux_num = (pin / 8);
  18         struct regmap *regmap;
  19         int reg, ret, mask, mux_type;
  20         u8 bit;
  21         u32 data;
  22
  23         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
  24                                 ? priv->regmap_pmu : priv->regmap_base;
  25
  26         /* get basic quadrupel of mux registers and the correct reg inside */
  27         mux_type = bank->iomux[iomux_num].type;
  28         reg = bank->iomux[iomux_num].offset;
  29         reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
  30
  31         data = (mask << (bit + 16));
  32         data |= (mux & mask) << bit;
  33         ret = regmap_write(regmap, reg, data);
  34
  35         return ret;
  36 }
  37
  38 #define RK3368_PULL_GRF_OFFSET          0x100
  39 #define RK3368_PULL_PMU_OFFSET          0x10
  40
  41 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  42                                          int pin_num, struct regmap **regmap,
  43                                          int *reg, u8 *bit)
  44 {
  45         struct rockchip_pinctrl_priv *priv = bank->priv;
  46
  47         /* The first 32 pins of the first bank are located in PMU */
  48         if (bank->bank_num == 0) {
  49                 *regmap = priv->regmap_pmu;
  50                 *reg = RK3368_PULL_PMU_OFFSET;
  51
  52                 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
  53                 *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
  54                 *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
  55         } else {
  56                 *regmap = priv->regmap_base;
  57                 *reg = RK3368_PULL_GRF_OFFSET;
  58
  59                 /* correct the offset, as we're starting with the 2nd bank */
  60                 *reg -= 0x10;
  61                 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
  62                 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
  63
  64                 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
  65                 *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
  66         }
  67 }
  68
  69 #define RK3368_DRV_PMU_OFFSET           0x20
  70 #define RK3368_DRV_GRF_OFFSET           0x200
  71
  72 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  73                                         int pin_num, struct regmap **regmap,
  74                                         int *reg, u8 *bit)
  75 {
  76         struct rockchip_pinctrl_priv *priv = bank->priv;
  77
  78         /* The first 32 pins of the first bank are located in PMU */
  79         if (bank->bank_num == 0) {
  80                 *regmap = priv->regmap_pmu;
  81                 *reg = RK3368_DRV_PMU_OFFSET;
  82         } else {
  83                 *regmap = priv->regmap_base;
  84                 *reg = RK3368_DRV_GRF_OFFSET;
  85
  86                 /* correct the offset, as we're starting with the 2nd bank */
  87                 *reg -= 0x10;
  88                 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
  89         }
  90
  91         *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
  92         *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
  93         *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
  94 }
  95
  96 static int rk3368_set_drive(struct rockchip_pin_bank *bank,
  97                             int pin_num, int strength)
  98 {
  99         struct regmap *regmap;
 100         int reg, ret;
 101         u32 data;
 102         u8 bit;
 103         int type = bank->drv[pin_num / 8].drv_type;
 104
 105         rk3368_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 106         ret = rockchip_translate_drive_value(type, strength);
 107         if (ret < 0) {
 108                 debug("unsupported driver strength %d\n", strength);
 109                 return ret;
 110         }
 111
 112         /* enable the write to the equivalent lower bits */
 113         data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 114         data |= (ret << bit);
 115         ret = regmap_write(regmap, reg, data);
 116
 117         return ret;
 118 }
 119
 120 static struct rockchip_pin_bank rk3368_pin_banks[] = {
 121         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
 122                                              IOMUX_SOURCE_PMU,
 123                                              IOMUX_SOURCE_PMU,
 124                                              IOMUX_SOURCE_PMU
 125                             ),
 126         PIN_BANK(1, 32, "gpio1"),
 127         PIN_BANK(2, 32, "gpio2"),
 128         PIN_BANK(3, 32, "gpio3"),
 129 };
 130
 131 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
 132         .pin_banks              = rk3368_pin_banks,
 133         .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
 134         .label                  = "RK3368-GPIO",
 135         .type                   = RK3368,
 136         .grf_mux_offset         = 0x0,
 137         .pmu_mux_offset         = 0x0,
 138         .set_mux                = rk3368_set_mux,
 139         .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
 140         .set_drive              = rk3368_set_drive,
 141 };
 142
 143 static const struct udevice_id rk3368_pinctrl_ids[] = {
 144         {
 145                 .compatible = "rockchip,rk3368-pinctrl",
 146                 .data = (ulong)&rk3368_pin_ctrl
 147         },
 148         { }
 149 };
 150
 151 U_BOOT_DRIVER(pinctrl_rk3368) = {
 152         .name           = "rockchip_rk3368_pinctrl",
 153         .id             = UCLASS_PINCTRL,
 154         .of_match       = rk3368_pinctrl_ids,
 155         .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
 156         .ops            = &rockchip_pinctrl_ops,
 157 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 158         .bind           = dm_scan_fdt_dev,
 159 #endif
 160         .probe          = rockchip_pinctrl_probe,
 161 };