drivers/pinctrl/rockchip/pinctrl-rk3368.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/pinctrl.h>
   9 #include <regmap.h>
  10 #include <syscon.h>
  11
  12 #include "pinctrl-rockchip.h"
  13
  14 static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
  15 {
  16         struct rockchip_pinctrl_priv *priv = bank->priv;
  17         int iomux_num = (pin / 8);
  18         struct regmap *regmap;
  19         int reg, ret, mask, mux_type;
  20         u8 bit;
  21         u32 data;
  22
  23         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
  24                                 ? priv->regmap_pmu : priv->regmap_base;
  25
  26         /* get basic quadrupel of mux registers and the correct reg inside */
  27         mux_type = bank->iomux[iomux_num].type;
  28         reg = bank->iomux[iomux_num].offset;
  29         reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
  30
  31         data = (mask << (bit + 16));
  32         data |= (mux & mask) << bit;
  33         ret = regmap_write(regmap, reg, data);
  34
  35         return ret;
  36 }
  37
  38 #define RK3368_PULL_GRF_OFFSET          0x100
  39 #define RK3368_PULL_PMU_OFFSET          0x10
  40
  41 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
  42                                          int pin_num, struct regmap **regmap,
  43                                          int *reg, u8 *bit)
  44 {
  45         struct rockchip_pinctrl_priv *priv = bank->priv;
  46
  47         /* The first 32 pins of the first bank are located in PMU */
  48         if (bank->bank_num == 0) {
  49                 *regmap = priv->regmap_pmu;
  50                 *reg = RK3368_PULL_PMU_OFFSET;
  51         } else {
  52                 *regmap = priv->regmap_base;
  53                 *reg = RK3368_PULL_GRF_OFFSET;
  54
  55                 /* correct the offset, as we're starting with the 2nd bank */
  56                 *reg -= 0x10;
  57                 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
  58         }
  59
  60         *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
  61
  62         *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
  63         *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
  64 }
  65
  66 static int rk3368_set_pull(struct rockchip_pin_bank *bank,
  67                            int pin_num, int pull)
  68 {
  69         struct regmap *regmap;
  70         int reg, ret;
  71         u8 bit, type;
  72         u32 data;
  73
  74         if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
  75                 return -ENOTSUPP;
  76
  77         rk3368_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
  78         type = bank->pull_type[pin_num / 8];
  79         ret = rockchip_translate_pull_value(type, pull);
  80         if (ret < 0) {
  81                 debug("unsupported pull setting %d\n", pull);
  82                 return ret;
  83         }
  84
  85         /* enable the write to the equivalent lower bits */
  86         data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
  87         data |= (ret << bit);
  88         ret = regmap_write(regmap, reg, data);
  89
  90         return ret;
  91 }
  92
  93 #define RK3368_DRV_PMU_OFFSET           0x20
  94 #define RK3368_DRV_GRF_OFFSET           0x200
  95
  96 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
  97                                         int pin_num, struct regmap **regmap,
  98                                         int *reg, u8 *bit)
  99 {
 100         struct rockchip_pinctrl_priv *priv = bank->priv;
 101
 102         /* The first 32 pins of the first bank are located in PMU */
 103         if (bank->bank_num == 0) {
 104                 *regmap = priv->regmap_pmu;
 105                 *reg = RK3368_DRV_PMU_OFFSET;
 106         } else {
 107                 *regmap = priv->regmap_base;
 108                 *reg = RK3368_DRV_GRF_OFFSET;
 109
 110                 /* correct the offset, as we're starting with the 2nd bank */
 111                 *reg -= 0x10;
 112                 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
 113         }
 114
 115         *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
 116         *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
 117         *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
 118 }
 119
 120 static int rk3368_set_drive(struct rockchip_pin_bank *bank,
 121                             int pin_num, int strength)
 122 {
 123         struct regmap *regmap;
 124         int reg, ret;
 125         u32 data;
 126         u8 bit;
 127         int type = bank->drv[pin_num / 8].drv_type;
 128
 129         rk3368_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
 130         ret = rockchip_translate_drive_value(type, strength);
 131         if (ret < 0) {
 132                 debug("unsupported driver strength %d\n", strength);
 133                 return ret;
 134         }
 135
 136         /* enable the write to the equivalent lower bits */
 137         data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
 138         data |= (ret << bit);
 139         ret = regmap_write(regmap, reg, data);
 140
 141         return ret;
 142 }
 143
 144 static struct rockchip_pin_bank rk3368_pin_banks[] = {
 145         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
 146                                              IOMUX_SOURCE_PMU,
 147                                              IOMUX_SOURCE_PMU,
 148                                              IOMUX_SOURCE_PMU
 149                             ),
 150         PIN_BANK(1, 32, "gpio1"),
 151         PIN_BANK(2, 32, "gpio2"),
 152         PIN_BANK(3, 32, "gpio3"),
 153 };
 154
 155 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
 156         .pin_banks              = rk3368_pin_banks,
 157         .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
 158         .grf_mux_offset         = 0x0,
 159         .pmu_mux_offset         = 0x0,
 160         .set_mux                = rk3368_set_mux,
 161         .set_pull               = rk3368_set_pull,
 162         .set_drive              = rk3368_set_drive,
 163 };
 164
 165 static const struct udevice_id rk3368_pinctrl_ids[] = {
 166         {
 167                 .compatible = "rockchip,rk3368-pinctrl",
 168                 .data = (ulong)&rk3368_pin_ctrl
 169         },
 170         { }
 171 };
 172
 173 U_BOOT_DRIVER(pinctrl_rk3368) = {
 174         .name           = "rockchip_rk3368_pinctrl",
 175         .id             = UCLASS_PINCTRL,
 176         .of_match       = rk3368_pinctrl_ids,
 177         .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
 178         .ops            = &rockchip_pinctrl_ops,
 179 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 180         .bind           = dm_scan_fdt_dev,
 181 #endif
 182         .probe          = rockchip_pinctrl_probe,
 183 };