drivers/pinctrl/renesas/pfc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pin Control driver for SuperH Pin Function Controller.
   4  *
   5  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   6  *
   7  * Copyright (C) 2008 Magnus Damm
   8  * Copyright (C) 2009 - 2012 Paul Mundt
   9  * Copyright (C) 2017 Marek Vasut
  10  */
  11
  12 #define DRV_NAME "sh-pfc"
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/pinctrl.h>
  18 #include <linux/io.h>
  19 #include <linux/sizes.h>
  20
  21 #include "sh_pfc.h"
  22
  23 enum sh_pfc_model {
  24         SH_PFC_R8A7790 = 0,
  25         SH_PFC_R8A7791,
  26         SH_PFC_R8A7792,
  27         SH_PFC_R8A7793,
  28         SH_PFC_R8A7794,
  29         SH_PFC_R8A7795,
  30         SH_PFC_R8A7796,
  31         SH_PFC_R8A77965,
  32         SH_PFC_R8A77970,
  33         SH_PFC_R8A77990,
  34         SH_PFC_R8A77995,
  35 };
  36
  37 struct sh_pfc_pin_config {
  38         u32 type;
  39 };
  40
  41 struct sh_pfc_pinctrl {
  42         struct sh_pfc *pfc;
  43
  44         struct sh_pfc_pin_config *configs;
  45
  46         const char *func_prop_name;
  47         const char *groups_prop_name;
  48         const char *pins_prop_name;
  49 };
  50
  51 struct sh_pfc_pin_range {
  52         u16 start;
  53         u16 end;
  54 };
  55
  56 struct sh_pfc_pinctrl_priv {
  57         struct sh_pfc                   pfc;
  58         struct sh_pfc_pinctrl           pmx;
  59 };
  60
  61 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  62 {
  63         unsigned int offset;
  64         unsigned int i;
  65
  66         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  67                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  68
  69                 if (pin <= range->end)
  70                         return pin >= range->start
  71                              ? offset + pin - range->start : -1;
  72
  73                 offset += range->end - range->start + 1;
  74         }
  75
  76         return -EINVAL;
  77 }
  78
  79 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  80 {
  81         if (enum_id < r->begin)
  82                 return 0;
  83
  84         if (enum_id > r->end)
  85                 return 0;
  86
  87         return 1;
  88 }
  89
  90 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  91 {
  92         switch (reg_width) {
  93         case 8:
  94                 return readb(mapped_reg);
  95         case 16:
  96                 return readw(mapped_reg);
  97         case 32:
  98                 return readl(mapped_reg);
  99         }
 100
 101         BUG();
 102         return 0;
 103 }
 104
 105 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 106                           u32 data)
 107 {
 108         switch (reg_width) {
 109         case 8:
 110                 writeb(data, mapped_reg);
 111                 return;
 112         case 16:
 113                 writew(data, mapped_reg);
 114                 return;
 115         case 32:
 116                 writel(data, mapped_reg);
 117                 return;
 118         }
 119
 120         BUG();
 121 }
 122
 123 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
 124 {
 125         return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
 126 }
 127
 128 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
 129 {
 130         void __iomem *unlock_reg =
 131                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 132
 133         if (pfc->info->unlock_reg)
 134                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 135
 136         sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
 137 }
 138
 139 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 140                                      const struct pinmux_cfg_reg *crp,
 141                                      unsigned int in_pos,
 142                                      void __iomem **mapped_regp, u32 *maskp,
 143                                      unsigned int *posp)
 144 {
 145         unsigned int k;
 146
 147         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 148
 149         if (crp->field_width) {
 150                 *maskp = (1 << crp->field_width) - 1;
 151                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 152         } else {
 153                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 154                 *posp = crp->reg_width;
 155                 for (k = 0; k <= in_pos; k++)
 156                         *posp -= crp->var_field_width[k];
 157         }
 158 }
 159
 160 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 161                                     const struct pinmux_cfg_reg *crp,
 162                                     unsigned int field, u32 value)
 163 {
 164         void __iomem *mapped_reg;
 165         void __iomem *unlock_reg =
 166                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 167         unsigned int pos;
 168         u32 mask, data;
 169
 170         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 171
 172         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 173                 "r_width = %u, f_width = %u\n",
 174                 crp->reg, value, field, crp->reg_width, crp->field_width);
 175
 176         mask = ~(mask << pos);
 177         value = value << pos;
 178
 179         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 180         data &= mask;
 181         data |= value;
 182
 183         if (pfc->info->unlock_reg)
 184                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 185
 186         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 187 }
 188
 189 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 190                                  const struct pinmux_cfg_reg **crp,
 191                                  unsigned int *fieldp, u32 *valuep)
 192 {
 193         unsigned int k = 0;
 194
 195         while (1) {
 196                 const struct pinmux_cfg_reg *config_reg =
 197                         pfc->info->cfg_regs + k;
 198                 unsigned int r_width = config_reg->reg_width;
 199                 unsigned int f_width = config_reg->field_width;
 200                 unsigned int curr_width;
 201                 unsigned int bit_pos;
 202                 unsigned int pos = 0;
 203                 unsigned int m = 0;
 204
 205                 if (!r_width)
 206                         break;
 207
 208                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 209                         u32 ncomb;
 210                         u32 n;
 211
 212                         if (f_width)
 213                                 curr_width = f_width;
 214                         else
 215                                 curr_width = config_reg->var_field_width[m];
 216
 217                         ncomb = 1 << curr_width;
 218                         for (n = 0; n < ncomb; n++) {
 219                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 220                                         *crp = config_reg;
 221                                         *fieldp = m;
 222                                         *valuep = n;
 223                                         return 0;
 224                                 }
 225                         }
 226                         pos += ncomb;
 227                         m++;
 228                 }
 229                 k++;
 230         }
 231
 232         return -EINVAL;
 233 }
 234
 235 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 236                               u16 *enum_idp)
 237 {
 238         const u16 *data = pfc->info->pinmux_data;
 239         unsigned int k;
 240
 241         if (pos) {
 242                 *enum_idp = data[pos + 1];
 243                 return pos + 1;
 244         }
 245
 246         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 247                 if (data[k] == mark) {
 248                         *enum_idp = data[k + 1];
 249                         return k + 1;
 250                 }
 251         }
 252
 253         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 254                 mark);
 255         return -EINVAL;
 256 }
 257
 258 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 259 {
 260         const struct pinmux_range *range;
 261         int pos = 0;
 262
 263         switch (pinmux_type) {
 264         case PINMUX_TYPE_GPIO:
 265         case PINMUX_TYPE_FUNCTION:
 266                 range = NULL;
 267                 break;
 268
 269         case PINMUX_TYPE_OUTPUT:
 270                 range = &pfc->info->output;
 271                 break;
 272
 273         case PINMUX_TYPE_INPUT:
 274                 range = &pfc->info->input;
 275                 break;
 276
 277         default:
 278                 return -EINVAL;
 279         }
 280
 281         /* Iterate over all the configuration fields we need to update. */
 282         while (1) {
 283                 const struct pinmux_cfg_reg *cr;
 284                 unsigned int field;
 285                 u16 enum_id;
 286                 u32 value;
 287                 int in_range;
 288                 int ret;
 289
 290                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 291                 if (pos < 0)
 292                         return pos;
 293
 294                 if (!enum_id)
 295                         break;
 296
 297                 /* Check if the configuration field selects a function. If it
 298                  * doesn't, skip the field if it's not applicable to the
 299                  * requested pinmux type.
 300                  */
 301                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 302                 if (!in_range) {
 303                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 304                                 /* Functions are allowed to modify all
 305                                  * fields.
 306                                  */
 307                                 in_range = 1;
 308                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 309                                 /* Input/output types can only modify fields
 310                                  * that correspond to their respective ranges.
 311                                  */
 312                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 313
 314                                 /*
 315                                  * special case pass through for fixed
 316                                  * input-only or output-only pins without
 317                                  * function enum register association.
 318                                  */
 319                                 if (in_range && enum_id == range->force)
 320                                         continue;
 321                         }
 322                         /* GPIOs are only allowed to modify function fields. */
 323                 }
 324
 325                 if (!in_range)
 326                         continue;
 327
 328                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 329                 if (ret < 0)
 330                         return ret;
 331
 332                 sh_pfc_write_config_reg(pfc, cr, field, value);
 333         }
 334
 335         return 0;
 336 }
 337
 338 const struct pinmux_bias_reg *
 339 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
 340                        unsigned int *bit)
 341 {
 342         unsigned int i, j;
 343
 344         for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 345                 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
 346                         if (pfc->info->bias_regs[i].pins[j] == pin) {
 347                                 *bit = j;
 348                                 return &pfc->info->bias_regs[i];
 349                         }
 350                 }
 351         }
 352
 353         WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
 354
 355         return NULL;
 356 }
 357
 358 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 359 {
 360         struct sh_pfc_pin_range *range;
 361         unsigned int nr_ranges;
 362         unsigned int i;
 363
 364         if (pfc->info->pins[0].pin == (u16)-1) {
 365                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 366                  * in its pin arrays yet. Consider the pin numbers range as
 367                  * continuous and allocate a single range.
 368                  */
 369                 pfc->nr_ranges = 1;
 370                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 371                 if (pfc->ranges == NULL)
 372                         return -ENOMEM;
 373
 374                 pfc->ranges->start = 0;
 375                 pfc->ranges->end = pfc->info->nr_pins - 1;
 376                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 377
 378                 return 0;
 379         }
 380
 381         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 382          * be sorted by pin numbers, and pins without a GPIO port must come
 383          * last.
 384          */
 385         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 386                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 387                         nr_ranges++;
 388         }
 389
 390         pfc->nr_ranges = nr_ranges;
 391         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 392         if (pfc->ranges == NULL)
 393                 return -ENOMEM;
 394
 395         range = pfc->ranges;
 396         range->start = pfc->info->pins[0].pin;
 397
 398         for (i = 1; i < pfc->info->nr_pins; ++i) {
 399                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 400                         continue;
 401
 402                 range->end = pfc->info->pins[i-1].pin;
 403                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 404                         pfc->nr_gpio_pins = range->end + 1;
 405
 406                 range++;
 407                 range->start = pfc->info->pins[i].pin;
 408         }
 409
 410         range->end = pfc->info->pins[i-1].pin;
 411         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 412                 pfc->nr_gpio_pins = range->end + 1;
 413
 414         return 0;
 415 }
 416
 417 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 418 {
 419         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 420
 421         return priv->pfc.info->nr_pins;
 422 }
 423
 424 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 425                                                   unsigned selector)
 426 {
 427         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 428
 429         return priv->pfc.info->pins[selector].name;
 430 }
 431
 432 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 433 {
 434         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 435
 436         return priv->pfc.info->nr_groups;
 437 }
 438
 439 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 440                                                   unsigned selector)
 441 {
 442         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 443
 444         return priv->pfc.info->groups[selector].name;
 445 }
 446
 447 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 448 {
 449         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 450
 451         return priv->pfc.info->nr_functions;
 452 }
 453
 454 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 455                                                   unsigned selector)
 456 {
 457         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 458
 459         return priv->pfc.info->functions[selector].name;
 460 }
 461
 462 static int sh_pfc_gpio_request_enable(struct udevice *dev,
 463                                       unsigned pin_selector)
 464 {
 465         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 466         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 467         struct sh_pfc *pfc = &priv->pfc;
 468         struct sh_pfc_pin_config *cfg;
 469         const struct sh_pfc_pin *pin = NULL;
 470         int i, ret, idx;
 471
 472         for (i = 0; i < pfc->info->nr_pins; i++) {
 473                 if (priv->pfc.info->pins[i].pin != pin_selector)
 474                         continue;
 475
 476                 pin = &priv->pfc.info->pins[i];
 477                 break;
 478         }
 479
 480         if (!pin)
 481                 return -EINVAL;
 482
 483         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 484         cfg = &pmx->configs[idx];
 485
 486         if (cfg->type != PINMUX_TYPE_NONE)
 487                 return -EBUSY;
 488
 489         ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 490         if (ret)
 491                 return ret;
 492
 493         cfg->type = PINMUX_TYPE_GPIO;
 494
 495         return 0;
 496 }
 497
 498 static int sh_pfc_gpio_disable_free(struct udevice *dev,
 499                                     unsigned pin_selector)
 500 {
 501         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 502         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 503         struct sh_pfc *pfc = &priv->pfc;
 504         struct sh_pfc_pin_config *cfg;
 505         const struct sh_pfc_pin *pin = NULL;
 506         int i, idx;
 507
 508         for (i = 0; i < pfc->info->nr_pins; i++) {
 509                 if (priv->pfc.info->pins[i].pin != pin_selector)
 510                         continue;
 511
 512                 pin = &priv->pfc.info->pins[i];
 513                 break;
 514         }
 515
 516         if (!pin)
 517                 return -EINVAL;
 518
 519         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 520         cfg = &pmx->configs[idx];
 521
 522         cfg->type = PINMUX_TYPE_NONE;
 523
 524         return 0;
 525 }
 526
 527 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 528                                   unsigned func_selector)
 529 {
 530         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 531         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 532         struct sh_pfc *pfc = &priv->pfc;
 533         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 534         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 535         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 536
 537         if (cfg->type != PINMUX_TYPE_NONE)
 538                 return -EBUSY;
 539
 540         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 541 }
 542
 543 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 544                                      unsigned func_selector)
 545 {
 546         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 547         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 548         struct sh_pfc *pfc = &priv->pfc;
 549         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 550         unsigned int i;
 551         int ret = 0;
 552
 553         for (i = 0; i < grp->nr_pins; ++i) {
 554                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 555                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 556
 557                 if (cfg->type != PINMUX_TYPE_NONE) {
 558                         ret = -EBUSY;
 559                         goto done;
 560                 }
 561         }
 562
 563         for (i = 0; i < grp->nr_pins; ++i) {
 564                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 565                 if (ret < 0)
 566                         break;
 567         }
 568
 569 done:
 570         return ret;
 571 }
 572 #if CONFIG_IS_ENABLED(PINCONF)
 573 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 574         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 575         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 576         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 577         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 578         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 579 };
 580
 581 static void __iomem *
 582 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 583                                        unsigned int *offset, unsigned int *size)
 584 {
 585         const struct pinmux_drive_reg_field *field;
 586         const struct pinmux_drive_reg *reg;
 587         unsigned int i;
 588
 589         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 590                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 591                         field = &reg->fields[i];
 592
 593                         if (field->size && field->pin == pin) {
 594                                 *offset = field->offset;
 595                                 *size = field->size;
 596
 597                                 return (void __iomem *)(uintptr_t)reg->reg;
 598                         }
 599                 }
 600         }
 601
 602         return NULL;
 603 }
 604
 605 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 606                                              unsigned int pin, u16 strength)
 607 {
 608         unsigned int offset;
 609         unsigned int size;
 610         unsigned int step;
 611         void __iomem *reg;
 612         void __iomem *unlock_reg =
 613                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 614         u32 val;
 615
 616         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 617         if (!reg)
 618                 return -EINVAL;
 619
 620         step = size == 2 ? 6 : 3;
 621
 622         if (strength < step || strength > 24)
 623                 return -EINVAL;
 624
 625         /* Convert the value from mA based on a full drive strength value of
 626          * 24mA. We can make the full value configurable later if needed.
 627          */
 628         strength = strength / step - 1;
 629
 630         val = sh_pfc_read_raw_reg(reg, 32);
 631         val &= ~GENMASK(offset + 4 - 1, offset);
 632         val |= strength << offset;
 633
 634         if (unlock_reg)
 635                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 636
 637         sh_pfc_write_raw_reg(reg, 32, val);
 638
 639         return 0;
 640 }
 641
 642 /* Check whether the requested parameter is supported for a pin. */
 643 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 644                                     unsigned int param)
 645 {
 646         int idx = sh_pfc_get_pin_index(pfc, _pin);
 647         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 648
 649         switch (param) {
 650         case PIN_CONFIG_BIAS_DISABLE:
 651                 return pin->configs &
 652                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 653
 654         case PIN_CONFIG_BIAS_PULL_UP:
 655                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 656
 657         case PIN_CONFIG_BIAS_PULL_DOWN:
 658                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 659
 660         case PIN_CONFIG_DRIVE_STRENGTH:
 661                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 662
 663         case PIN_CONFIG_POWER_SOURCE:
 664                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 665
 666         default:
 667                 return false;
 668         }
 669 }
 670
 671 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 672                               unsigned int param, unsigned int arg)
 673 {
 674         struct sh_pfc *pfc = pmx->pfc;
 675         void __iomem *pocctrl;
 676         void __iomem *unlock_reg =
 677                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 678         u32 addr, val;
 679         int bit, ret;
 680
 681         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 682                 return -ENOTSUPP;
 683
 684         switch (param) {
 685         case PIN_CONFIG_BIAS_PULL_UP:
 686         case PIN_CONFIG_BIAS_PULL_DOWN:
 687         case PIN_CONFIG_BIAS_DISABLE:
 688                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 689                         return -ENOTSUPP;
 690
 691                 pfc->info->ops->set_bias(pfc, _pin, param);
 692
 693                 break;
 694
 695         case PIN_CONFIG_DRIVE_STRENGTH:
 696                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 697                 if (ret < 0)
 698                         return ret;
 699
 700                 break;
 701
 702         case PIN_CONFIG_POWER_SOURCE:
 703                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 704                         return -ENOTSUPP;
 705
 706                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 707                 if (bit < 0) {
 708                         printf("invalid pin %#x", _pin);
 709                         return bit;
 710                 }
 711
 712                 if (arg != 1800 && arg != 3300)
 713                         return -EINVAL;
 714
 715                 pocctrl = (void __iomem *)(uintptr_t)addr;
 716
 717                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 718                 if (arg == 3300)
 719                         val |= BIT(bit);
 720                 else
 721                         val &= ~BIT(bit);
 722
 723                 if (unlock_reg)
 724                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 725
 726                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 727
 728                 break;
 729
 730         default:
 731                 return -ENOTSUPP;
 732         }
 733
 734         return 0;
 735 }
 736
 737 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 738                                   unsigned int pin_selector,
 739                                   unsigned int param, unsigned int arg)
 740 {
 741         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 742         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 743         struct sh_pfc *pfc = &priv->pfc;
 744         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 745
 746         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 747
 748         return 0;
 749 }
 750
 751 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 752                                       unsigned int group_selector,
 753                                       unsigned int param, unsigned int arg)
 754 {
 755         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 756         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 757         struct sh_pfc *pfc = &priv->pfc;
 758         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 759         unsigned int i;
 760
 761         for (i = 0; i < grp->nr_pins; i++)
 762                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 763
 764         return 0;
 765 }
 766 #endif
 767
 768 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 769         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 770         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 771         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 772         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 773         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 774         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 775
 776 #if CONFIG_IS_ENABLED(PINCONF)
 777         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 778         .pinconf_params         = sh_pfc_pinconf_params,
 779         .pinconf_set            = sh_pfc_pinconf_pin_set,
 780         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 781 #endif
 782         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 783         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 784         .set_state              = pinctrl_generic_set_state,
 785
 786         .gpio_request_enable    = sh_pfc_gpio_request_enable,
 787         .gpio_disable_free      = sh_pfc_gpio_disable_free,
 788 };
 789
 790 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 791 {
 792         unsigned int i;
 793
 794         /* Allocate and initialize the pins and configs arrays. */
 795         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 796                                     GFP_KERNEL);
 797         if (unlikely(!pmx->configs))
 798                 return -ENOMEM;
 799
 800         for (i = 0; i < pfc->info->nr_pins; ++i) {
 801                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 802                 cfg->type = PINMUX_TYPE_NONE;
 803         }
 804
 805         return 0;
 806 }
 807
 808
 809 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 810 {
 811         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 812         enum sh_pfc_model model = dev_get_driver_data(dev);
 813         fdt_addr_t base;
 814
 815         base = devfdt_get_addr(dev);
 816         if (base == FDT_ADDR_T_NONE)
 817                 return -EINVAL;
 818
 819         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 820         if (!priv->pfc.regs)
 821                 return -ENOMEM;
 822
 823 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 824         if (model == SH_PFC_R8A7790)
 825                 priv->pfc.info = &r8a7790_pinmux_info;
 826 #endif
 827 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 828         if (model == SH_PFC_R8A7791)
 829                 priv->pfc.info = &r8a7791_pinmux_info;
 830 #endif
 831 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 832         if (model == SH_PFC_R8A7792)
 833                 priv->pfc.info = &r8a7792_pinmux_info;
 834 #endif
 835 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 836         if (model == SH_PFC_R8A7793)
 837                 priv->pfc.info = &r8a7793_pinmux_info;
 838 #endif
 839 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 840         if (model == SH_PFC_R8A7794)
 841                 priv->pfc.info = &r8a7794_pinmux_info;
 842 #endif
 843 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 844         if (model == SH_PFC_R8A7795)
 845                 priv->pfc.info = &r8a7795_pinmux_info;
 846 #endif
 847 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 848         if (model == SH_PFC_R8A7796)
 849                 priv->pfc.info = &r8a7796_pinmux_info;
 850 #endif
 851 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 852         if (model == SH_PFC_R8A77965)
 853                 priv->pfc.info = &r8a77965_pinmux_info;
 854 #endif
 855 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 856         if (model == SH_PFC_R8A77970)
 857                 priv->pfc.info = &r8a77970_pinmux_info;
 858 #endif
 859 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 860         if (model == SH_PFC_R8A77990)
 861                 priv->pfc.info = &r8a77990_pinmux_info;
 862 #endif
 863 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 864         if (model == SH_PFC_R8A77995)
 865                 priv->pfc.info = &r8a77995_pinmux_info;
 866 #endif
 867
 868         priv->pmx.pfc = &priv->pfc;
 869         sh_pfc_init_ranges(&priv->pfc);
 870         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 871
 872         return 0;
 873 }
 874
 875 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 876 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 877         {
 878                 .compatible = "renesas,pfc-r8a7790",
 879                 .data = SH_PFC_R8A7790,
 880         },
 881 #endif
 882 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 883         {
 884                 .compatible = "renesas,pfc-r8a7791",
 885                 .data = SH_PFC_R8A7791,
 886         },
 887 #endif
 888 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 889         {
 890                 .compatible = "renesas,pfc-r8a7792",
 891                 .data = SH_PFC_R8A7792,
 892         },
 893 #endif
 894 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 895         {
 896                 .compatible = "renesas,pfc-r8a7793",
 897                 .data = SH_PFC_R8A7793,
 898         },
 899 #endif
 900 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 901         {
 902                 .compatible = "renesas,pfc-r8a7794",
 903                 .data = SH_PFC_R8A7794,
 904         },
 905 #endif
 906 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 907         {
 908                 .compatible = "renesas,pfc-r8a7795",
 909                 .data = SH_PFC_R8A7795,
 910         },
 911 #endif
 912 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 913         {
 914                 .compatible = "renesas,pfc-r8a7796",
 915                 .data = SH_PFC_R8A7796,
 916         },
 917 #endif
 918 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 919         {
 920                 .compatible = "renesas,pfc-r8a77965",
 921                 .data = SH_PFC_R8A77965,
 922         },
 923 #endif
 924 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 925         {
 926                 .compatible = "renesas,pfc-r8a77970",
 927                 .data = SH_PFC_R8A77970,
 928         },
 929 #endif
 930 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 931         {
 932                 .compatible = "renesas,pfc-r8a77990",
 933                 .data = SH_PFC_R8A77990,
 934         },
 935 #endif
 936 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 937         {
 938                 .compatible = "renesas,pfc-r8a77995",
 939                 .data = SH_PFC_R8A77995,
 940         },
 941 #endif
 942         { },
 943 };
 944
 945 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 946         .name           = "sh_pfc_pinctrl",
 947         .id             = UCLASS_PINCTRL,
 948         .of_match       = sh_pfc_pinctrl_ids,
 949         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 950         .ops            = &sh_pfc_pinctrl_ops,
 951         .probe          = sh_pfc_pinctrl_probe,
 952 };