drivers/pinctrl/renesas/pfc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pin Control driver for SuperH Pin Function Controller.
   4  *
   5  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   6  *
   7  * Copyright (C) 2008 Magnus Damm
   8  * Copyright (C) 2009 - 2012 Paul Mundt
   9  * Copyright (C) 2017 Marek Vasut
  10  */
  11
  12 #define DRV_NAME "sh-pfc"
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/device_compat.h>
  18 #include <dm/devres.h>
  19 #include <dm/pinctrl.h>
  20 #include <linux/io.h>
  21 #include <linux/sizes.h>
  22
  23 #include "sh_pfc.h"
  24
  25 enum sh_pfc_model {
  26         SH_PFC_R8A7790 = 0,
  27         SH_PFC_R8A7791,
  28         SH_PFC_R8A7792,
  29         SH_PFC_R8A7793,
  30         SH_PFC_R8A7794,
  31         SH_PFC_R8A7795,
  32         SH_PFC_R8A7796,
  33         SH_PFC_R8A77965,
  34         SH_PFC_R8A77970,
  35         SH_PFC_R8A77980,
  36         SH_PFC_R8A77990,
  37         SH_PFC_R8A77995,
  38 };
  39
  40 struct sh_pfc_pin_config {
  41         u32 type;
  42 };
  43
  44 struct sh_pfc_pinctrl {
  45         struct sh_pfc *pfc;
  46
  47         struct sh_pfc_pin_config *configs;
  48
  49         const char *func_prop_name;
  50         const char *groups_prop_name;
  51         const char *pins_prop_name;
  52 };
  53
  54 struct sh_pfc_pin_range {
  55         u16 start;
  56         u16 end;
  57 };
  58
  59 struct sh_pfc_pinctrl_priv {
  60         struct sh_pfc                   pfc;
  61         struct sh_pfc_pinctrl           pmx;
  62 };
  63
  64 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  65 {
  66         unsigned int offset;
  67         unsigned int i;
  68
  69         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  70                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  71
  72                 if (pin <= range->end)
  73                         return pin >= range->start
  74                              ? offset + pin - range->start : -1;
  75
  76                 offset += range->end - range->start + 1;
  77         }
  78
  79         return -EINVAL;
  80 }
  81
  82 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  83 {
  84         if (enum_id < r->begin)
  85                 return 0;
  86
  87         if (enum_id > r->end)
  88                 return 0;
  89
  90         return 1;
  91 }
  92
  93 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  94 {
  95         switch (reg_width) {
  96         case 8:
  97                 return readb(mapped_reg);
  98         case 16:
  99                 return readw(mapped_reg);
 100         case 32:
 101                 return readl(mapped_reg);
 102         }
 103
 104         BUG();
 105         return 0;
 106 }
 107
 108 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 109                           u32 data)
 110 {
 111         switch (reg_width) {
 112         case 8:
 113                 writeb(data, mapped_reg);
 114                 return;
 115         case 16:
 116                 writew(data, mapped_reg);
 117                 return;
 118         case 32:
 119                 writel(data, mapped_reg);
 120                 return;
 121         }
 122
 123         BUG();
 124 }
 125
 126 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
 127 {
 128         return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
 129 }
 130
 131 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
 132 {
 133         void __iomem *unlock_reg =
 134                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 135
 136         if (pfc->info->unlock_reg)
 137                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 138
 139         sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
 140 }
 141
 142 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 143                                      const struct pinmux_cfg_reg *crp,
 144                                      unsigned int in_pos,
 145                                      void __iomem **mapped_regp, u32 *maskp,
 146                                      unsigned int *posp)
 147 {
 148         unsigned int k;
 149
 150         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 151
 152         if (crp->field_width) {
 153                 *maskp = (1 << crp->field_width) - 1;
 154                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 155         } else {
 156                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 157                 *posp = crp->reg_width;
 158                 for (k = 0; k <= in_pos; k++)
 159                         *posp -= crp->var_field_width[k];
 160         }
 161 }
 162
 163 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 164                                     const struct pinmux_cfg_reg *crp,
 165                                     unsigned int field, u32 value)
 166 {
 167         void __iomem *mapped_reg;
 168         void __iomem *unlock_reg =
 169                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 170         unsigned int pos;
 171         u32 mask, data;
 172
 173         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 174
 175         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 176                 "r_width = %u, f_width = %u\n",
 177                 crp->reg, value, field, crp->reg_width, crp->field_width);
 178
 179         mask = ~(mask << pos);
 180         value = value << pos;
 181
 182         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 183         data &= mask;
 184         data |= value;
 185
 186         if (pfc->info->unlock_reg)
 187                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 188
 189         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 190 }
 191
 192 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 193                                  const struct pinmux_cfg_reg **crp,
 194                                  unsigned int *fieldp, u32 *valuep)
 195 {
 196         unsigned int k = 0;
 197
 198         while (1) {
 199                 const struct pinmux_cfg_reg *config_reg =
 200                         pfc->info->cfg_regs + k;
 201                 unsigned int r_width = config_reg->reg_width;
 202                 unsigned int f_width = config_reg->field_width;
 203                 unsigned int curr_width;
 204                 unsigned int bit_pos;
 205                 unsigned int pos = 0;
 206                 unsigned int m = 0;
 207
 208                 if (!r_width)
 209                         break;
 210
 211                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 212                         u32 ncomb;
 213                         u32 n;
 214
 215                         if (f_width)
 216                                 curr_width = f_width;
 217                         else
 218                                 curr_width = config_reg->var_field_width[m];
 219
 220                         ncomb = 1 << curr_width;
 221                         for (n = 0; n < ncomb; n++) {
 222                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 223                                         *crp = config_reg;
 224                                         *fieldp = m;
 225                                         *valuep = n;
 226                                         return 0;
 227                                 }
 228                         }
 229                         pos += ncomb;
 230                         m++;
 231                 }
 232                 k++;
 233         }
 234
 235         return -EINVAL;
 236 }
 237
 238 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 239                               u16 *enum_idp)
 240 {
 241         const u16 *data = pfc->info->pinmux_data;
 242         unsigned int k;
 243
 244         if (pos) {
 245                 *enum_idp = data[pos + 1];
 246                 return pos + 1;
 247         }
 248
 249         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 250                 if (data[k] == mark) {
 251                         *enum_idp = data[k + 1];
 252                         return k + 1;
 253                 }
 254         }
 255
 256         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 257                 mark);
 258         return -EINVAL;
 259 }
 260
 261 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 262 {
 263         const struct pinmux_range *range;
 264         int pos = 0;
 265
 266         switch (pinmux_type) {
 267         case PINMUX_TYPE_GPIO:
 268         case PINMUX_TYPE_FUNCTION:
 269                 range = NULL;
 270                 break;
 271
 272         case PINMUX_TYPE_OUTPUT:
 273                 range = &pfc->info->output;
 274                 break;
 275
 276         case PINMUX_TYPE_INPUT:
 277                 range = &pfc->info->input;
 278                 break;
 279
 280         default:
 281                 return -EINVAL;
 282         }
 283
 284         /* Iterate over all the configuration fields we need to update. */
 285         while (1) {
 286                 const struct pinmux_cfg_reg *cr;
 287                 unsigned int field;
 288                 u16 enum_id;
 289                 u32 value;
 290                 int in_range;
 291                 int ret;
 292
 293                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 294                 if (pos < 0)
 295                         return pos;
 296
 297                 if (!enum_id)
 298                         break;
 299
 300                 /* Check if the configuration field selects a function. If it
 301                  * doesn't, skip the field if it's not applicable to the
 302                  * requested pinmux type.
 303                  */
 304                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 305                 if (!in_range) {
 306                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 307                                 /* Functions are allowed to modify all
 308                                  * fields.
 309                                  */
 310                                 in_range = 1;
 311                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 312                                 /* Input/output types can only modify fields
 313                                  * that correspond to their respective ranges.
 314                                  */
 315                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 316
 317                                 /*
 318                                  * special case pass through for fixed
 319                                  * input-only or output-only pins without
 320                                  * function enum register association.
 321                                  */
 322                                 if (in_range && enum_id == range->force)
 323                                         continue;
 324                         }
 325                         /* GPIOs are only allowed to modify function fields. */
 326                 }
 327
 328                 if (!in_range)
 329                         continue;
 330
 331                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 332                 if (ret < 0)
 333                         return ret;
 334
 335                 sh_pfc_write_config_reg(pfc, cr, field, value);
 336         }
 337
 338         return 0;
 339 }
 340
 341 const struct pinmux_bias_reg *
 342 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
 343                        unsigned int *bit)
 344 {
 345         unsigned int i, j;
 346
 347         for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 348                 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
 349                         if (pfc->info->bias_regs[i].pins[j] == pin) {
 350                                 *bit = j;
 351                                 return &pfc->info->bias_regs[i];
 352                         }
 353                 }
 354         }
 355
 356         WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
 357
 358         return NULL;
 359 }
 360
 361 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 362 {
 363         struct sh_pfc_pin_range *range;
 364         unsigned int nr_ranges;
 365         unsigned int i;
 366
 367         if (pfc->info->pins[0].pin == (u16)-1) {
 368                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 369                  * in its pin arrays yet. Consider the pin numbers range as
 370                  * continuous and allocate a single range.
 371                  */
 372                 pfc->nr_ranges = 1;
 373                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 374                 if (pfc->ranges == NULL)
 375                         return -ENOMEM;
 376
 377                 pfc->ranges->start = 0;
 378                 pfc->ranges->end = pfc->info->nr_pins - 1;
 379                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 380
 381                 return 0;
 382         }
 383
 384         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 385          * be sorted by pin numbers, and pins without a GPIO port must come
 386          * last.
 387          */
 388         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 389                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 390                         nr_ranges++;
 391         }
 392
 393         pfc->nr_ranges = nr_ranges;
 394         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 395         if (pfc->ranges == NULL)
 396                 return -ENOMEM;
 397
 398         range = pfc->ranges;
 399         range->start = pfc->info->pins[0].pin;
 400
 401         for (i = 1; i < pfc->info->nr_pins; ++i) {
 402                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 403                         continue;
 404
 405                 range->end = pfc->info->pins[i-1].pin;
 406                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 407                         pfc->nr_gpio_pins = range->end + 1;
 408
 409                 range++;
 410                 range->start = pfc->info->pins[i].pin;
 411         }
 412
 413         range->end = pfc->info->pins[i-1].pin;
 414         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 415                 pfc->nr_gpio_pins = range->end + 1;
 416
 417         return 0;
 418 }
 419
 420 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 421 {
 422         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 423
 424         return priv->pfc.info->nr_pins;
 425 }
 426
 427 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 428                                                   unsigned selector)
 429 {
 430         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 431
 432         return priv->pfc.info->pins[selector].name;
 433 }
 434
 435 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 436 {
 437         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 438
 439         return priv->pfc.info->nr_groups;
 440 }
 441
 442 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 443                                                   unsigned selector)
 444 {
 445         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 446
 447         return priv->pfc.info->groups[selector].name;
 448 }
 449
 450 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 451 {
 452         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 453
 454         return priv->pfc.info->nr_functions;
 455 }
 456
 457 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 458                                                   unsigned selector)
 459 {
 460         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 461
 462         return priv->pfc.info->functions[selector].name;
 463 }
 464
 465 static int sh_pfc_gpio_request_enable(struct udevice *dev,
 466                                       unsigned pin_selector)
 467 {
 468         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 469         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 470         struct sh_pfc *pfc = &priv->pfc;
 471         struct sh_pfc_pin_config *cfg;
 472         const struct sh_pfc_pin *pin = NULL;
 473         int i, ret, idx;
 474
 475         for (i = 0; i < pfc->info->nr_pins; i++) {
 476                 if (priv->pfc.info->pins[i].pin != pin_selector)
 477                         continue;
 478
 479                 pin = &priv->pfc.info->pins[i];
 480                 break;
 481         }
 482
 483         if (!pin)
 484                 return -EINVAL;
 485
 486         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 487         cfg = &pmx->configs[idx];
 488
 489         if (cfg->type != PINMUX_TYPE_NONE)
 490                 return -EBUSY;
 491
 492         ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 493         if (ret)
 494                 return ret;
 495
 496         cfg->type = PINMUX_TYPE_GPIO;
 497
 498         return 0;
 499 }
 500
 501 static int sh_pfc_gpio_disable_free(struct udevice *dev,
 502                                     unsigned pin_selector)
 503 {
 504         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 505         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 506         struct sh_pfc *pfc = &priv->pfc;
 507         struct sh_pfc_pin_config *cfg;
 508         const struct sh_pfc_pin *pin = NULL;
 509         int i, idx;
 510
 511         for (i = 0; i < pfc->info->nr_pins; i++) {
 512                 if (priv->pfc.info->pins[i].pin != pin_selector)
 513                         continue;
 514
 515                 pin = &priv->pfc.info->pins[i];
 516                 break;
 517         }
 518
 519         if (!pin)
 520                 return -EINVAL;
 521
 522         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 523         cfg = &pmx->configs[idx];
 524
 525         cfg->type = PINMUX_TYPE_NONE;
 526
 527         return 0;
 528 }
 529
 530 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 531                                   unsigned func_selector)
 532 {
 533         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 534         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 535         struct sh_pfc *pfc = &priv->pfc;
 536         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 537         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 538         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 539
 540         if (cfg->type != PINMUX_TYPE_NONE)
 541                 return -EBUSY;
 542
 543         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 544 }
 545
 546 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 547                                      unsigned func_selector)
 548 {
 549         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 550         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 551         struct sh_pfc *pfc = &priv->pfc;
 552         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 553         unsigned int i;
 554         int ret = 0;
 555
 556         for (i = 0; i < grp->nr_pins; ++i) {
 557                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 558                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 559
 560                 if (cfg->type != PINMUX_TYPE_NONE) {
 561                         ret = -EBUSY;
 562                         goto done;
 563                 }
 564         }
 565
 566         for (i = 0; i < grp->nr_pins; ++i) {
 567                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 568                 if (ret < 0)
 569                         break;
 570         }
 571
 572 done:
 573         return ret;
 574 }
 575 #if CONFIG_IS_ENABLED(PINCONF)
 576 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 577         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 578         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 579         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 580         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 581         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 582 };
 583
 584 static void __iomem *
 585 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 586                                        unsigned int *offset, unsigned int *size)
 587 {
 588         const struct pinmux_drive_reg_field *field;
 589         const struct pinmux_drive_reg *reg;
 590         unsigned int i;
 591
 592         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 593                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 594                         field = &reg->fields[i];
 595
 596                         if (field->size && field->pin == pin) {
 597                                 *offset = field->offset;
 598                                 *size = field->size;
 599
 600                                 return (void __iomem *)(uintptr_t)reg->reg;
 601                         }
 602                 }
 603         }
 604
 605         return NULL;
 606 }
 607
 608 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 609                                              unsigned int pin, u16 strength)
 610 {
 611         unsigned int offset;
 612         unsigned int size;
 613         unsigned int step;
 614         void __iomem *reg;
 615         void __iomem *unlock_reg =
 616                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 617         u32 val;
 618
 619         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 620         if (!reg)
 621                 return -EINVAL;
 622
 623         step = size == 2 ? 6 : 3;
 624
 625         if (strength < step || strength > 24)
 626                 return -EINVAL;
 627
 628         /* Convert the value from mA based on a full drive strength value of
 629          * 24mA. We can make the full value configurable later if needed.
 630          */
 631         strength = strength / step - 1;
 632
 633         val = sh_pfc_read_raw_reg(reg, 32);
 634         val &= ~GENMASK(offset + 4 - 1, offset);
 635         val |= strength << offset;
 636
 637         if (unlock_reg)
 638                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 639
 640         sh_pfc_write_raw_reg(reg, 32, val);
 641
 642         return 0;
 643 }
 644
 645 /* Check whether the requested parameter is supported for a pin. */
 646 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 647                                     unsigned int param)
 648 {
 649         int idx = sh_pfc_get_pin_index(pfc, _pin);
 650         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 651
 652         switch (param) {
 653         case PIN_CONFIG_BIAS_DISABLE:
 654                 return pin->configs &
 655                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 656
 657         case PIN_CONFIG_BIAS_PULL_UP:
 658                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 659
 660         case PIN_CONFIG_BIAS_PULL_DOWN:
 661                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 662
 663         case PIN_CONFIG_DRIVE_STRENGTH:
 664                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 665
 666         case PIN_CONFIG_POWER_SOURCE:
 667                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 668
 669         default:
 670                 return false;
 671         }
 672 }
 673
 674 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 675                               unsigned int param, unsigned int arg)
 676 {
 677         struct sh_pfc *pfc = pmx->pfc;
 678         void __iomem *pocctrl;
 679         void __iomem *unlock_reg =
 680                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 681         u32 addr, val;
 682         int bit, ret;
 683
 684         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 685                 return -ENOTSUPP;
 686
 687         switch (param) {
 688         case PIN_CONFIG_BIAS_PULL_UP:
 689         case PIN_CONFIG_BIAS_PULL_DOWN:
 690         case PIN_CONFIG_BIAS_DISABLE:
 691                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 692                         return -ENOTSUPP;
 693
 694                 pfc->info->ops->set_bias(pfc, _pin, param);
 695
 696                 break;
 697
 698         case PIN_CONFIG_DRIVE_STRENGTH:
 699                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 700                 if (ret < 0)
 701                         return ret;
 702
 703                 break;
 704
 705         case PIN_CONFIG_POWER_SOURCE:
 706                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 707                         return -ENOTSUPP;
 708
 709                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 710                 if (bit < 0) {
 711                         printf("invalid pin %#x", _pin);
 712                         return bit;
 713                 }
 714
 715                 if (arg != 1800 && arg != 3300)
 716                         return -EINVAL;
 717
 718                 pocctrl = (void __iomem *)(uintptr_t)addr;
 719
 720                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 721                 if (arg == 3300)
 722                         val |= BIT(bit);
 723                 else
 724                         val &= ~BIT(bit);
 725
 726                 if (unlock_reg)
 727                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 728
 729                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 730
 731                 break;
 732
 733         default:
 734                 return -ENOTSUPP;
 735         }
 736
 737         return 0;
 738 }
 739
 740 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 741                                   unsigned int pin_selector,
 742                                   unsigned int param, unsigned int arg)
 743 {
 744         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 745         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 746         struct sh_pfc *pfc = &priv->pfc;
 747         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 748
 749         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 750
 751         return 0;
 752 }
 753
 754 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 755                                       unsigned int group_selector,
 756                                       unsigned int param, unsigned int arg)
 757 {
 758         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 759         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 760         struct sh_pfc *pfc = &priv->pfc;
 761         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 762         unsigned int i;
 763
 764         for (i = 0; i < grp->nr_pins; i++)
 765                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 766
 767         return 0;
 768 }
 769 #endif
 770
 771 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 772         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 773         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 774         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 775         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 776         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 777         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 778
 779 #if CONFIG_IS_ENABLED(PINCONF)
 780         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 781         .pinconf_params         = sh_pfc_pinconf_params,
 782         .pinconf_set            = sh_pfc_pinconf_pin_set,
 783         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 784 #endif
 785         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 786         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 787         .set_state              = pinctrl_generic_set_state,
 788
 789         .gpio_request_enable    = sh_pfc_gpio_request_enable,
 790         .gpio_disable_free      = sh_pfc_gpio_disable_free,
 791 };
 792
 793 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 794 {
 795         unsigned int i;
 796
 797         /* Allocate and initialize the pins and configs arrays. */
 798         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 799                                     GFP_KERNEL);
 800         if (unlikely(!pmx->configs))
 801                 return -ENOMEM;
 802
 803         for (i = 0; i < pfc->info->nr_pins; ++i) {
 804                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 805                 cfg->type = PINMUX_TYPE_NONE;
 806         }
 807
 808         return 0;
 809 }
 810
 811
 812 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 813 {
 814         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 815         enum sh_pfc_model model = dev_get_driver_data(dev);
 816         fdt_addr_t base;
 817
 818         base = devfdt_get_addr(dev);
 819         if (base == FDT_ADDR_T_NONE)
 820                 return -EINVAL;
 821
 822         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 823         if (!priv->pfc.regs)
 824                 return -ENOMEM;
 825
 826 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 827         if (model == SH_PFC_R8A7790)
 828                 priv->pfc.info = &r8a7790_pinmux_info;
 829 #endif
 830 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 831         if (model == SH_PFC_R8A7791)
 832                 priv->pfc.info = &r8a7791_pinmux_info;
 833 #endif
 834 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 835         if (model == SH_PFC_R8A7792)
 836                 priv->pfc.info = &r8a7792_pinmux_info;
 837 #endif
 838 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 839         if (model == SH_PFC_R8A7793)
 840                 priv->pfc.info = &r8a7793_pinmux_info;
 841 #endif
 842 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 843         if (model == SH_PFC_R8A7794)
 844                 priv->pfc.info = &r8a7794_pinmux_info;
 845 #endif
 846 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 847         if (model == SH_PFC_R8A7795)
 848                 priv->pfc.info = &r8a7795_pinmux_info;
 849 #endif
 850 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 851         if (model == SH_PFC_R8A7796)
 852                 priv->pfc.info = &r8a7796_pinmux_info;
 853 #endif
 854 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 855         if (model == SH_PFC_R8A77965)
 856                 priv->pfc.info = &r8a77965_pinmux_info;
 857 #endif
 858 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 859         if (model == SH_PFC_R8A77970)
 860                 priv->pfc.info = &r8a77970_pinmux_info;
 861 #endif
 862 #ifdef CONFIG_PINCTRL_PFC_R8A77980
 863         if (model == SH_PFC_R8A77980)
 864                 priv->pfc.info = &r8a77980_pinmux_info;
 865 #endif
 866 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 867         if (model == SH_PFC_R8A77990)
 868                 priv->pfc.info = &r8a77990_pinmux_info;
 869 #endif
 870 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 871         if (model == SH_PFC_R8A77995)
 872                 priv->pfc.info = &r8a77995_pinmux_info;
 873 #endif
 874
 875         priv->pmx.pfc = &priv->pfc;
 876         sh_pfc_init_ranges(&priv->pfc);
 877         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 878
 879         return 0;
 880 }
 881
 882 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 883 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 884         {
 885                 .compatible = "renesas,pfc-r8a7790",
 886                 .data = SH_PFC_R8A7790,
 887         },
 888 #endif
 889 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 890         {
 891                 .compatible = "renesas,pfc-r8a7791",
 892                 .data = SH_PFC_R8A7791,
 893         },
 894 #endif
 895 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 896         {
 897                 .compatible = "renesas,pfc-r8a7792",
 898                 .data = SH_PFC_R8A7792,
 899         },
 900 #endif
 901 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 902         {
 903                 .compatible = "renesas,pfc-r8a7793",
 904                 .data = SH_PFC_R8A7793,
 905         },
 906 #endif
 907 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 908         {
 909                 .compatible = "renesas,pfc-r8a7794",
 910                 .data = SH_PFC_R8A7794,
 911         },
 912 #endif
 913 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 914         {
 915                 .compatible = "renesas,pfc-r8a7795",
 916                 .data = SH_PFC_R8A7795,
 917         },
 918 #endif
 919 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 920         {
 921                 .compatible = "renesas,pfc-r8a7796",
 922                 .data = SH_PFC_R8A7796,
 923         },
 924 #endif
 925 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 926         {
 927                 .compatible = "renesas,pfc-r8a77965",
 928                 .data = SH_PFC_R8A77965,
 929         },
 930 #endif
 931 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 932         {
 933                 .compatible = "renesas,pfc-r8a77970",
 934                 .data = SH_PFC_R8A77970,
 935         },
 936 #endif
 937 #ifdef CONFIG_PINCTRL_PFC_R8A77980
 938         {
 939                 .compatible = "renesas,pfc-r8a77980",
 940                 .data = SH_PFC_R8A77980,
 941         },
 942 #endif
 943 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 944         {
 945                 .compatible = "renesas,pfc-r8a77990",
 946                 .data = SH_PFC_R8A77990,
 947         },
 948 #endif
 949 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 950         {
 951                 .compatible = "renesas,pfc-r8a77995",
 952                 .data = SH_PFC_R8A77995,
 953         },
 954 #endif
 955         { },
 956 };
 957
 958 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 959         .name           = "sh_pfc_pinctrl",
 960         .id             = UCLASS_PINCTRL,
 961         .of_match       = sh_pfc_pinctrl_ids,
 962         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 963         .ops            = &sh_pfc_pinctrl_ops,
 964         .probe          = sh_pfc_pinctrl_probe,
 965 };