2 * Pin Control driver for SuperH Pin Function Controller.
4 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 * Copyright (C) 2008 Magnus Damm
7 * Copyright (C) 2009 - 2012 Paul Mundt
8 * Copyright (C) 2017 Marek Vasut
10 * SPDX-License-Identifier: GPL-2.0
13 #define DRV_NAME "sh-pfc"
18 #include <dm/pinctrl.h>
20 #include <linux/sizes.h>
24 DECLARE_GLOBAL_DATA_PTR;
31 struct sh_pfc_pin_config {
35 struct sh_pfc_pinctrl {
38 struct sh_pfc_pin_config *configs;
40 const char *func_prop_name;
41 const char *groups_prop_name;
42 const char *pins_prop_name;
45 struct sh_pfc_pin_range {
50 struct sh_pfc_pinctrl_priv {
52 struct sh_pfc_pinctrl pmx;
55 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
60 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
61 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
63 if (pin <= range->end)
64 return pin >= range->start
65 ? offset + pin - range->start : -1;
67 offset += range->end - range->start + 1;
73 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
75 if (enum_id < r->begin)
84 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
88 return readb(mapped_reg);
90 return readw(mapped_reg);
92 return readl(mapped_reg);
99 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
104 writeb(data, mapped_reg);
107 writew(data, mapped_reg);
110 writel(data, mapped_reg);
117 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
119 return sh_pfc_read_raw_reg(pfc->regs + reg, width);
122 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
124 void __iomem *unlock_reg =
125 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
127 if (pfc->info->unlock_reg)
128 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
130 sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
133 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
134 const struct pinmux_cfg_reg *crp,
136 void __iomem **mapped_regp, u32 *maskp,
141 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
143 if (crp->field_width) {
144 *maskp = (1 << crp->field_width) - 1;
145 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
147 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
148 *posp = crp->reg_width;
149 for (k = 0; k <= in_pos; k++)
150 *posp -= crp->var_field_width[k];
154 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
155 const struct pinmux_cfg_reg *crp,
156 unsigned int field, u32 value)
158 void __iomem *mapped_reg;
159 void __iomem *unlock_reg =
160 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
164 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
166 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
167 "r_width = %u, f_width = %u\n",
168 crp->reg, value, field, crp->reg_width, crp->field_width);
170 mask = ~(mask << pos);
171 value = value << pos;
173 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
177 if (pfc->info->unlock_reg)
178 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
180 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
183 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
184 const struct pinmux_cfg_reg **crp,
185 unsigned int *fieldp, u32 *valuep)
190 const struct pinmux_cfg_reg *config_reg =
191 pfc->info->cfg_regs + k;
192 unsigned int r_width = config_reg->reg_width;
193 unsigned int f_width = config_reg->field_width;
194 unsigned int curr_width;
195 unsigned int bit_pos;
196 unsigned int pos = 0;
202 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
207 curr_width = f_width;
209 curr_width = config_reg->var_field_width[m];
211 ncomb = 1 << curr_width;
212 for (n = 0; n < ncomb; n++) {
213 if (config_reg->enum_ids[pos + n] == enum_id) {
229 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
232 const u16 *data = pfc->info->pinmux_data;
236 *enum_idp = data[pos + 1];
240 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
241 if (data[k] == mark) {
242 *enum_idp = data[k + 1];
247 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
252 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
254 const struct pinmux_range *range;
257 switch (pinmux_type) {
258 case PINMUX_TYPE_GPIO:
259 case PINMUX_TYPE_FUNCTION:
263 case PINMUX_TYPE_OUTPUT:
264 range = &pfc->info->output;
267 case PINMUX_TYPE_INPUT:
268 range = &pfc->info->input;
275 /* Iterate over all the configuration fields we need to update. */
277 const struct pinmux_cfg_reg *cr;
284 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
291 /* Check if the configuration field selects a function. If it
292 * doesn't, skip the field if it's not applicable to the
293 * requested pinmux type.
295 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
297 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
298 /* Functions are allowed to modify all
302 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
303 /* Input/output types can only modify fields
304 * that correspond to their respective ranges.
306 in_range = sh_pfc_enum_in_range(enum_id, range);
309 * special case pass through for fixed
310 * input-only or output-only pins without
311 * function enum register association.
313 if (in_range && enum_id == range->force)
316 /* GPIOs are only allowed to modify function fields. */
322 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
326 sh_pfc_write_config_reg(pfc, cr, field, value);
332 const struct sh_pfc_bias_info *
333 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
334 unsigned int num, unsigned int pin)
338 for (i = 0; i < num; i++)
339 if (info[i].pin == pin)
342 printf("Pin %u is not in bias info list\n", pin);
347 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
349 struct sh_pfc_pin_range *range;
350 unsigned int nr_ranges;
353 if (pfc->info->pins[0].pin == (u16)-1) {
354 /* Pin number -1 denotes that the SoC doesn't report pin numbers
355 * in its pin arrays yet. Consider the pin numbers range as
356 * continuous and allocate a single range.
359 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
360 if (pfc->ranges == NULL)
363 pfc->ranges->start = 0;
364 pfc->ranges->end = pfc->info->nr_pins - 1;
365 pfc->nr_gpio_pins = pfc->info->nr_pins;
370 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
371 * be sorted by pin numbers, and pins without a GPIO port must come
374 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
375 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
379 pfc->nr_ranges = nr_ranges;
380 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
381 if (pfc->ranges == NULL)
385 range->start = pfc->info->pins[0].pin;
387 for (i = 1; i < pfc->info->nr_pins; ++i) {
388 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
391 range->end = pfc->info->pins[i-1].pin;
392 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
393 pfc->nr_gpio_pins = range->end + 1;
396 range->start = pfc->info->pins[i].pin;
399 range->end = pfc->info->pins[i-1].pin;
400 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
401 pfc->nr_gpio_pins = range->end + 1;
406 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
408 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
410 return priv->pfc.info->nr_pins;
413 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
416 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
418 return priv->pfc.info->pins[selector].name;
421 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
423 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
425 return priv->pfc.info->nr_groups;
428 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
431 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
433 return priv->pfc.info->groups[selector].name;
436 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
438 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
440 return priv->pfc.info->nr_functions;
443 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
446 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
448 return priv->pfc.info->functions[selector].name;
451 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
453 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
454 struct sh_pfc_pinctrl *pmx = &priv->pmx;
455 struct sh_pfc *pfc = &priv->pfc;
456 struct sh_pfc_pin_config *cfg;
457 const struct sh_pfc_pin *pin = NULL;
460 for (i = 1; i < pfc->info->nr_pins; i++) {
461 if (priv->pfc.info->pins[i].pin != pin_selector)
464 pin = &priv->pfc.info->pins[i];
471 idx = sh_pfc_get_pin_index(pfc, pin->pin);
472 cfg = &pmx->configs[idx];
474 if (cfg->type != PINMUX_TYPE_NONE)
477 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
480 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
481 unsigned func_selector)
483 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
484 struct sh_pfc_pinctrl *pmx = &priv->pmx;
485 struct sh_pfc *pfc = &priv->pfc;
486 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
487 int idx = sh_pfc_get_pin_index(pfc, pin->pin);
488 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
490 if (cfg->type != PINMUX_TYPE_NONE)
493 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
496 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
497 unsigned func_selector)
499 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
500 struct sh_pfc_pinctrl *pmx = &priv->pmx;
501 struct sh_pfc *pfc = &priv->pfc;
502 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
506 for (i = 0; i < grp->nr_pins; ++i) {
507 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
508 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
510 if (cfg->type != PINMUX_TYPE_NONE) {
516 for (i = 0; i < grp->nr_pins; ++i) {
517 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
525 #if CONFIG_IS_ENABLED(PINCONF)
526 static const struct pinconf_param sh_pfc_pinconf_params[] = {
527 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
528 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
529 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
530 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
531 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
534 static void __iomem *
535 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
536 unsigned int *offset, unsigned int *size)
538 const struct pinmux_drive_reg_field *field;
539 const struct pinmux_drive_reg *reg;
542 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
543 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
544 field = ®->fields[i];
546 if (field->size && field->pin == pin) {
547 *offset = field->offset;
550 return (void __iomem *)(uintptr_t)reg->reg;
558 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
559 unsigned int pin, u16 strength)
565 void __iomem *unlock_reg =
566 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
569 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
573 step = size == 2 ? 6 : 3;
575 if (strength < step || strength > 24)
578 /* Convert the value from mA based on a full drive strength value of
579 * 24mA. We can make the full value configurable later if needed.
581 strength = strength / step - 1;
583 val = sh_pfc_read_raw_reg(reg, 32);
584 val &= ~GENMASK(offset + size - 1, offset);
585 val |= strength << offset;
588 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
590 sh_pfc_write_raw_reg(reg, 32, val);
595 /* Check whether the requested parameter is supported for a pin. */
596 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
599 int idx = sh_pfc_get_pin_index(pfc, _pin);
600 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
603 case PIN_CONFIG_BIAS_DISABLE:
604 return pin->configs &
605 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
607 case PIN_CONFIG_BIAS_PULL_UP:
608 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
610 case PIN_CONFIG_BIAS_PULL_DOWN:
611 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
613 case PIN_CONFIG_DRIVE_STRENGTH:
614 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
616 case PIN_CONFIG_POWER_SOURCE:
617 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
624 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
625 unsigned int param, unsigned int arg)
627 struct sh_pfc *pfc = pmx->pfc;
628 void __iomem *pocctrl;
629 void __iomem *unlock_reg =
630 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
634 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
638 case PIN_CONFIG_BIAS_PULL_UP:
639 case PIN_CONFIG_BIAS_PULL_DOWN:
640 case PIN_CONFIG_BIAS_DISABLE:
641 if (!pfc->info->ops || !pfc->info->ops->set_bias)
644 pfc->info->ops->set_bias(pfc, _pin, param);
648 case PIN_CONFIG_DRIVE_STRENGTH:
649 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
655 case PIN_CONFIG_POWER_SOURCE:
656 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
659 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
661 printf("invalid pin %#x", _pin);
665 if (arg != 1800 && arg != 3300)
668 pocctrl = (void __iomem *)(uintptr_t)addr;
670 val = sh_pfc_read_raw_reg(pocctrl, 32);
677 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
679 sh_pfc_write_raw_reg(pocctrl, 32, val);
690 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
691 unsigned int pin_selector,
692 unsigned int param, unsigned int arg)
694 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
695 struct sh_pfc_pinctrl *pmx = &priv->pmx;
696 struct sh_pfc *pfc = &priv->pfc;
697 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
699 sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
704 static int sh_pfc_pinconf_group_set(struct udevice *dev,
705 unsigned int group_selector,
706 unsigned int param, unsigned int arg)
708 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
709 struct sh_pfc_pinctrl *pmx = &priv->pmx;
710 struct sh_pfc *pfc = &priv->pfc;
711 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
714 for (i = 0; i < grp->nr_pins; i++)
715 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
721 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
722 .get_pins_count = sh_pfc_pinctrl_get_pins_count,
723 .get_pin_name = sh_pfc_pinctrl_get_pin_name,
724 .get_groups_count = sh_pfc_pinctrl_get_groups_count,
725 .get_group_name = sh_pfc_pinctrl_get_group_name,
726 .get_functions_count = sh_pfc_pinctrl_get_functions_count,
727 .get_function_name = sh_pfc_pinctrl_get_function_name,
729 #if CONFIG_IS_ENABLED(PINCONF)
730 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
731 .pinconf_params = sh_pfc_pinconf_params,
732 .pinconf_set = sh_pfc_pinconf_pin_set,
733 .pinconf_group_set = sh_pfc_pinconf_group_set,
735 .pinmux_set = sh_pfc_pinctrl_pin_set,
736 .pinmux_group_set = sh_pfc_pinctrl_group_set,
737 .set_state = pinctrl_generic_set_state,
740 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
744 /* Allocate and initialize the pins and configs arrays. */
745 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
747 if (unlikely(!pmx->configs))
750 for (i = 0; i < pfc->info->nr_pins; ++i) {
751 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
752 cfg->type = PINMUX_TYPE_NONE;
759 static int sh_pfc_pinctrl_probe(struct udevice *dev)
761 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
762 enum sh_pfc_model model = dev_get_driver_data(dev);
765 base = devfdt_get_addr(dev);
766 if (base == FDT_ADDR_T_NONE)
769 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
773 #ifdef CONFIG_PINCTRL_PFC_R8A7795
774 if (model == SH_PFC_R8A7795)
775 priv->pfc.info = &r8a7795_pinmux_info;
777 #ifdef CONFIG_PINCTRL_PFC_R8A7796
778 if (model == SH_PFC_R8A7796)
779 priv->pfc.info = &r8a7796_pinmux_info;
782 priv->pmx.pfc = &priv->pfc;
783 sh_pfc_init_ranges(&priv->pfc);
784 sh_pfc_map_pins(&priv->pfc, &priv->pmx);
789 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
790 #ifdef CONFIG_PINCTRL_PFC_R8A7795
792 .compatible = "renesas,pfc-r8a7795",
793 .data = SH_PFC_R8A7795,
796 #ifdef CONFIG_PINCTRL_PFC_R8A7796
798 .compatible = "renesas,pfc-r8a7796",
799 .data = SH_PFC_R8A7796,
805 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
806 .name = "sh_pfc_pinctrl",
807 .id = UCLASS_PINCTRL,
808 .of_match = sh_pfc_pinctrl_ids,
809 .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
810 .ops = &sh_pfc_pinctrl_ops,
811 .probe = sh_pfc_pinctrl_probe,