Merge tag 'efi-2020-07-rc6' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
[oweals/u-boot.git] / drivers / pinctrl / renesas / pfc-r8a77990.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R8A77990 processor support - PFC hardware block.
4  *
5  * Copyright (C) 2018-2019 Renesas Electronics Corp.
6  *
7  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
8  *
9  * R8A7796 processor support - PFC hardware block.
10  *
11  * Copyright (C) 2016-2017 Renesas Electronics Corp.
12  */
13
14 #include <common.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <dm/pinctrl.h>
18 #include <linux/bitops.h>
19 #include <linux/kernel.h>
20
21 #include "sh_pfc.h"
22
23 #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
24                    SH_PFC_PIN_CFG_PULL_DOWN)
25
26 #define CPU_ALL_PORT(fn, sfx) \
27         PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
28         PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
29         PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
30         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
32         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
33         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
34         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
35         PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
36         PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
37         PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
38         PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
39         PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
40         PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
41         PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
42         PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
43         PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
44         PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
45         PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
46         PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
47 /*
48  * F_() : just information
49  * FM() : macro for FN_xxx / xxx_MARK
50  */
51
52 /* GPSR0 */
53 #define GPSR0_17        F_(SDA4,                IP7_27_24)
54 #define GPSR0_16        F_(SCL4,                IP7_23_20)
55 #define GPSR0_15        F_(D15,                 IP7_19_16)
56 #define GPSR0_14        F_(D14,                 IP7_15_12)
57 #define GPSR0_13        F_(D13,                 IP7_11_8)
58 #define GPSR0_12        F_(D12,                 IP7_7_4)
59 #define GPSR0_11        F_(D11,                 IP7_3_0)
60 #define GPSR0_10        F_(D10,                 IP6_31_28)
61 #define GPSR0_9         F_(D9,                  IP6_27_24)
62 #define GPSR0_8         F_(D8,                  IP6_23_20)
63 #define GPSR0_7         F_(D7,                  IP6_19_16)
64 #define GPSR0_6         F_(D6,                  IP6_15_12)
65 #define GPSR0_5         F_(D5,                  IP6_11_8)
66 #define GPSR0_4         F_(D4,                  IP6_7_4)
67 #define GPSR0_3         F_(D3,                  IP6_3_0)
68 #define GPSR0_2         F_(D2,                  IP5_31_28)
69 #define GPSR0_1         F_(D1,                  IP5_27_24)
70 #define GPSR0_0         F_(D0,                  IP5_23_20)
71
72 /* GPSR1 */
73 #define GPSR1_22        F_(WE0_N,               IP5_19_16)
74 #define GPSR1_21        F_(CS0_N,               IP5_15_12)
75 #define GPSR1_20        FM(CLKOUT)
76 #define GPSR1_19        F_(A19,                 IP5_11_8)
77 #define GPSR1_18        F_(A18,                 IP5_7_4)
78 #define GPSR1_17        F_(A17,                 IP5_3_0)
79 #define GPSR1_16        F_(A16,                 IP4_31_28)
80 #define GPSR1_15        F_(A15,                 IP4_27_24)
81 #define GPSR1_14        F_(A14,                 IP4_23_20)
82 #define GPSR1_13        F_(A13,                 IP4_19_16)
83 #define GPSR1_12        F_(A12,                 IP4_15_12)
84 #define GPSR1_11        F_(A11,                 IP4_11_8)
85 #define GPSR1_10        F_(A10,                 IP4_7_4)
86 #define GPSR1_9         F_(A9,                  IP4_3_0)
87 #define GPSR1_8         F_(A8,                  IP3_31_28)
88 #define GPSR1_7         F_(A7,                  IP3_27_24)
89 #define GPSR1_6         F_(A6,                  IP3_23_20)
90 #define GPSR1_5         F_(A5,                  IP3_19_16)
91 #define GPSR1_4         F_(A4,                  IP3_15_12)
92 #define GPSR1_3         F_(A3,                  IP3_11_8)
93 #define GPSR1_2         F_(A2,                  IP3_7_4)
94 #define GPSR1_1         F_(A1,                  IP3_3_0)
95 #define GPSR1_0         F_(A0,                  IP2_31_28)
96
97 /* GPSR2 */
98 #define GPSR2_25        F_(EX_WAIT0,            IP2_27_24)
99 #define GPSR2_24        F_(RD_WR_N,             IP2_23_20)
100 #define GPSR2_23        F_(RD_N,                IP2_19_16)
101 #define GPSR2_22        F_(BS_N,                IP2_15_12)
102 #define GPSR2_21        FM(AVB_PHY_INT)
103 #define GPSR2_20        F_(AVB_TXCREFCLK,       IP2_3_0)
104 #define GPSR2_19        FM(AVB_RD3)
105 #define GPSR2_18        F_(AVB_RD2,             IP1_31_28)
106 #define GPSR2_17        F_(AVB_RD1,             IP1_27_24)
107 #define GPSR2_16        F_(AVB_RD0,             IP1_23_20)
108 #define GPSR2_15        FM(AVB_RXC)
109 #define GPSR2_14        FM(AVB_RX_CTL)
110 #define GPSR2_13        F_(RPC_RESET_N,         IP1_19_16)
111 #define GPSR2_12        F_(RPC_INT_N,           IP1_15_12)
112 #define GPSR2_11        F_(QSPI1_SSL,           IP1_11_8)
113 #define GPSR2_10        F_(QSPI1_IO3,           IP1_7_4)
114 #define GPSR2_9         F_(QSPI1_IO2,           IP1_3_0)
115 #define GPSR2_8         F_(QSPI1_MISO_IO1,      IP0_31_28)
116 #define GPSR2_7         F_(QSPI1_MOSI_IO0,      IP0_27_24)
117 #define GPSR2_6         F_(QSPI1_SPCLK,         IP0_23_20)
118 #define GPSR2_5         FM(QSPI0_SSL)
119 #define GPSR2_4         F_(QSPI0_IO3,           IP0_19_16)
120 #define GPSR2_3         F_(QSPI0_IO2,           IP0_15_12)
121 #define GPSR2_2         F_(QSPI0_MISO_IO1,      IP0_11_8)
122 #define GPSR2_1         F_(QSPI0_MOSI_IO0,      IP0_7_4)
123 #define GPSR2_0         F_(QSPI0_SPCLK,         IP0_3_0)
124
125 /* GPSR3 */
126 #define GPSR3_15        F_(SD1_WP,              IP11_7_4)
127 #define GPSR3_14        F_(SD1_CD,              IP11_3_0)
128 #define GPSR3_13        F_(SD0_WP,              IP10_31_28)
129 #define GPSR3_12        F_(SD0_CD,              IP10_27_24)
130 #define GPSR3_11        F_(SD1_DAT3,            IP9_11_8)
131 #define GPSR3_10        F_(SD1_DAT2,            IP9_7_4)
132 #define GPSR3_9         F_(SD1_DAT1,            IP9_3_0)
133 #define GPSR3_8         F_(SD1_DAT0,            IP8_31_28)
134 #define GPSR3_7         F_(SD1_CMD,             IP8_27_24)
135 #define GPSR3_6         F_(SD1_CLK,             IP8_23_20)
136 #define GPSR3_5         F_(SD0_DAT3,            IP8_19_16)
137 #define GPSR3_4         F_(SD0_DAT2,            IP8_15_12)
138 #define GPSR3_3         F_(SD0_DAT1,            IP8_11_8)
139 #define GPSR3_2         F_(SD0_DAT0,            IP8_7_4)
140 #define GPSR3_1         F_(SD0_CMD,             IP8_3_0)
141 #define GPSR3_0         F_(SD0_CLK,             IP7_31_28)
142
143 /* GPSR4 */
144 #define GPSR4_10        F_(SD3_DS,              IP10_23_20)
145 #define GPSR4_9         F_(SD3_DAT7,            IP10_19_16)
146 #define GPSR4_8         F_(SD3_DAT6,            IP10_15_12)
147 #define GPSR4_7         F_(SD3_DAT5,            IP10_11_8)
148 #define GPSR4_6         F_(SD3_DAT4,            IP10_7_4)
149 #define GPSR4_5         F_(SD3_DAT3,            IP10_3_0)
150 #define GPSR4_4         F_(SD3_DAT2,            IP9_31_28)
151 #define GPSR4_3         F_(SD3_DAT1,            IP9_27_24)
152 #define GPSR4_2         F_(SD3_DAT0,            IP9_23_20)
153 #define GPSR4_1         F_(SD3_CMD,             IP9_19_16)
154 #define GPSR4_0         F_(SD3_CLK,             IP9_15_12)
155
156 /* GPSR5 */
157 #define GPSR5_19        F_(MLB_DAT,             IP13_23_20)
158 #define GPSR5_18        F_(MLB_SIG,             IP13_19_16)
159 #define GPSR5_17        F_(MLB_CLK,             IP13_15_12)
160 #define GPSR5_16        F_(SSI_SDATA9,          IP13_11_8)
161 #define GPSR5_15        F_(MSIOF0_SS2,          IP13_7_4)
162 #define GPSR5_14        F_(MSIOF0_SS1,          IP13_3_0)
163 #define GPSR5_13        F_(MSIOF0_SYNC,         IP12_31_28)
164 #define GPSR5_12        F_(MSIOF0_TXD,          IP12_27_24)
165 #define GPSR5_11        F_(MSIOF0_RXD,          IP12_23_20)
166 #define GPSR5_10        F_(MSIOF0_SCK,          IP12_19_16)
167 #define GPSR5_9         F_(RX2_A,               IP12_15_12)
168 #define GPSR5_8         F_(TX2_A,               IP12_11_8)
169 #define GPSR5_7         F_(SCK2_A,              IP12_7_4)
170 #define GPSR5_6         F_(TX1,                 IP12_3_0)
171 #define GPSR5_5         F_(RX1,                 IP11_31_28)
172 #define GPSR5_4         F_(RTS0_N_A,            IP11_23_20)
173 #define GPSR5_3         F_(CTS0_N_A,            IP11_19_16)
174 #define GPSR5_2         F_(TX0_A,               IP11_15_12)
175 #define GPSR5_1         F_(RX0_A,               IP11_11_8)
176 #define GPSR5_0         F_(SCK0_A,              IP11_27_24)
177
178 /* GPSR6 */
179 #define GPSR6_17        F_(USB30_PWEN,          IP15_27_24)
180 #define GPSR6_16        F_(SSI_SDATA6,          IP15_19_16)
181 #define GPSR6_15        F_(SSI_WS6,             IP15_15_12)
182 #define GPSR6_14        F_(SSI_SCK6,            IP15_11_8)
183 #define GPSR6_13        F_(SSI_SDATA5,          IP15_7_4)
184 #define GPSR6_12        F_(SSI_WS5,             IP15_3_0)
185 #define GPSR6_11        F_(SSI_SCK5,            IP14_31_28)
186 #define GPSR6_10        F_(SSI_SDATA4,          IP14_27_24)
187 #define GPSR6_9         F_(USB30_OVC,           IP15_31_28)
188 #define GPSR6_8         F_(AUDIO_CLKA,          IP15_23_20)
189 #define GPSR6_7         F_(SSI_SDATA3,          IP14_23_20)
190 #define GPSR6_6         F_(SSI_WS349,           IP14_19_16)
191 #define GPSR6_5         F_(SSI_SCK349,          IP14_15_12)
192 #define GPSR6_4         F_(SSI_SDATA2,          IP14_11_8)
193 #define GPSR6_3         F_(SSI_SDATA1,          IP14_7_4)
194 #define GPSR6_2         F_(SSI_SDATA0,          IP14_3_0)
195 #define GPSR6_1         F_(SSI_WS01239,         IP13_31_28)
196 #define GPSR6_0         F_(SSI_SCK01239,        IP13_27_24)
197
198 /* IPSRx */             /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */         /* 8 */         /* 9 - F */
199 #define IP0_3_0         FM(QSPI0_SPCLK)         FM(HSCK4_A)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP0_7_4         FM(QSPI0_MOSI_IO0)      FM(HCTS4_N_A)           F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP0_11_8        FM(QSPI0_MISO_IO1)      FM(HRTS4_N_A)           F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP0_15_12       FM(QSPI0_IO2)           FM(HTX4_A)              F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP0_19_16       FM(QSPI0_IO3)           FM(HRX4_A)              F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP0_23_20       FM(QSPI1_SPCLK)         FM(RIF2_CLK_A)          FM(HSCK4_B)             FM(VI4_DATA0_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP0_27_24       FM(QSPI1_MOSI_IO0)      FM(RIF2_SYNC_A)         FM(HTX4_B)              FM(VI4_DATA1_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP0_31_28       FM(QSPI1_MISO_IO1)      FM(RIF2_D0_A)           FM(HRX4_B)              FM(VI4_DATA2_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP1_3_0         FM(QSPI1_IO2)           FM(RIF2_D1_A)           FM(HTX3_C)              FM(VI4_DATA3_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP1_7_4         FM(QSPI1_IO3)           FM(RIF3_CLK_A)          FM(HRX3_C)              FM(VI4_DATA4_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP1_11_8        FM(QSPI1_SSL)           FM(RIF3_SYNC_A)         FM(HSCK3_C)             FM(VI4_DATA5_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP1_15_12       FM(RPC_INT_N)           FM(RIF3_D0_A)           FM(HCTS3_N_C)           FM(VI4_DATA6_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP1_19_16       FM(RPC_RESET_N)         FM(RIF3_D1_A)           FM(HRTS3_N_C)           FM(VI4_DATA7_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP1_23_20       FM(AVB_RD0)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP1_27_24       FM(AVB_RD1)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP1_31_28       FM(AVB_RD2)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP2_3_0         FM(AVB_TXCREFCLK)       F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP2_7_4         FM(AVB_MDIO)            F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP2_11_8        FM(AVB_MDC)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP2_15_12       FM(BS_N)                FM(PWM0_A)              FM(AVB_MAGIC)           FM(VI4_CLK)             F_(0, 0)                FM(TX3_C)       F_(0, 0)        FM(VI5_CLK_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP2_19_16       FM(RD_N)                FM(PWM1_A)              FM(AVB_LINK)            FM(VI4_FIELD)           F_(0, 0)                FM(RX3_C)       FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP2_23_20       FM(RD_WR_N)             FM(SCL7_A)              FM(AVB_AVTP_MATCH_A)    FM(VI4_VSYNC_N)         FM(TX5_B)               FM(SCK3_C)      FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP2_27_24       FM(EX_WAIT0)            FM(SDA7_A)              FM(AVB_AVTP_CAPTURE_A)  FM(VI4_HSYNC_N)         FM(RX5_B)               FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP2_31_28       FM(A0)                  FM(IRQ0)                FM(PWM2_A)              FM(MSIOF3_SS1_B)        FM(VI5_CLK_A)           FM(DU_CDE)      FM(HRX3_D)      FM(IERX)        FM(QSTB_QHE)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP3_3_0         FM(A1)                  FM(IRQ1)                FM(PWM3_A)              FM(DU_DOTCLKIN1)        FM(VI5_DATA0_A)         FM(DU_DISP_CDE) FM(SDA6_B)      FM(IETX)        FM(QCPV_QDE)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP3_7_4         FM(A2)                  FM(IRQ2)                FM(AVB_AVTP_PPS)        FM(VI4_CLKENB)          FM(VI5_DATA1_A)         FM(DU_DISP)     FM(SCL6_B)      F_(0, 0)        FM(QSTVB_QVE)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP3_11_8        FM(A3)                  FM(CTS4_N_A)            FM(PWM4_A)              FM(VI4_DATA12)          F_(0, 0)                FM(DU_DOTCLKOUT0) FM(HTX3_D)    FM(IECLK)       FM(LCDOUT12)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP3_15_12       FM(A4)                  FM(RTS4_N_A)            FM(MSIOF3_SYNC_B)       FM(VI4_DATA8)           FM(PWM2_B)              FM(DU_DG4)      FM(RIF2_CLK_B)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP3_19_16       FM(A5)                  FM(SCK4_A)              FM(MSIOF3_SCK_B)        FM(VI4_DATA9)           FM(PWM3_B)              F_(0, 0)        FM(RIF2_SYNC_B) F_(0, 0)        FM(QPOLA)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP3_23_20       FM(A6)                  FM(RX4_A)               FM(MSIOF3_RXD_B)        FM(VI4_DATA10)          F_(0, 0)                F_(0, 0)        FM(RIF2_D0_B)   F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP3_27_24       FM(A7)                  FM(TX4_A)               FM(MSIOF3_TXD_B)        FM(VI4_DATA11)          F_(0, 0)                F_(0, 0)        FM(RIF2_D1_B)   F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP3_31_28       FM(A8)                  FM(SDA6_A)              FM(RX3_B)               FM(HRX4_C)              FM(VI5_HSYNC_N_A)       FM(DU_HSYNC)    FM(VI4_DATA0_B) F_(0, 0)        FM(QSTH_QHS)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232 /* IPSRx */             /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */         /* 8 */         /* 9 - F */
233 #define IP4_3_0         FM(A9)                  FM(TX5_A)               FM(IRQ3)                FM(VI4_DATA16)          FM(VI5_VSYNC_N_A)       FM(DU_DG7)      F_(0, 0)        F_(0, 0)        FM(LCDOUT15)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP4_7_4         FM(A10)                 FM(IRQ4)                FM(MSIOF2_SYNC_B)       FM(VI4_DATA13)          FM(VI5_FIELD_A)         FM(DU_DG5)      FM(FSCLKST2_N_B) F_(0, 0)       FM(LCDOUT13)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP4_11_8        FM(A11)                 FM(SCL6_A)              FM(TX3_B)               FM(HTX4_C)              F_(0, 0)                FM(DU_VSYNC)    FM(VI4_DATA1_B) F_(0, 0)        FM(QSTVA_QVS)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP4_15_12       FM(A12)                 FM(RX5_A)               FM(MSIOF2_SS2_B)        FM(VI4_DATA17)          FM(VI5_DATA3_A)         FM(DU_DG6)      F_(0, 0)        F_(0, 0)        FM(LCDOUT14)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP4_19_16       FM(A13)                 FM(SCK5_A)              FM(MSIOF2_SCK_B)        FM(VI4_DATA14)          FM(HRX4_D)              FM(DU_DB2)      F_(0, 0)        F_(0, 0)        FM(LCDOUT2)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP4_23_20       FM(A14)                 FM(MSIOF1_SS1)          FM(MSIOF2_RXD_B)        FM(VI4_DATA15)          FM(HTX4_D)              FM(DU_DB3)      F_(0, 0)        F_(0, 0)        FM(LCDOUT3)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP4_27_24       FM(A15)                 FM(MSIOF1_SS2)          FM(MSIOF2_TXD_B)        FM(VI4_DATA18)          FM(VI5_DATA4_A)         FM(DU_DB4)      F_(0, 0)        F_(0, 0)        FM(LCDOUT4)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP4_31_28       FM(A16)                 FM(MSIOF1_SYNC)         FM(MSIOF2_SS1_B)        FM(VI4_DATA19)          FM(VI5_DATA5_A)         FM(DU_DB5)      F_(0, 0)        F_(0, 0)        FM(LCDOUT5)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP5_3_0         FM(A17)                 FM(MSIOF1_RXD)          F_(0, 0)                FM(VI4_DATA20)          FM(VI5_DATA6_A)         FM(DU_DB6)      F_(0, 0)        F_(0, 0)        FM(LCDOUT6)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP5_7_4         FM(A18)                 FM(MSIOF1_TXD)          F_(0, 0)                FM(VI4_DATA21)          FM(VI5_DATA7_A)         FM(DU_DB0)      F_(0, 0)        FM(HRX4_E)      FM(LCDOUT0)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP5_11_8        FM(A19)                 FM(MSIOF1_SCK)          F_(0, 0)                FM(VI4_DATA22)          FM(VI5_DATA2_A)         FM(DU_DB1)      F_(0, 0)        FM(HTX4_E)      FM(LCDOUT1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP5_15_12       FM(CS0_N)               FM(SCL5)                F_(0, 0)                F_(0, 0)                F_(0, 0)                FM(DU_DR0)      FM(VI4_DATA2_B) F_(0, 0)        FM(LCDOUT16)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP5_19_16       FM(WE0_N)               FM(SDA5)                F_(0, 0)                F_(0, 0)                F_(0, 0)                FM(DU_DR1)      FM(VI4_DATA3_B) F_(0, 0)        FM(LCDOUT17)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP5_23_20       FM(D0)                  FM(MSIOF3_SCK_A)        F_(0, 0)                F_(0, 0)                F_(0, 0)                FM(DU_DR2)      FM(CTS4_N_C)    F_(0, 0)        FM(LCDOUT18)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP5_27_24       FM(D1)                  FM(MSIOF3_SYNC_A)       FM(SCK3_A)              FM(VI4_DATA23)          FM(VI5_CLKENB_A)        FM(DU_DB7)      FM(RTS4_N_C)    F_(0, 0)        FM(LCDOUT7)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP5_31_28       FM(D2)                  FM(MSIOF3_RXD_A)        FM(RX5_C)               F_(0, 0)                FM(VI5_DATA14_A)        FM(DU_DR3)      FM(RX4_C)       F_(0, 0)        FM(LCDOUT19)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP6_3_0         FM(D3)                  FM(MSIOF3_TXD_A)        FM(TX5_C)               F_(0, 0)                FM(VI5_DATA15_A)        FM(DU_DR4)      FM(TX4_C)       F_(0, 0)        FM(LCDOUT20)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP6_7_4         FM(D4)                  FM(CANFD1_TX)           FM(HSCK3_B)             FM(CAN1_TX)             FM(RTS3_N_A)            FM(MSIOF3_SS2_A) F_(0, 0)       FM(VI5_DATA1_B) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP6_11_8        FM(D5)                  FM(RX3_A)               FM(HRX3_B)              F_(0, 0)                F_(0, 0)                FM(DU_DR5)      FM(VI4_DATA4_B) F_(0, 0)        FM(LCDOUT21)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP6_15_12       FM(D6)                  FM(TX3_A)               FM(HTX3_B)              F_(0, 0)                F_(0, 0)                FM(DU_DR6)      FM(VI4_DATA5_B) F_(0, 0)        FM(LCDOUT22)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP6_19_16       FM(D7)                  FM(CANFD1_RX)           FM(IRQ5)                FM(CAN1_RX)             FM(CTS3_N_A)            F_(0, 0)        F_(0, 0)        FM(VI5_DATA2_B) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP6_23_20       FM(D8)                  FM(MSIOF2_SCK_A)        FM(SCK4_B)              F_(0, 0)                FM(VI5_DATA12_A)        FM(DU_DR7)      FM(RIF3_CLK_B)  FM(HCTS3_N_E)   FM(LCDOUT23)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP6_27_24       FM(D9)                  FM(MSIOF2_SYNC_A)       F_(0, 0)                F_(0, 0)                FM(VI5_DATA10_A)        FM(DU_DG0)      FM(RIF3_SYNC_B) FM(HRX3_E)      FM(LCDOUT8)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP6_31_28       FM(D10)                 FM(MSIOF2_RXD_A)        F_(0, 0)                F_(0, 0)                FM(VI5_DATA13_A)        FM(DU_DG1)      FM(RIF3_D0_B)   FM(HTX3_E)      FM(LCDOUT9)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP7_3_0         FM(D11)                 FM(MSIOF2_TXD_A)        F_(0, 0)                F_(0, 0)                FM(VI5_DATA11_A)        FM(DU_DG2)      FM(RIF3_D1_B)   FM(HRTS3_N_E)   FM(LCDOUT10)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP7_7_4         FM(D12)                 FM(CANFD0_TX)           FM(TX4_B)               FM(CAN0_TX)             FM(VI5_DATA8_A)         F_(0, 0)        F_(0, 0)        FM(VI5_DATA3_B) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP7_11_8        FM(D13)                 FM(CANFD0_RX)           FM(RX4_B)               FM(CAN0_RX)             FM(VI5_DATA9_A)         FM(SCL7_B)      F_(0, 0)        FM(VI5_DATA4_B) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP7_15_12       FM(D14)                 FM(CAN_CLK)             FM(HRX3_A)              FM(MSIOF2_SS2_A)        F_(0, 0)                FM(SDA7_B)      F_(0, 0)        FM(VI5_DATA5_B) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP7_19_16       FM(D15)                 FM(MSIOF2_SS1_A)        FM(HTX3_A)              FM(MSIOF3_SS1_A)        F_(0, 0)                FM(DU_DG3)      F_(0, 0)        F_(0, 0)        FM(LCDOUT11)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP7_23_20       FM(SCL4)                FM(CS1_N_A26)           F_(0, 0)                F_(0, 0)                F_(0, 0)                FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP7_27_24       FM(SDA4)                FM(WE1_N)               F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP7_31_28       FM(SD0_CLK)             FM(NFDATA8)             FM(SCL1_C)              FM(HSCK1_B)             FM(SDA2_E)              FM(FMCLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265
266 /* IPSRx */             /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */         /* 8 */         /* 9 - F */
267 #define IP8_3_0         FM(SD0_CMD)             FM(NFDATA9)             F_(0, 0)                FM(HRX1_B)              F_(0, 0)                FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP8_7_4         FM(SD0_DAT0)            FM(NFDATA10)            F_(0, 0)                FM(HTX1_B)              F_(0, 0)                FM(REMOCON_B)   F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP8_11_8        FM(SD0_DAT1)            FM(NFDATA11)            FM(SDA2_C)              FM(HCTS1_N_B)           F_(0, 0)                FM(FMIN_B)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP8_15_12       FM(SD0_DAT2)            FM(NFDATA12)            FM(SCL2_C)              FM(HRTS1_N_B)           F_(0, 0)                FM(BPFCLK_B)    F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP8_19_16       FM(SD0_DAT3)            FM(NFDATA13)            FM(SDA1_C)              FM(SCL2_E)              FM(SPEEDIN_C)           FM(REMOCON_C)   F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP8_23_20       FM(SD1_CLK)             FM(NFDATA14_B)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP8_27_24       FM(SD1_CMD)             FM(NFDATA15_B)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP8_31_28       FM(SD1_DAT0)            FM(NFWP_N_B)            F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP9_3_0         FM(SD1_DAT1)            FM(NFCE_N_B)            F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP9_7_4         FM(SD1_DAT2)            FM(NFALE_B)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP9_11_8        FM(SD1_DAT3)            FM(NFRB_N_B)            F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP9_15_12       FM(SD3_CLK)             FM(NFWE_N)              F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP9_19_16       FM(SD3_CMD)             FM(NFRE_N)              F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP9_23_20       FM(SD3_DAT0)            FM(NFDATA0)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP9_27_24       FM(SD3_DAT1)            FM(NFDATA1)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP9_31_28       FM(SD3_DAT2)            FM(NFDATA2)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP10_3_0        FM(SD3_DAT3)            FM(NFDATA3)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP10_7_4        FM(SD3_DAT4)            FM(NFDATA4)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP10_11_8       FM(SD3_DAT5)            FM(NFDATA5)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP10_15_12      FM(SD3_DAT6)            FM(NFDATA6)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP10_19_16      FM(SD3_DAT7)            FM(NFDATA7)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP10_23_20      FM(SD3_DS)              FM(NFCLE)               F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP10_27_24      FM(SD0_CD)              FM(NFALE_A)             FM(SD3_CD)              FM(RIF0_CLK_B)          FM(SCL2_B)              FM(TCLK1_A)     FM(SSI_SCK2_B)  FM(TS_SCK0)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP10_31_28      FM(SD0_WP)              FM(NFRB_N_A)            FM(SD3_WP)              FM(RIF0_D0_B)           FM(SDA2_B)              FM(TCLK2_A)     FM(SSI_WS2_B)   FM(TS_SDAT0)    F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP11_3_0        FM(SD1_CD)              FM(NFCE_N_A)            FM(SSI_SCK1)            FM(RIF0_D1_B)           F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(TS_SDEN0)    F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP11_7_4        FM(SD1_WP)              FM(NFWP_N_A)            FM(SSI_WS1)             FM(RIF0_SYNC_B)         F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(TS_SPSYNC0)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP11_11_8       FM(RX0_A)               FM(HRX1_A)              FM(SSI_SCK2_A)          FM(RIF1_SYNC)           F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(TS_SCK1)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP11_15_12      FM(TX0_A)               FM(HTX1_A)              FM(SSI_WS2_A)           FM(RIF1_D0)             F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(TS_SDAT1)    F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP11_19_16      FM(CTS0_N_A)            FM(NFDATA14_A)          FM(AUDIO_CLKOUT_A)      FM(RIF1_D1)             FM(SCIF_CLK_A)          FM(FMCLK_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP11_23_20      FM(RTS0_N_A)            FM(NFDATA15_A)          FM(AUDIO_CLKOUT1_A)     FM(RIF1_CLK)            FM(SCL2_A)              FM(FMIN_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP11_27_24      FM(SCK0_A)              FM(HSCK1_A)             FM(USB3HS0_ID)          FM(RTS1_N)              FM(SDA2_A)              FM(FMCLK_C)     F_(0, 0)        F_(0, 0)        FM(USB0_ID)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP11_31_28      FM(RX1)                 FM(HRX2_B)              FM(SSI_SCK9_B)          FM(AUDIO_CLKOUT1_B)     F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299
300 /* IPSRx */             /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */         /* 8 */         /* 9 - F */
301 #define IP12_3_0        FM(TX1)                 FM(HTX2_B)              FM(SSI_WS9_B)           FM(AUDIO_CLKOUT3_B)     F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP12_7_4        FM(SCK2_A)              FM(HSCK0_A)             FM(AUDIO_CLKB_A)        FM(CTS1_N)              FM(RIF0_CLK_A)          FM(REMOCON_A)   FM(SCIF_CLK_B)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP12_11_8       FM(TX2_A)               FM(HRX0_A)              FM(AUDIO_CLKOUT2_A)     F_(0, 0)                FM(SCL1_A)              F_(0, 0)        FM(FSO_CFE_0_N_A) FM(TS_SDEN1)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP12_15_12      FM(RX2_A)               FM(HTX0_A)              FM(AUDIO_CLKOUT3_A)     F_(0, 0)                FM(SDA1_A)              F_(0, 0)        FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP12_19_16      FM(MSIOF0_SCK)          F_(0, 0)                FM(SSI_SCK78)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP12_23_20      FM(MSIOF0_RXD)          F_(0, 0)                FM(SSI_WS78)            F_(0, 0)                F_(0, 0)                FM(TX2_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP12_27_24      FM(MSIOF0_TXD)          F_(0, 0)                FM(SSI_SDATA7)          F_(0, 0)                F_(0, 0)                FM(RX2_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP12_31_28      FM(MSIOF0_SYNC)         FM(AUDIO_CLKOUT_B)      FM(SSI_SDATA8)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP13_3_0        FM(MSIOF0_SS1)          FM(HRX2_A)              FM(SSI_SCK4)            FM(HCTS0_N_A)           FM(BPFCLK_C)            FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP13_7_4        FM(MSIOF0_SS2)          FM(HTX2_A)              FM(SSI_WS4)             FM(HRTS0_N_A)           FM(FMIN_C)              FM(BPFCLK_A)    F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP13_11_8       FM(SSI_SDATA9)          F_(0, 0)                FM(AUDIO_CLKC_A)        FM(SCK1)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP13_15_12      FM(MLB_CLK)             FM(RX0_B)               F_(0, 0)                FM(RIF0_D0_A)           FM(SCL1_B)              FM(TCLK1_B)     F_(0, 0)        F_(0, 0)        FM(SIM0_RST_A)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP13_19_16      FM(MLB_SIG)             FM(SCK0_B)              F_(0, 0)                FM(RIF0_D1_A)           FM(SDA1_B)              FM(TCLK2_B)     F_(0, 0)        F_(0, 0)        FM(SIM0_D_A)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP13_23_20      FM(MLB_DAT)             FM(TX0_B)               F_(0, 0)                FM(RIF0_SYNC_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP13_27_24      FM(SSI_SCK01239)        F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP13_31_28      FM(SSI_WS01239)         F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP14_3_0        FM(SSI_SDATA0)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP14_7_4        FM(SSI_SDATA1)          FM(AUDIO_CLKC_B)        F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM0_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP14_11_8       FM(SSI_SDATA2)          FM(AUDIO_CLKOUT2_B)     FM(SSI_SCK9_A)          F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP14_15_12      FM(SSI_SCK349)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM2_C)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP14_19_16      FM(SSI_WS349)           F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM3_C)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP14_23_20      FM(SSI_SDATA3)          FM(AUDIO_CLKOUT1_C)     FM(AUDIO_CLKB_B)        F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP14_27_24      FM(SSI_SDATA4)          F_(0, 0)                FM(SSI_WS9_A)           F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP14_31_28      FM(SSI_SCK5)            FM(HRX0_B)              F_(0, 0)                FM(USB0_PWEN_B)         FM(SCL2_D)              F_(0, 0)        FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP15_3_0        FM(SSI_WS5)             FM(HTX0_B)              F_(0, 0)                FM(USB0_OVC_B)          FM(SDA2_D)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP15_7_4        FM(SSI_SDATA5)          FM(HSCK0_B)             FM(AUDIO_CLKB_C)        FM(TPU0TO0)             F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP15_11_8       FM(SSI_SCK6)            FM(HSCK2_A)             FM(AUDIO_CLKC_C)        FM(TPU0TO1)             F_(0, 0)                F_(0, 0)        FM(FSO_CFE_0_N_B) F_(0, 0)      FM(SIM0_RST_B)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP15_15_12      FM(SSI_WS6)             FM(HCTS2_N_A)           FM(AUDIO_CLKOUT2_C)     FM(TPU0TO2)             FM(SDA1_D)              F_(0, 0)        FM(FSO_CFE_1_N_B) F_(0, 0)      FM(SIM0_D_B)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP15_19_16      FM(SSI_SDATA6)          FM(HRTS2_N_A)           FM(AUDIO_CLKOUT3_C)     FM(TPU0TO3)             FM(SCL1_D)              F_(0, 0)        FM(FSO_TOE_N_B) F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP15_23_20      FM(AUDIO_CLKA)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP15_27_24      FM(USB30_PWEN)          FM(USB0_PWEN_A)         F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP15_31_28      FM(USB30_OVC)           FM(USB0_OVC_A)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(FSO_TOE_N_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333
334 #define PINMUX_GPSR     \
335 \
336                                                                                                          \
337                                                                                                          \
338                                                                                                          \
339                                                                                                          \
340                                                                                                          \
341                                                                                                          \
342                                 GPSR2_25                                                                 \
343                                 GPSR2_24                                                                 \
344                                 GPSR2_23                                                                 \
345                 GPSR1_22        GPSR2_22                                                                 \
346                 GPSR1_21        GPSR2_21                                                                 \
347                 GPSR1_20        GPSR2_20                                                                 \
348                 GPSR1_19        GPSR2_19                                        GPSR5_19                 \
349                 GPSR1_18        GPSR2_18                                        GPSR5_18                 \
350 GPSR0_17        GPSR1_17        GPSR2_17                                        GPSR5_17        GPSR6_17 \
351 GPSR0_16        GPSR1_16        GPSR2_16                                        GPSR5_16        GPSR6_16 \
352 GPSR0_15        GPSR1_15        GPSR2_15        GPSR3_15                        GPSR5_15        GPSR6_15 \
353 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14                        GPSR5_14        GPSR6_14 \
354 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13                        GPSR5_13        GPSR6_13 \
355 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12                        GPSR5_12        GPSR6_12 \
356 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11                        GPSR5_11        GPSR6_11 \
357 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
358 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
359 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
360 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
361 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
362 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
363 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
364 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3 \
365 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2 \
366 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1 \
367 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0
368
369 #define PINMUX_IPSR                             \
370 \
371 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
372 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
373 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
374 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
375 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
376 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
377 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
378 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
379 \
380 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
381 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
382 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
383 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
384 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
385 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
386 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
387 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
388 \
389 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
390 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
391 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
392 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
393 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
394 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
395 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
396 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
397 \
398 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
399 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
400 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
401 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
402 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
403 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
404 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
405 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28
406
407 /* The bit numbering in MOD_SEL fields is reversed */
408 #define REV4(f0, f1, f2, f3)                    f0 f2 f1 f3
409 #define REV8(f0, f1, f2, f3, f4, f5, f6, f7)    f0 f4 f2 f6 f1 f5 f3 f7
410
411 /* MOD_SEL0 */                  /* 0 */                         /* 1 */                         /* 2 */                         /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */
412 #define MOD_SEL0_30_29     REV4(FM(SEL_ADGB_0),                 FM(SEL_ADGB_1),                 FM(SEL_ADGB_2),                 F_(0, 0))
413 #define MOD_SEL0_28             FM(SEL_DRIF0_0)                 FM(SEL_DRIF0_1)
414 #define MOD_SEL0_27_26     REV4(FM(SEL_FM_0),                   FM(SEL_FM_1),                   FM(SEL_FM_2),                   F_(0, 0))
415 #define MOD_SEL0_25             FM(SEL_FSO_0)                   FM(SEL_FSO_1)
416 #define MOD_SEL0_24             FM(SEL_HSCIF0_0)                FM(SEL_HSCIF0_1)
417 #define MOD_SEL0_23             FM(SEL_HSCIF1_0)                FM(SEL_HSCIF1_1)
418 #define MOD_SEL0_22             FM(SEL_HSCIF2_0)                FM(SEL_HSCIF2_1)
419 #define MOD_SEL0_21_20     REV4(FM(SEL_I2C1_0),                 FM(SEL_I2C1_1),                 FM(SEL_I2C1_2),                 FM(SEL_I2C1_3))
420 #define MOD_SEL0_19_18_17  REV8(FM(SEL_I2C2_0),                 FM(SEL_I2C2_1),                 FM(SEL_I2C2_2),                 FM(SEL_I2C2_3),         FM(SEL_I2C2_4),         F_(0, 0),       F_(0, 0),       F_(0, 0))
421 #define MOD_SEL0_16             FM(SEL_NDF_0)                   FM(SEL_NDF_1)
422 #define MOD_SEL0_15             FM(SEL_PWM0_0)                  FM(SEL_PWM0_1)
423 #define MOD_SEL0_14             FM(SEL_PWM1_0)                  FM(SEL_PWM1_1)
424 #define MOD_SEL0_13_12     REV4(FM(SEL_PWM2_0),                 FM(SEL_PWM2_1),                 FM(SEL_PWM2_2),                 F_(0, 0))
425 #define MOD_SEL0_11_10     REV4(FM(SEL_PWM3_0),                 FM(SEL_PWM3_1),                 FM(SEL_PWM3_2),                 F_(0, 0))
426 #define MOD_SEL0_9              FM(SEL_PWM4_0)                  FM(SEL_PWM4_1)
427 #define MOD_SEL0_8              FM(SEL_PWM5_0)                  FM(SEL_PWM5_1)
428 #define MOD_SEL0_7              FM(SEL_PWM6_0)                  FM(SEL_PWM6_1)
429 #define MOD_SEL0_6_5       REV4(FM(SEL_REMOCON_0),              FM(SEL_REMOCON_1),              FM(SEL_REMOCON_2),              F_(0, 0))
430 #define MOD_SEL0_4              FM(SEL_SCIF_0)                  FM(SEL_SCIF_1)
431 #define MOD_SEL0_3              FM(SEL_SCIF0_0)                 FM(SEL_SCIF0_1)
432 #define MOD_SEL0_2              FM(SEL_SCIF2_0)                 FM(SEL_SCIF2_1)
433 #define MOD_SEL0_1_0       REV4(FM(SEL_SPEED_PULSE_IF_0),       FM(SEL_SPEED_PULSE_IF_1),       FM(SEL_SPEED_PULSE_IF_2),       F_(0, 0))
434
435 /* MOD_SEL1 */                  /* 0 */                         /* 1 */                         /* 2 */                         /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */
436 #define MOD_SEL1_29             FM(SEL_TIMER_TMU_0)             FM(SEL_TIMER_TMU_1)
437 #define MOD_SEL1_28             FM(SEL_USB_20_CH0_0)            FM(SEL_USB_20_CH0_1)
438 #define MOD_SEL1_26             FM(SEL_DRIF2_0)                 FM(SEL_DRIF2_1)
439 #define MOD_SEL1_25             FM(SEL_DRIF3_0)                 FM(SEL_DRIF3_1)
440 #define MOD_SEL1_24_23_22  REV8(FM(SEL_HSCIF3_0),               FM(SEL_HSCIF3_1),               FM(SEL_HSCIF3_2),               FM(SEL_HSCIF3_3),       FM(SEL_HSCIF3_4),       F_(0, 0),       F_(0, 0),       F_(0, 0))
441 #define MOD_SEL1_21_20_19  REV8(FM(SEL_HSCIF4_0),               FM(SEL_HSCIF4_1),               FM(SEL_HSCIF4_2),               FM(SEL_HSCIF4_3),       FM(SEL_HSCIF4_4),       F_(0, 0),       F_(0, 0),       F_(0, 0))
442 #define MOD_SEL1_18             FM(SEL_I2C6_0)                  FM(SEL_I2C6_1)
443 #define MOD_SEL1_17             FM(SEL_I2C7_0)                  FM(SEL_I2C7_1)
444 #define MOD_SEL1_16             FM(SEL_MSIOF2_0)                FM(SEL_MSIOF2_1)
445 #define MOD_SEL1_15             FM(SEL_MSIOF3_0)                FM(SEL_MSIOF3_1)
446 #define MOD_SEL1_14_13     REV4(FM(SEL_SCIF3_0),                FM(SEL_SCIF3_1),                FM(SEL_SCIF3_2),                F_(0, 0))
447 #define MOD_SEL1_12_11     REV4(FM(SEL_SCIF4_0),                FM(SEL_SCIF4_1),                FM(SEL_SCIF4_2),                F_(0, 0))
448 #define MOD_SEL1_10_9      REV4(FM(SEL_SCIF5_0),                FM(SEL_SCIF5_1),                FM(SEL_SCIF5_2),                F_(0, 0))
449 #define MOD_SEL1_8              FM(SEL_VIN4_0)                  FM(SEL_VIN4_1)
450 #define MOD_SEL1_7              FM(SEL_VIN5_0)                  FM(SEL_VIN5_1)
451 #define MOD_SEL1_6_5       REV4(FM(SEL_ADGC_0),                 FM(SEL_ADGC_1),                 FM(SEL_ADGC_2),                 F_(0, 0))
452 #define MOD_SEL1_4              FM(SEL_SSI9_0)                  FM(SEL_SSI9_1)
453
454 #define PINMUX_MOD_SELS \
455 \
456 MOD_SEL0_30_29 \
457                         MOD_SEL1_29 \
458 MOD_SEL0_28             MOD_SEL1_28 \
459 MOD_SEL0_27_26 \
460                         MOD_SEL1_26 \
461 MOD_SEL0_25             MOD_SEL1_25 \
462 MOD_SEL0_24             MOD_SEL1_24_23_22 \
463 MOD_SEL0_23 \
464 MOD_SEL0_22 \
465 MOD_SEL0_21_20          MOD_SEL1_21_20_19 \
466 MOD_SEL0_19_18_17       MOD_SEL1_18 \
467                         MOD_SEL1_17 \
468 MOD_SEL0_16             MOD_SEL1_16 \
469 MOD_SEL0_15             MOD_SEL1_15 \
470 MOD_SEL0_14             MOD_SEL1_14_13 \
471 MOD_SEL0_13_12 \
472                         MOD_SEL1_12_11 \
473 MOD_SEL0_11_10 \
474                         MOD_SEL1_10_9 \
475 MOD_SEL0_9 \
476 MOD_SEL0_8              MOD_SEL1_8 \
477 MOD_SEL0_7              MOD_SEL1_7 \
478 MOD_SEL0_6_5            MOD_SEL1_6_5 \
479 MOD_SEL0_4              MOD_SEL1_4 \
480 MOD_SEL0_3 \
481 MOD_SEL0_2 \
482 MOD_SEL0_1_0
483
484 /*
485  * These pins are not able to be muxed but have other properties
486  * that can be set, such as pull-up/pull-down enable.
487  */
488 #define PINMUX_STATIC \
489         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
490         FM(AVB_TD3) \
491         FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
492         FM(ASEBRK) \
493         FM(MLB_REF)
494
495 enum {
496         PINMUX_RESERVED = 0,
497
498         PINMUX_DATA_BEGIN,
499         GP_ALL(DATA),
500         PINMUX_DATA_END,
501
502 #define F_(x, y)
503 #define FM(x)   FN_##x,
504         PINMUX_FUNCTION_BEGIN,
505         GP_ALL(FN),
506         PINMUX_GPSR
507         PINMUX_IPSR
508         PINMUX_MOD_SELS
509         PINMUX_FUNCTION_END,
510 #undef F_
511 #undef FM
512
513 #define F_(x, y)
514 #define FM(x)   x##_MARK,
515         PINMUX_MARK_BEGIN,
516         PINMUX_GPSR
517         PINMUX_IPSR
518         PINMUX_MOD_SELS
519         PINMUX_STATIC
520         PINMUX_MARK_END,
521 #undef F_
522 #undef FM
523 };
524
525 static const u16 pinmux_data[] = {
526         PINMUX_DATA_GP_ALL(),
527
528         PINMUX_SINGLE(CLKOUT),
529         PINMUX_SINGLE(AVB_PHY_INT),
530         PINMUX_SINGLE(AVB_RD3),
531         PINMUX_SINGLE(AVB_RXC),
532         PINMUX_SINGLE(AVB_RX_CTL),
533         PINMUX_SINGLE(QSPI0_SSL),
534
535         /* IPSR0 */
536         PINMUX_IPSR_GPSR(IP0_3_0,               QSPI0_SPCLK),
537         PINMUX_IPSR_MSEL(IP0_3_0,               HSCK4_A,        SEL_HSCIF4_0),
538
539         PINMUX_IPSR_GPSR(IP0_7_4,               QSPI0_MOSI_IO0),
540         PINMUX_IPSR_MSEL(IP0_7_4,               HCTS4_N_A,      SEL_HSCIF4_0),
541
542         PINMUX_IPSR_GPSR(IP0_11_8,              QSPI0_MISO_IO1),
543         PINMUX_IPSR_MSEL(IP0_11_8,              HRTS4_N_A,      SEL_HSCIF4_0),
544
545         PINMUX_IPSR_GPSR(IP0_15_12,             QSPI0_IO2),
546         PINMUX_IPSR_GPSR(IP0_15_12,             HTX4_A),
547
548         PINMUX_IPSR_GPSR(IP0_19_16,             QSPI0_IO3),
549         PINMUX_IPSR_MSEL(IP0_19_16,             HRX4_A,         SEL_HSCIF4_0),
550
551         PINMUX_IPSR_GPSR(IP0_23_20,             QSPI1_SPCLK),
552         PINMUX_IPSR_MSEL(IP0_23_20,             RIF2_CLK_A,     SEL_DRIF2_0),
553         PINMUX_IPSR_MSEL(IP0_23_20,             HSCK4_B,        SEL_HSCIF4_1),
554         PINMUX_IPSR_MSEL(IP0_23_20,             VI4_DATA0_A,    SEL_VIN4_0),
555
556         PINMUX_IPSR_GPSR(IP0_27_24,             QSPI1_MOSI_IO0),
557         PINMUX_IPSR_MSEL(IP0_27_24,             RIF2_SYNC_A,    SEL_DRIF2_0),
558         PINMUX_IPSR_GPSR(IP0_27_24,             HTX4_B),
559         PINMUX_IPSR_MSEL(IP0_27_24,             VI4_DATA1_A,    SEL_VIN4_0),
560
561         PINMUX_IPSR_GPSR(IP0_31_28,             QSPI1_MISO_IO1),
562         PINMUX_IPSR_MSEL(IP0_31_28,             RIF2_D0_A,      SEL_DRIF2_0),
563         PINMUX_IPSR_MSEL(IP0_31_28,             HRX4_B,         SEL_HSCIF4_1),
564         PINMUX_IPSR_MSEL(IP0_31_28,             VI4_DATA2_A,    SEL_VIN4_0),
565
566         /* IPSR1 */
567         PINMUX_IPSR_GPSR(IP1_3_0,               QSPI1_IO2),
568         PINMUX_IPSR_MSEL(IP1_3_0,               RIF2_D1_A,      SEL_DRIF2_0),
569         PINMUX_IPSR_GPSR(IP1_3_0,               HTX3_C),
570         PINMUX_IPSR_MSEL(IP1_3_0,               VI4_DATA3_A,    SEL_VIN4_0),
571
572         PINMUX_IPSR_GPSR(IP1_7_4,               QSPI1_IO3),
573         PINMUX_IPSR_MSEL(IP1_7_4,               RIF3_CLK_A,     SEL_DRIF3_0),
574         PINMUX_IPSR_MSEL(IP1_7_4,               HRX3_C,         SEL_HSCIF3_2),
575         PINMUX_IPSR_MSEL(IP1_7_4,               VI4_DATA4_A,    SEL_VIN4_0),
576
577         PINMUX_IPSR_GPSR(IP1_11_8,              QSPI1_SSL),
578         PINMUX_IPSR_MSEL(IP1_11_8,              RIF3_SYNC_A,    SEL_DRIF3_0),
579         PINMUX_IPSR_MSEL(IP1_11_8,              HSCK3_C,        SEL_HSCIF3_2),
580         PINMUX_IPSR_MSEL(IP1_11_8,              VI4_DATA5_A,    SEL_VIN4_0),
581
582         PINMUX_IPSR_GPSR(IP1_15_12,             RPC_INT_N),
583         PINMUX_IPSR_MSEL(IP1_15_12,             RIF3_D0_A,      SEL_DRIF3_0),
584         PINMUX_IPSR_MSEL(IP1_15_12,             HCTS3_N_C,      SEL_HSCIF3_2),
585         PINMUX_IPSR_MSEL(IP1_15_12,             VI4_DATA6_A,    SEL_VIN4_0),
586
587         PINMUX_IPSR_GPSR(IP1_19_16,             RPC_RESET_N),
588         PINMUX_IPSR_MSEL(IP1_19_16,             RIF3_D1_A,      SEL_DRIF3_0),
589         PINMUX_IPSR_MSEL(IP1_19_16,             HRTS3_N_C,      SEL_HSCIF3_2),
590         PINMUX_IPSR_MSEL(IP1_19_16,             VI4_DATA7_A,    SEL_VIN4_0),
591
592         PINMUX_IPSR_GPSR(IP1_23_20,             AVB_RD0),
593
594         PINMUX_IPSR_GPSR(IP1_27_24,             AVB_RD1),
595
596         PINMUX_IPSR_GPSR(IP1_31_28,             AVB_RD2),
597
598         /* IPSR2 */
599         PINMUX_IPSR_GPSR(IP2_3_0,               AVB_TXCREFCLK),
600
601         PINMUX_IPSR_GPSR(IP2_7_4,               AVB_MDIO),
602
603         PINMUX_IPSR_GPSR(IP2_11_8,              AVB_MDC),
604
605         PINMUX_IPSR_GPSR(IP2_15_12,             BS_N),
606         PINMUX_IPSR_MSEL(IP2_15_12,             PWM0_A,         SEL_PWM0_0),
607         PINMUX_IPSR_GPSR(IP2_15_12,             AVB_MAGIC),
608         PINMUX_IPSR_GPSR(IP2_15_12,             VI4_CLK),
609         PINMUX_IPSR_GPSR(IP2_15_12,             TX3_C),
610         PINMUX_IPSR_MSEL(IP2_15_12,             VI5_CLK_B,      SEL_VIN5_1),
611
612         PINMUX_IPSR_GPSR(IP2_19_16,             RD_N),
613         PINMUX_IPSR_MSEL(IP2_19_16,             PWM1_A,         SEL_PWM1_0),
614         PINMUX_IPSR_GPSR(IP2_19_16,             AVB_LINK),
615         PINMUX_IPSR_GPSR(IP2_19_16,             VI4_FIELD),
616         PINMUX_IPSR_MSEL(IP2_19_16,             RX3_C,          SEL_SCIF3_2),
617         PINMUX_IPSR_GPSR(IP2_19_16,             FSCLKST2_N_A),
618         PINMUX_IPSR_MSEL(IP2_19_16,             VI5_DATA0_B,    SEL_VIN5_1),
619
620         PINMUX_IPSR_GPSR(IP2_23_20,             RD_WR_N),
621         PINMUX_IPSR_MSEL(IP2_23_20,             SCL7_A,         SEL_I2C7_0),
622         PINMUX_IPSR_GPSR(IP2_23_20,             AVB_AVTP_MATCH_A),
623         PINMUX_IPSR_GPSR(IP2_23_20,             VI4_VSYNC_N),
624         PINMUX_IPSR_GPSR(IP2_23_20,             TX5_B),
625         PINMUX_IPSR_MSEL(IP2_23_20,             SCK3_C,         SEL_SCIF3_2),
626         PINMUX_IPSR_MSEL(IP2_23_20,             PWM5_A,         SEL_PWM5_0),
627
628         PINMUX_IPSR_GPSR(IP2_27_24,             EX_WAIT0),
629         PINMUX_IPSR_MSEL(IP2_27_24,             SDA7_A,         SEL_I2C7_0),
630         PINMUX_IPSR_GPSR(IP2_27_24,             AVB_AVTP_CAPTURE_A),
631         PINMUX_IPSR_GPSR(IP2_27_24,             VI4_HSYNC_N),
632         PINMUX_IPSR_MSEL(IP2_27_24,             RX5_B,          SEL_SCIF5_1),
633         PINMUX_IPSR_MSEL(IP2_27_24,             PWM6_A,         SEL_PWM6_0),
634
635         PINMUX_IPSR_GPSR(IP2_31_28,             A0),
636         PINMUX_IPSR_GPSR(IP2_31_28,             IRQ0),
637         PINMUX_IPSR_MSEL(IP2_31_28,             PWM2_A,         SEL_PWM2_0),
638         PINMUX_IPSR_MSEL(IP2_31_28,             MSIOF3_SS1_B,   SEL_MSIOF3_1),
639         PINMUX_IPSR_MSEL(IP2_31_28,             VI5_CLK_A,      SEL_VIN5_0),
640         PINMUX_IPSR_GPSR(IP2_31_28,             DU_CDE),
641         PINMUX_IPSR_MSEL(IP2_31_28,             HRX3_D,         SEL_HSCIF3_3),
642         PINMUX_IPSR_GPSR(IP2_31_28,             IERX),
643         PINMUX_IPSR_GPSR(IP2_31_28,             QSTB_QHE),
644
645         /* IPSR3 */
646         PINMUX_IPSR_GPSR(IP3_3_0,               A1),
647         PINMUX_IPSR_GPSR(IP3_3_0,               IRQ1),
648         PINMUX_IPSR_MSEL(IP3_3_0,               PWM3_A,         SEL_PWM3_0),
649         PINMUX_IPSR_GPSR(IP3_3_0,               DU_DOTCLKIN1),
650         PINMUX_IPSR_MSEL(IP3_3_0,               VI5_DATA0_A,    SEL_VIN5_0),
651         PINMUX_IPSR_GPSR(IP3_3_0,               DU_DISP_CDE),
652         PINMUX_IPSR_MSEL(IP3_3_0,               SDA6_B,         SEL_I2C6_1),
653         PINMUX_IPSR_GPSR(IP3_3_0,               IETX),
654         PINMUX_IPSR_GPSR(IP3_3_0,               QCPV_QDE),
655
656         PINMUX_IPSR_GPSR(IP3_7_4,               A2),
657         PINMUX_IPSR_GPSR(IP3_7_4,               IRQ2),
658         PINMUX_IPSR_GPSR(IP3_7_4,               AVB_AVTP_PPS),
659         PINMUX_IPSR_GPSR(IP3_7_4,               VI4_CLKENB),
660         PINMUX_IPSR_MSEL(IP3_7_4,               VI5_DATA1_A,    SEL_VIN5_0),
661         PINMUX_IPSR_GPSR(IP3_7_4,               DU_DISP),
662         PINMUX_IPSR_MSEL(IP3_7_4,               SCL6_B,         SEL_I2C6_1),
663         PINMUX_IPSR_GPSR(IP3_7_4,               QSTVB_QVE),
664
665         PINMUX_IPSR_GPSR(IP3_11_8,              A3),
666         PINMUX_IPSR_MSEL(IP3_11_8,              CTS4_N_A,       SEL_SCIF4_0),
667         PINMUX_IPSR_MSEL(IP3_11_8,              PWM4_A,         SEL_PWM4_0),
668         PINMUX_IPSR_GPSR(IP3_11_8,              VI4_DATA12),
669         PINMUX_IPSR_GPSR(IP3_11_8,              DU_DOTCLKOUT0),
670         PINMUX_IPSR_GPSR(IP3_11_8,              HTX3_D),
671         PINMUX_IPSR_GPSR(IP3_11_8,              IECLK),
672         PINMUX_IPSR_GPSR(IP3_11_8,              LCDOUT12),
673
674         PINMUX_IPSR_GPSR(IP3_15_12,             A4),
675         PINMUX_IPSR_MSEL(IP3_15_12,             RTS4_N_A,       SEL_SCIF4_0),
676         PINMUX_IPSR_MSEL(IP3_15_12,             MSIOF3_SYNC_B,  SEL_MSIOF3_1),
677         PINMUX_IPSR_GPSR(IP3_15_12,             VI4_DATA8),
678         PINMUX_IPSR_MSEL(IP3_15_12,             PWM2_B,         SEL_PWM2_1),
679         PINMUX_IPSR_GPSR(IP3_15_12,             DU_DG4),
680         PINMUX_IPSR_MSEL(IP3_15_12,             RIF2_CLK_B,     SEL_DRIF2_1),
681
682         PINMUX_IPSR_GPSR(IP3_19_16,             A5),
683         PINMUX_IPSR_MSEL(IP3_19_16,             SCK4_A,         SEL_SCIF4_0),
684         PINMUX_IPSR_MSEL(IP3_19_16,             MSIOF3_SCK_B,   SEL_MSIOF3_1),
685         PINMUX_IPSR_GPSR(IP3_19_16,             VI4_DATA9),
686         PINMUX_IPSR_MSEL(IP3_19_16,             PWM3_B,         SEL_PWM3_1),
687         PINMUX_IPSR_MSEL(IP3_19_16,             RIF2_SYNC_B,    SEL_DRIF2_1),
688         PINMUX_IPSR_GPSR(IP3_19_16,             QPOLA),
689
690         PINMUX_IPSR_GPSR(IP3_23_20,             A6),
691         PINMUX_IPSR_MSEL(IP3_23_20,             RX4_A,          SEL_SCIF4_0),
692         PINMUX_IPSR_MSEL(IP3_23_20,             MSIOF3_RXD_B,   SEL_MSIOF3_1),
693         PINMUX_IPSR_GPSR(IP3_23_20,             VI4_DATA10),
694         PINMUX_IPSR_MSEL(IP3_23_20,             RIF2_D0_B,      SEL_DRIF2_1),
695
696         PINMUX_IPSR_GPSR(IP3_27_24,             A7),
697         PINMUX_IPSR_GPSR(IP3_27_24,             TX4_A),
698         PINMUX_IPSR_GPSR(IP3_27_24,             MSIOF3_TXD_B),
699         PINMUX_IPSR_GPSR(IP3_27_24,             VI4_DATA11),
700         PINMUX_IPSR_MSEL(IP3_27_24,             RIF2_D1_B,      SEL_DRIF2_1),
701
702         PINMUX_IPSR_GPSR(IP3_31_28,             A8),
703         PINMUX_IPSR_MSEL(IP3_31_28,             SDA6_A,         SEL_I2C6_0),
704         PINMUX_IPSR_MSEL(IP3_31_28,             RX3_B,          SEL_SCIF3_1),
705         PINMUX_IPSR_MSEL(IP3_31_28,             HRX4_C,         SEL_HSCIF4_2),
706         PINMUX_IPSR_MSEL(IP3_31_28,             VI5_HSYNC_N_A,  SEL_VIN5_0),
707         PINMUX_IPSR_GPSR(IP3_31_28,             DU_HSYNC),
708         PINMUX_IPSR_MSEL(IP3_31_28,             VI4_DATA0_B,    SEL_VIN4_1),
709         PINMUX_IPSR_GPSR(IP3_31_28,             QSTH_QHS),
710
711         /* IPSR4 */
712         PINMUX_IPSR_GPSR(IP4_3_0,               A9),
713         PINMUX_IPSR_GPSR(IP4_3_0,               TX5_A),
714         PINMUX_IPSR_GPSR(IP4_3_0,               IRQ3),
715         PINMUX_IPSR_GPSR(IP4_3_0,               VI4_DATA16),
716         PINMUX_IPSR_MSEL(IP4_3_0,               VI5_VSYNC_N_A,  SEL_VIN5_0),
717         PINMUX_IPSR_GPSR(IP4_3_0,               DU_DG7),
718         PINMUX_IPSR_GPSR(IP4_3_0,               LCDOUT15),
719
720         PINMUX_IPSR_GPSR(IP4_7_4,               A10),
721         PINMUX_IPSR_GPSR(IP4_7_4,               IRQ4),
722         PINMUX_IPSR_MSEL(IP4_7_4,               MSIOF2_SYNC_B,  SEL_MSIOF2_1),
723         PINMUX_IPSR_GPSR(IP4_7_4,               VI4_DATA13),
724         PINMUX_IPSR_MSEL(IP4_7_4,               VI5_FIELD_A,    SEL_VIN5_0),
725         PINMUX_IPSR_GPSR(IP4_7_4,               DU_DG5),
726         PINMUX_IPSR_GPSR(IP4_7_4,               FSCLKST2_N_B),
727         PINMUX_IPSR_GPSR(IP4_7_4,               LCDOUT13),
728
729         PINMUX_IPSR_GPSR(IP4_11_8,              A11),
730         PINMUX_IPSR_MSEL(IP4_11_8,              SCL6_A,         SEL_I2C6_0),
731         PINMUX_IPSR_GPSR(IP4_11_8,              TX3_B),
732         PINMUX_IPSR_GPSR(IP4_11_8,              HTX4_C),
733         PINMUX_IPSR_GPSR(IP4_11_8,              DU_VSYNC),
734         PINMUX_IPSR_MSEL(IP4_11_8,              VI4_DATA1_B,    SEL_VIN4_1),
735         PINMUX_IPSR_GPSR(IP4_11_8,              QSTVA_QVS),
736
737         PINMUX_IPSR_GPSR(IP4_15_12,             A12),
738         PINMUX_IPSR_MSEL(IP4_15_12,             RX5_A,          SEL_SCIF5_0),
739         PINMUX_IPSR_GPSR(IP4_15_12,             MSIOF2_SS2_B),
740         PINMUX_IPSR_GPSR(IP4_15_12,             VI4_DATA17),
741         PINMUX_IPSR_MSEL(IP4_15_12,             VI5_DATA3_A,    SEL_VIN5_0),
742         PINMUX_IPSR_GPSR(IP4_15_12,             DU_DG6),
743         PINMUX_IPSR_GPSR(IP4_15_12,             LCDOUT14),
744
745         PINMUX_IPSR_GPSR(IP4_19_16,             A13),
746         PINMUX_IPSR_MSEL(IP4_19_16,             SCK5_A,         SEL_SCIF5_0),
747         PINMUX_IPSR_MSEL(IP4_19_16,             MSIOF2_SCK_B,   SEL_MSIOF2_1),
748         PINMUX_IPSR_GPSR(IP4_19_16,             VI4_DATA14),
749         PINMUX_IPSR_MSEL(IP4_19_16,             HRX4_D,         SEL_HSCIF4_3),
750         PINMUX_IPSR_GPSR(IP4_19_16,             DU_DB2),
751         PINMUX_IPSR_GPSR(IP4_19_16,             LCDOUT2),
752
753         PINMUX_IPSR_GPSR(IP4_23_20,             A14),
754         PINMUX_IPSR_GPSR(IP4_23_20,             MSIOF1_SS1),
755         PINMUX_IPSR_MSEL(IP4_23_20,             MSIOF2_RXD_B,   SEL_MSIOF2_1),
756         PINMUX_IPSR_GPSR(IP4_23_20,             VI4_DATA15),
757         PINMUX_IPSR_GPSR(IP4_23_20,             HTX4_D),
758         PINMUX_IPSR_GPSR(IP4_23_20,             DU_DB3),
759         PINMUX_IPSR_GPSR(IP4_23_20,             LCDOUT3),
760
761         PINMUX_IPSR_GPSR(IP4_27_24,             A15),
762         PINMUX_IPSR_GPSR(IP4_27_24,             MSIOF1_SS2),
763         PINMUX_IPSR_GPSR(IP4_27_24,             MSIOF2_TXD_B),
764         PINMUX_IPSR_GPSR(IP4_27_24,             VI4_DATA18),
765         PINMUX_IPSR_MSEL(IP4_27_24,             VI5_DATA4_A,    SEL_VIN5_0),
766         PINMUX_IPSR_GPSR(IP4_27_24,             DU_DB4),
767         PINMUX_IPSR_GPSR(IP4_27_24,             LCDOUT4),
768
769         PINMUX_IPSR_GPSR(IP4_31_28,             A16),
770         PINMUX_IPSR_GPSR(IP4_31_28,             MSIOF1_SYNC),
771         PINMUX_IPSR_GPSR(IP4_31_28,             MSIOF2_SS1_B),
772         PINMUX_IPSR_GPSR(IP4_31_28,             VI4_DATA19),
773         PINMUX_IPSR_MSEL(IP4_31_28,             VI5_DATA5_A,    SEL_VIN5_0),
774         PINMUX_IPSR_GPSR(IP4_31_28,             DU_DB5),
775         PINMUX_IPSR_GPSR(IP4_31_28,             LCDOUT5),
776
777         /* IPSR5 */
778         PINMUX_IPSR_GPSR(IP5_3_0,               A17),
779         PINMUX_IPSR_GPSR(IP5_3_0,               MSIOF1_RXD),
780         PINMUX_IPSR_GPSR(IP5_3_0,               VI4_DATA20),
781         PINMUX_IPSR_MSEL(IP5_3_0,               VI5_DATA6_A,    SEL_VIN5_0),
782         PINMUX_IPSR_GPSR(IP5_3_0,               DU_DB6),
783         PINMUX_IPSR_GPSR(IP5_3_0,               LCDOUT6),
784
785         PINMUX_IPSR_GPSR(IP5_7_4,               A18),
786         PINMUX_IPSR_GPSR(IP5_7_4,               MSIOF1_TXD),
787         PINMUX_IPSR_GPSR(IP5_7_4,               VI4_DATA21),
788         PINMUX_IPSR_MSEL(IP5_7_4,               VI5_DATA7_A,    SEL_VIN5_0),
789         PINMUX_IPSR_GPSR(IP5_7_4,               DU_DB0),
790         PINMUX_IPSR_MSEL(IP5_7_4,               HRX4_E,         SEL_HSCIF4_4),
791         PINMUX_IPSR_GPSR(IP5_7_4,               LCDOUT0),
792
793         PINMUX_IPSR_GPSR(IP5_11_8,              A19),
794         PINMUX_IPSR_GPSR(IP5_11_8,              MSIOF1_SCK),
795         PINMUX_IPSR_GPSR(IP5_11_8,              VI4_DATA22),
796         PINMUX_IPSR_MSEL(IP5_11_8,              VI5_DATA2_A,    SEL_VIN5_0),
797         PINMUX_IPSR_GPSR(IP5_11_8,              DU_DB1),
798         PINMUX_IPSR_GPSR(IP5_11_8,              HTX4_E),
799         PINMUX_IPSR_GPSR(IP5_11_8,              LCDOUT1),
800
801         PINMUX_IPSR_GPSR(IP5_15_12,             CS0_N),
802         PINMUX_IPSR_GPSR(IP5_15_12,             SCL5),
803         PINMUX_IPSR_GPSR(IP5_15_12,             DU_DR0),
804         PINMUX_IPSR_MSEL(IP5_15_12,             VI4_DATA2_B,    SEL_VIN4_1),
805         PINMUX_IPSR_GPSR(IP5_15_12,             LCDOUT16),
806
807         PINMUX_IPSR_GPSR(IP5_19_16,             WE0_N),
808         PINMUX_IPSR_GPSR(IP5_19_16,             SDA5),
809         PINMUX_IPSR_GPSR(IP5_19_16,             DU_DR1),
810         PINMUX_IPSR_MSEL(IP5_19_16,             VI4_DATA3_B,    SEL_VIN4_1),
811         PINMUX_IPSR_GPSR(IP5_19_16,             LCDOUT17),
812
813         PINMUX_IPSR_GPSR(IP5_23_20,             D0),
814         PINMUX_IPSR_MSEL(IP5_23_20,             MSIOF3_SCK_A,   SEL_MSIOF3_0),
815         PINMUX_IPSR_GPSR(IP5_23_20,             DU_DR2),
816         PINMUX_IPSR_MSEL(IP5_23_20,             CTS4_N_C,       SEL_SCIF4_2),
817         PINMUX_IPSR_GPSR(IP5_23_20,             LCDOUT18),
818
819         PINMUX_IPSR_GPSR(IP5_27_24,             D1),
820         PINMUX_IPSR_MSEL(IP5_27_24,             MSIOF3_SYNC_A,  SEL_MSIOF3_0),
821         PINMUX_IPSR_MSEL(IP5_27_24,             SCK3_A,         SEL_SCIF3_0),
822         PINMUX_IPSR_GPSR(IP5_27_24,             VI4_DATA23),
823         PINMUX_IPSR_MSEL(IP5_27_24,             VI5_CLKENB_A,   SEL_VIN5_0),
824         PINMUX_IPSR_GPSR(IP5_27_24,             DU_DB7),
825         PINMUX_IPSR_MSEL(IP5_27_24,             RTS4_N_C,       SEL_SCIF4_2),
826         PINMUX_IPSR_GPSR(IP5_27_24,             LCDOUT7),
827
828         PINMUX_IPSR_GPSR(IP5_31_28,             D2),
829         PINMUX_IPSR_MSEL(IP5_31_28,             MSIOF3_RXD_A,   SEL_MSIOF3_0),
830         PINMUX_IPSR_MSEL(IP5_31_28,             RX5_C,          SEL_SCIF5_2),
831         PINMUX_IPSR_MSEL(IP5_31_28,             VI5_DATA14_A,   SEL_VIN5_0),
832         PINMUX_IPSR_GPSR(IP5_31_28,             DU_DR3),
833         PINMUX_IPSR_MSEL(IP5_31_28,             RX4_C,          SEL_SCIF4_2),
834         PINMUX_IPSR_GPSR(IP5_31_28,             LCDOUT19),
835
836         /* IPSR6 */
837         PINMUX_IPSR_GPSR(IP6_3_0,               D3),
838         PINMUX_IPSR_GPSR(IP6_3_0,               MSIOF3_TXD_A),
839         PINMUX_IPSR_GPSR(IP6_3_0,               TX5_C),
840         PINMUX_IPSR_MSEL(IP6_3_0,               VI5_DATA15_A,   SEL_VIN5_0),
841         PINMUX_IPSR_GPSR(IP6_3_0,               DU_DR4),
842         PINMUX_IPSR_GPSR(IP6_3_0,               TX4_C),
843         PINMUX_IPSR_GPSR(IP6_3_0,               LCDOUT20),
844
845         PINMUX_IPSR_GPSR(IP6_7_4,               D4),
846         PINMUX_IPSR_GPSR(IP6_7_4,               CANFD1_TX),
847         PINMUX_IPSR_MSEL(IP6_7_4,               HSCK3_B,        SEL_HSCIF3_1),
848         PINMUX_IPSR_GPSR(IP6_7_4,               CAN1_TX),
849         PINMUX_IPSR_MSEL(IP6_7_4,               RTS3_N_A,       SEL_SCIF3_0),
850         PINMUX_IPSR_GPSR(IP6_7_4,               MSIOF3_SS2_A),
851         PINMUX_IPSR_MSEL(IP6_7_4,               VI5_DATA1_B,    SEL_VIN5_1),
852
853         PINMUX_IPSR_GPSR(IP6_11_8,              D5),
854         PINMUX_IPSR_MSEL(IP6_11_8,              RX3_A,          SEL_SCIF3_0),
855         PINMUX_IPSR_MSEL(IP6_11_8,              HRX3_B,         SEL_HSCIF3_1),
856         PINMUX_IPSR_GPSR(IP6_11_8,              DU_DR5),
857         PINMUX_IPSR_MSEL(IP6_11_8,              VI4_DATA4_B,    SEL_VIN4_1),
858         PINMUX_IPSR_GPSR(IP6_11_8,              LCDOUT21),
859
860         PINMUX_IPSR_GPSR(IP6_15_12,             D6),
861         PINMUX_IPSR_GPSR(IP6_15_12,             TX3_A),
862         PINMUX_IPSR_GPSR(IP6_15_12,             HTX3_B),
863         PINMUX_IPSR_GPSR(IP6_15_12,             DU_DR6),
864         PINMUX_IPSR_MSEL(IP6_15_12,             VI4_DATA5_B,    SEL_VIN4_1),
865         PINMUX_IPSR_GPSR(IP6_15_12,             LCDOUT22),
866
867         PINMUX_IPSR_GPSR(IP6_19_16,             D7),
868         PINMUX_IPSR_GPSR(IP6_19_16,             CANFD1_RX),
869         PINMUX_IPSR_GPSR(IP6_19_16,             IRQ5),
870         PINMUX_IPSR_GPSR(IP6_19_16,             CAN1_RX),
871         PINMUX_IPSR_MSEL(IP6_19_16,             CTS3_N_A,       SEL_SCIF3_0),
872         PINMUX_IPSR_MSEL(IP6_19_16,             VI5_DATA2_B,    SEL_VIN5_1),
873
874         PINMUX_IPSR_GPSR(IP6_23_20,             D8),
875         PINMUX_IPSR_MSEL(IP6_23_20,             MSIOF2_SCK_A,   SEL_MSIOF2_0),
876         PINMUX_IPSR_MSEL(IP6_23_20,             SCK4_B,         SEL_SCIF4_1),
877         PINMUX_IPSR_MSEL(IP6_23_20,             VI5_DATA12_A,   SEL_VIN5_0),
878         PINMUX_IPSR_GPSR(IP6_23_20,             DU_DR7),
879         PINMUX_IPSR_MSEL(IP6_23_20,             RIF3_CLK_B,     SEL_DRIF3_1),
880         PINMUX_IPSR_MSEL(IP6_23_20,             HCTS3_N_E,      SEL_HSCIF3_4),
881         PINMUX_IPSR_GPSR(IP6_23_20,             LCDOUT23),
882
883         PINMUX_IPSR_GPSR(IP6_27_24,             D9),
884         PINMUX_IPSR_MSEL(IP6_27_24,             MSIOF2_SYNC_A,  SEL_MSIOF2_0),
885         PINMUX_IPSR_MSEL(IP6_27_24,             VI5_DATA10_A,   SEL_VIN5_0),
886         PINMUX_IPSR_GPSR(IP6_27_24,             DU_DG0),
887         PINMUX_IPSR_MSEL(IP6_27_24,             RIF3_SYNC_B,    SEL_DRIF3_1),
888         PINMUX_IPSR_MSEL(IP6_27_24,             HRX3_E,         SEL_HSCIF3_4),
889         PINMUX_IPSR_GPSR(IP6_27_24,             LCDOUT8),
890
891         PINMUX_IPSR_GPSR(IP6_31_28,             D10),
892         PINMUX_IPSR_MSEL(IP6_31_28,             MSIOF2_RXD_A,   SEL_MSIOF2_0),
893         PINMUX_IPSR_MSEL(IP6_31_28,             VI5_DATA13_A,   SEL_VIN5_0),
894         PINMUX_IPSR_GPSR(IP6_31_28,             DU_DG1),
895         PINMUX_IPSR_MSEL(IP6_31_28,             RIF3_D0_B,      SEL_DRIF3_1),
896         PINMUX_IPSR_GPSR(IP6_31_28,             HTX3_E),
897         PINMUX_IPSR_GPSR(IP6_31_28,             LCDOUT9),
898
899         /* IPSR7 */
900         PINMUX_IPSR_GPSR(IP7_3_0,               D11),
901         PINMUX_IPSR_GPSR(IP7_3_0,               MSIOF2_TXD_A),
902         PINMUX_IPSR_MSEL(IP7_3_0,               VI5_DATA11_A,   SEL_VIN5_0),
903         PINMUX_IPSR_GPSR(IP7_3_0,               DU_DG2),
904         PINMUX_IPSR_MSEL(IP7_3_0,               RIF3_D1_B,      SEL_DRIF3_1),
905         PINMUX_IPSR_MSEL(IP7_3_0,               HRTS3_N_E,      SEL_HSCIF3_4),
906         PINMUX_IPSR_GPSR(IP7_3_0,               LCDOUT10),
907
908         PINMUX_IPSR_GPSR(IP7_7_4,               D12),
909         PINMUX_IPSR_GPSR(IP7_7_4,               CANFD0_TX),
910         PINMUX_IPSR_GPSR(IP7_7_4,               TX4_B),
911         PINMUX_IPSR_GPSR(IP7_7_4,               CAN0_TX),
912         PINMUX_IPSR_MSEL(IP7_7_4,               VI5_DATA8_A,    SEL_VIN5_0),
913         PINMUX_IPSR_MSEL(IP7_7_4,               VI5_DATA3_B,    SEL_VIN5_1),
914
915         PINMUX_IPSR_GPSR(IP7_11_8,              D13),
916         PINMUX_IPSR_GPSR(IP7_11_8,              CANFD0_RX),
917         PINMUX_IPSR_MSEL(IP7_11_8,              RX4_B,          SEL_SCIF4_1),
918         PINMUX_IPSR_GPSR(IP7_11_8,              CAN0_RX),
919         PINMUX_IPSR_MSEL(IP7_11_8,              VI5_DATA9_A,    SEL_VIN5_0),
920         PINMUX_IPSR_MSEL(IP7_11_8,              SCL7_B,         SEL_I2C7_1),
921         PINMUX_IPSR_MSEL(IP7_11_8,              VI5_DATA4_B,    SEL_VIN5_1),
922
923         PINMUX_IPSR_GPSR(IP7_15_12,             D14),
924         PINMUX_IPSR_GPSR(IP7_15_12,             CAN_CLK),
925         PINMUX_IPSR_MSEL(IP7_15_12,             HRX3_A,         SEL_HSCIF3_0),
926         PINMUX_IPSR_GPSR(IP7_15_12,             MSIOF2_SS2_A),
927         PINMUX_IPSR_MSEL(IP7_15_12,             SDA7_B,         SEL_I2C7_1),
928         PINMUX_IPSR_MSEL(IP7_15_12,             VI5_DATA5_B,    SEL_VIN5_1),
929
930         PINMUX_IPSR_GPSR(IP7_19_16,             D15),
931         PINMUX_IPSR_GPSR(IP7_19_16,             MSIOF2_SS1_A),
932         PINMUX_IPSR_GPSR(IP7_19_16,             HTX3_A),
933         PINMUX_IPSR_GPSR(IP7_19_16,             MSIOF3_SS1_A),
934         PINMUX_IPSR_GPSR(IP7_19_16,             DU_DG3),
935         PINMUX_IPSR_GPSR(IP7_19_16,             LCDOUT11),
936
937         PINMUX_IPSR_GPSR(IP7_23_20,             SCL4),
938         PINMUX_IPSR_GPSR(IP7_23_20,             CS1_N_A26),
939         PINMUX_IPSR_GPSR(IP7_23_20,             DU_DOTCLKIN0),
940         PINMUX_IPSR_MSEL(IP7_23_20,             VI4_DATA6_B,    SEL_VIN4_1),
941         PINMUX_IPSR_MSEL(IP7_23_20,             VI5_DATA6_B,    SEL_VIN5_1),
942         PINMUX_IPSR_GPSR(IP7_23_20,             QCLK),
943
944         PINMUX_IPSR_GPSR(IP7_27_24,             SDA4),
945         PINMUX_IPSR_GPSR(IP7_27_24,             WE1_N),
946         PINMUX_IPSR_MSEL(IP7_27_24,             VI4_DATA7_B,    SEL_VIN4_1),
947         PINMUX_IPSR_MSEL(IP7_27_24,             VI5_DATA7_B,    SEL_VIN5_1),
948         PINMUX_IPSR_GPSR(IP7_27_24,             QPOLB),
949
950         PINMUX_IPSR_GPSR(IP7_31_28,             SD0_CLK),
951         PINMUX_IPSR_GPSR(IP7_31_28,             NFDATA8),
952         PINMUX_IPSR_MSEL(IP7_31_28,             SCL1_C,         SEL_I2C1_2),
953         PINMUX_IPSR_MSEL(IP7_31_28,             HSCK1_B,        SEL_HSCIF1_1),
954         PINMUX_IPSR_MSEL(IP7_31_28,             SDA2_E,         SEL_I2C2_4),
955         PINMUX_IPSR_MSEL(IP7_31_28,             FMCLK_B,        SEL_FM_1),
956
957         /* IPSR8 */
958         PINMUX_IPSR_GPSR(IP8_3_0,               SD0_CMD),
959         PINMUX_IPSR_GPSR(IP8_3_0,               NFDATA9),
960         PINMUX_IPSR_MSEL(IP8_3_0,               HRX1_B,         SEL_HSCIF1_1),
961         PINMUX_IPSR_MSEL(IP8_3_0,               SPEEDIN_B,      SEL_SPEED_PULSE_IF_1),
962
963         PINMUX_IPSR_GPSR(IP8_7_4,               SD0_DAT0),
964         PINMUX_IPSR_GPSR(IP8_7_4,               NFDATA10),
965         PINMUX_IPSR_GPSR(IP8_7_4,               HTX1_B),
966         PINMUX_IPSR_MSEL(IP8_7_4,               REMOCON_B,      SEL_REMOCON_1),
967
968         PINMUX_IPSR_GPSR(IP8_11_8,              SD0_DAT1),
969         PINMUX_IPSR_GPSR(IP8_11_8,              NFDATA11),
970         PINMUX_IPSR_MSEL(IP8_11_8,              SDA2_C,         SEL_I2C2_2),
971         PINMUX_IPSR_MSEL(IP8_11_8,              HCTS1_N_B,      SEL_HSCIF1_1),
972         PINMUX_IPSR_MSEL(IP8_11_8,              FMIN_B,         SEL_FM_1),
973
974         PINMUX_IPSR_GPSR(IP8_15_12,             SD0_DAT2),
975         PINMUX_IPSR_GPSR(IP8_15_12,             NFDATA12),
976         PINMUX_IPSR_MSEL(IP8_15_12,             SCL2_C,         SEL_I2C2_2),
977         PINMUX_IPSR_MSEL(IP8_15_12,             HRTS1_N_B,      SEL_HSCIF1_1),
978         PINMUX_IPSR_GPSR(IP8_15_12,             BPFCLK_B),
979
980         PINMUX_IPSR_GPSR(IP8_19_16,             SD0_DAT3),
981         PINMUX_IPSR_GPSR(IP8_19_16,             NFDATA13),
982         PINMUX_IPSR_MSEL(IP8_19_16,             SDA1_C,         SEL_I2C1_2),
983         PINMUX_IPSR_MSEL(IP8_19_16,             SCL2_E,         SEL_I2C2_4),
984         PINMUX_IPSR_MSEL(IP8_19_16,             SPEEDIN_C,      SEL_SPEED_PULSE_IF_2),
985         PINMUX_IPSR_MSEL(IP8_19_16,             REMOCON_C,      SEL_REMOCON_2),
986
987         PINMUX_IPSR_GPSR(IP8_23_20,             SD1_CLK),
988         PINMUX_IPSR_MSEL(IP8_23_20,             NFDATA14_B,     SEL_NDF_1),
989
990         PINMUX_IPSR_GPSR(IP8_27_24,             SD1_CMD),
991         PINMUX_IPSR_MSEL(IP8_27_24,             NFDATA15_B,     SEL_NDF_1),
992
993         PINMUX_IPSR_GPSR(IP8_31_28,             SD1_DAT0),
994         PINMUX_IPSR_MSEL(IP8_31_28,             NFWP_N_B,       SEL_NDF_1),
995
996         /* IPSR9 */
997         PINMUX_IPSR_GPSR(IP9_3_0,               SD1_DAT1),
998         PINMUX_IPSR_MSEL(IP9_3_0,               NFCE_N_B,       SEL_NDF_1),
999
1000         PINMUX_IPSR_GPSR(IP9_7_4,               SD1_DAT2),
1001         PINMUX_IPSR_MSEL(IP9_7_4,               NFALE_B,        SEL_NDF_1),
1002
1003         PINMUX_IPSR_GPSR(IP9_11_8,              SD1_DAT3),
1004         PINMUX_IPSR_MSEL(IP9_11_8,              NFRB_N_B,       SEL_NDF_1),
1005
1006         PINMUX_IPSR_GPSR(IP9_15_12,             SD3_CLK),
1007         PINMUX_IPSR_GPSR(IP9_15_12,             NFWE_N),
1008
1009         PINMUX_IPSR_GPSR(IP9_19_16,             SD3_CMD),
1010         PINMUX_IPSR_GPSR(IP9_19_16,             NFRE_N),
1011
1012         PINMUX_IPSR_GPSR(IP9_23_20,             SD3_DAT0),
1013         PINMUX_IPSR_GPSR(IP9_23_20,             NFDATA0),
1014
1015         PINMUX_IPSR_GPSR(IP9_27_24,             SD3_DAT1),
1016         PINMUX_IPSR_GPSR(IP9_27_24,             NFDATA1),
1017
1018         PINMUX_IPSR_GPSR(IP9_31_28,             SD3_DAT2),
1019         PINMUX_IPSR_GPSR(IP9_31_28,             NFDATA2),
1020
1021         /* IPSR10 */
1022         PINMUX_IPSR_GPSR(IP10_3_0,              SD3_DAT3),
1023         PINMUX_IPSR_GPSR(IP10_3_0,              NFDATA3),
1024
1025         PINMUX_IPSR_GPSR(IP10_7_4,              SD3_DAT4),
1026         PINMUX_IPSR_GPSR(IP10_7_4,              NFDATA4),
1027
1028         PINMUX_IPSR_GPSR(IP10_11_8,             SD3_DAT5),
1029         PINMUX_IPSR_GPSR(IP10_11_8,             NFDATA5),
1030
1031         PINMUX_IPSR_GPSR(IP10_15_12,            SD3_DAT6),
1032         PINMUX_IPSR_GPSR(IP10_15_12,            NFDATA6),
1033
1034         PINMUX_IPSR_GPSR(IP10_19_16,            SD3_DAT7),
1035         PINMUX_IPSR_GPSR(IP10_19_16,            NFDATA7),
1036
1037         PINMUX_IPSR_GPSR(IP10_23_20,            SD3_DS),
1038         PINMUX_IPSR_GPSR(IP10_23_20,            NFCLE),
1039
1040         PINMUX_IPSR_GPSR(IP10_27_24,            SD0_CD),
1041         PINMUX_IPSR_MSEL(IP10_27_24,            NFALE_A,        SEL_NDF_0),
1042         PINMUX_IPSR_GPSR(IP10_27_24,            SD3_CD),
1043         PINMUX_IPSR_MSEL(IP10_27_24,            RIF0_CLK_B,     SEL_DRIF0_1),
1044         PINMUX_IPSR_MSEL(IP10_27_24,            SCL2_B,         SEL_I2C2_1),
1045         PINMUX_IPSR_MSEL(IP10_27_24,            TCLK1_A,        SEL_TIMER_TMU_0),
1046         PINMUX_IPSR_GPSR(IP10_27_24,            SSI_SCK2_B),
1047         PINMUX_IPSR_GPSR(IP10_27_24,            TS_SCK0),
1048
1049         PINMUX_IPSR_GPSR(IP10_31_28,            SD0_WP),
1050         PINMUX_IPSR_MSEL(IP10_31_28,            NFRB_N_A,       SEL_NDF_0),
1051         PINMUX_IPSR_GPSR(IP10_31_28,            SD3_WP),
1052         PINMUX_IPSR_MSEL(IP10_31_28,            RIF0_D0_B,      SEL_DRIF0_1),
1053         PINMUX_IPSR_MSEL(IP10_31_28,            SDA2_B,         SEL_I2C2_1),
1054         PINMUX_IPSR_MSEL(IP10_31_28,            TCLK2_A,        SEL_TIMER_TMU_0),
1055         PINMUX_IPSR_GPSR(IP10_31_28,            SSI_WS2_B),
1056         PINMUX_IPSR_GPSR(IP10_31_28,            TS_SDAT0),
1057
1058         /* IPSR11 */
1059         PINMUX_IPSR_GPSR(IP11_3_0,              SD1_CD),
1060         PINMUX_IPSR_MSEL(IP11_3_0,              NFCE_N_A,       SEL_NDF_0),
1061         PINMUX_IPSR_GPSR(IP11_3_0,              SSI_SCK1),
1062         PINMUX_IPSR_MSEL(IP11_3_0,              RIF0_D1_B,      SEL_DRIF0_1),
1063         PINMUX_IPSR_GPSR(IP11_3_0,              TS_SDEN0),
1064
1065         PINMUX_IPSR_GPSR(IP11_7_4,              SD1_WP),
1066         PINMUX_IPSR_MSEL(IP11_7_4,              NFWP_N_A,       SEL_NDF_0),
1067         PINMUX_IPSR_GPSR(IP11_7_4,              SSI_WS1),
1068         PINMUX_IPSR_MSEL(IP11_7_4,              RIF0_SYNC_B,    SEL_DRIF0_1),
1069         PINMUX_IPSR_GPSR(IP11_7_4,              TS_SPSYNC0),
1070
1071         PINMUX_IPSR_MSEL(IP11_11_8,             RX0_A,          SEL_SCIF0_0),
1072         PINMUX_IPSR_MSEL(IP11_11_8,             HRX1_A,         SEL_HSCIF1_0),
1073         PINMUX_IPSR_GPSR(IP11_11_8,             SSI_SCK2_A),
1074         PINMUX_IPSR_GPSR(IP11_11_8,             RIF1_SYNC),
1075         PINMUX_IPSR_GPSR(IP11_11_8,             TS_SCK1),
1076
1077         PINMUX_IPSR_MSEL(IP11_15_12,            TX0_A,          SEL_SCIF0_0),
1078         PINMUX_IPSR_GPSR(IP11_15_12,            HTX1_A),
1079         PINMUX_IPSR_GPSR(IP11_15_12,            SSI_WS2_A),
1080         PINMUX_IPSR_GPSR(IP11_15_12,            RIF1_D0),
1081         PINMUX_IPSR_GPSR(IP11_15_12,            TS_SDAT1),
1082
1083         PINMUX_IPSR_MSEL(IP11_19_16,            CTS0_N_A,       SEL_SCIF0_0),
1084         PINMUX_IPSR_MSEL(IP11_19_16,            NFDATA14_A,     SEL_NDF_0),
1085         PINMUX_IPSR_GPSR(IP11_19_16,            AUDIO_CLKOUT_A),
1086         PINMUX_IPSR_GPSR(IP11_19_16,            RIF1_D1),
1087         PINMUX_IPSR_MSEL(IP11_19_16,            SCIF_CLK_A,     SEL_SCIF_0),
1088         PINMUX_IPSR_MSEL(IP11_19_16,            FMCLK_A,        SEL_FM_0),
1089
1090         PINMUX_IPSR_MSEL(IP11_23_20,            RTS0_N_A,       SEL_SCIF0_0),
1091         PINMUX_IPSR_MSEL(IP11_23_20,            NFDATA15_A,     SEL_NDF_0),
1092         PINMUX_IPSR_GPSR(IP11_23_20,            AUDIO_CLKOUT1_A),
1093         PINMUX_IPSR_GPSR(IP11_23_20,            RIF1_CLK),
1094         PINMUX_IPSR_MSEL(IP11_23_20,            SCL2_A,         SEL_I2C2_0),
1095         PINMUX_IPSR_MSEL(IP11_23_20,            FMIN_A,         SEL_FM_0),
1096
1097         PINMUX_IPSR_MSEL(IP11_27_24,            SCK0_A,         SEL_SCIF0_0),
1098         PINMUX_IPSR_MSEL(IP11_27_24,            HSCK1_A,        SEL_HSCIF1_0),
1099         PINMUX_IPSR_GPSR(IP11_27_24,            USB3HS0_ID),
1100         PINMUX_IPSR_GPSR(IP11_27_24,            RTS1_N),
1101         PINMUX_IPSR_MSEL(IP11_27_24,            SDA2_A,         SEL_I2C2_0),
1102         PINMUX_IPSR_MSEL(IP11_27_24,            FMCLK_C,        SEL_FM_2),
1103         PINMUX_IPSR_GPSR(IP11_27_24,            USB0_ID),
1104
1105         PINMUX_IPSR_GPSR(IP11_31_28,            RX1),
1106         PINMUX_IPSR_MSEL(IP11_31_28,            HRX2_B,         SEL_HSCIF2_1),
1107         PINMUX_IPSR_MSEL(IP11_31_28,            SSI_SCK9_B,     SEL_SSI9_1),
1108         PINMUX_IPSR_GPSR(IP11_31_28,            AUDIO_CLKOUT1_B),
1109
1110         /* IPSR12 */
1111         PINMUX_IPSR_GPSR(IP12_3_0,              TX1),
1112         PINMUX_IPSR_GPSR(IP12_3_0,              HTX2_B),
1113         PINMUX_IPSR_MSEL(IP12_3_0,              SSI_WS9_B,      SEL_SSI9_1),
1114         PINMUX_IPSR_GPSR(IP12_3_0,              AUDIO_CLKOUT3_B),
1115
1116         PINMUX_IPSR_MSEL(IP12_7_4,              SCK2_A,         SEL_SCIF2_0),
1117         PINMUX_IPSR_MSEL(IP12_7_4,              HSCK0_A,        SEL_HSCIF0_0),
1118         PINMUX_IPSR_MSEL(IP12_7_4,              AUDIO_CLKB_A,   SEL_ADGB_0),
1119         PINMUX_IPSR_GPSR(IP12_7_4,              CTS1_N),
1120         PINMUX_IPSR_MSEL(IP12_7_4,              RIF0_CLK_A,     SEL_DRIF0_0),
1121         PINMUX_IPSR_MSEL(IP12_7_4,              REMOCON_A,      SEL_REMOCON_0),
1122         PINMUX_IPSR_MSEL(IP12_7_4,              SCIF_CLK_B,     SEL_SCIF_1),
1123
1124         PINMUX_IPSR_MSEL(IP12_11_8,             TX2_A,          SEL_SCIF2_0),
1125         PINMUX_IPSR_MSEL(IP12_11_8,             HRX0_A,         SEL_HSCIF0_0),
1126         PINMUX_IPSR_GPSR(IP12_11_8,             AUDIO_CLKOUT2_A),
1127         PINMUX_IPSR_MSEL(IP12_11_8,             SCL1_A,         SEL_I2C1_0),
1128         PINMUX_IPSR_MSEL(IP12_11_8,             FSO_CFE_0_N_A,  SEL_FSO_0),
1129         PINMUX_IPSR_GPSR(IP12_11_8,             TS_SDEN1),
1130
1131         PINMUX_IPSR_MSEL(IP12_15_12,            RX2_A,          SEL_SCIF2_0),
1132         PINMUX_IPSR_GPSR(IP12_15_12,            HTX0_A),
1133         PINMUX_IPSR_GPSR(IP12_15_12,            AUDIO_CLKOUT3_A),
1134         PINMUX_IPSR_MSEL(IP12_15_12,            SDA1_A,         SEL_I2C1_0),
1135         PINMUX_IPSR_MSEL(IP12_15_12,            FSO_CFE_1_N_A,  SEL_FSO_0),
1136         PINMUX_IPSR_GPSR(IP12_15_12,            TS_SPSYNC1),
1137
1138         PINMUX_IPSR_GPSR(IP12_19_16,            MSIOF0_SCK),
1139         PINMUX_IPSR_GPSR(IP12_19_16,            SSI_SCK78),
1140
1141         PINMUX_IPSR_GPSR(IP12_23_20,            MSIOF0_RXD),
1142         PINMUX_IPSR_GPSR(IP12_23_20,            SSI_WS78),
1143         PINMUX_IPSR_MSEL(IP12_23_20,            TX2_B,          SEL_SCIF2_1),
1144
1145         PINMUX_IPSR_GPSR(IP12_27_24,            MSIOF0_TXD),
1146         PINMUX_IPSR_GPSR(IP12_27_24,            SSI_SDATA7),
1147         PINMUX_IPSR_MSEL(IP12_27_24,            RX2_B,          SEL_SCIF2_1),
1148
1149         PINMUX_IPSR_GPSR(IP12_31_28,            MSIOF0_SYNC),
1150         PINMUX_IPSR_GPSR(IP12_31_28,            AUDIO_CLKOUT_B),
1151         PINMUX_IPSR_GPSR(IP12_31_28,            SSI_SDATA8),
1152
1153         /* IPSR13 */
1154         PINMUX_IPSR_GPSR(IP13_3_0,              MSIOF0_SS1),
1155         PINMUX_IPSR_MSEL(IP13_3_0,              HRX2_A,         SEL_HSCIF2_0),
1156         PINMUX_IPSR_GPSR(IP13_3_0,              SSI_SCK4),
1157         PINMUX_IPSR_MSEL(IP13_3_0,              HCTS0_N_A,      SEL_HSCIF0_0),
1158         PINMUX_IPSR_GPSR(IP13_3_0,              BPFCLK_C),
1159         PINMUX_IPSR_MSEL(IP13_3_0,              SPEEDIN_A,      SEL_SPEED_PULSE_IF_0),
1160
1161         PINMUX_IPSR_GPSR(IP13_7_4,              MSIOF0_SS2),
1162         PINMUX_IPSR_GPSR(IP13_7_4,              HTX2_A),
1163         PINMUX_IPSR_GPSR(IP13_7_4,              SSI_WS4),
1164         PINMUX_IPSR_MSEL(IP13_7_4,              HRTS0_N_A,      SEL_HSCIF0_0),
1165         PINMUX_IPSR_MSEL(IP13_7_4,              FMIN_C,         SEL_FM_2),
1166         PINMUX_IPSR_GPSR(IP13_7_4,              BPFCLK_A),
1167
1168         PINMUX_IPSR_GPSR(IP13_11_8,             SSI_SDATA9),
1169         PINMUX_IPSR_MSEL(IP13_11_8,             AUDIO_CLKC_A,   SEL_ADGC_0),
1170         PINMUX_IPSR_GPSR(IP13_11_8,             SCK1),
1171
1172         PINMUX_IPSR_GPSR(IP13_15_12,            MLB_CLK),
1173         PINMUX_IPSR_MSEL(IP13_15_12,            RX0_B,          SEL_SCIF0_1),
1174         PINMUX_IPSR_MSEL(IP13_15_12,            RIF0_D0_A,      SEL_DRIF0_0),
1175         PINMUX_IPSR_MSEL(IP13_15_12,            SCL1_B,         SEL_I2C1_1),
1176         PINMUX_IPSR_MSEL(IP13_15_12,            TCLK1_B,        SEL_TIMER_TMU_1),
1177         PINMUX_IPSR_GPSR(IP13_15_12,            SIM0_RST_A),
1178
1179         PINMUX_IPSR_GPSR(IP13_19_16,            MLB_SIG),
1180         PINMUX_IPSR_MSEL(IP13_19_16,            SCK0_B,         SEL_SCIF0_1),
1181         PINMUX_IPSR_MSEL(IP13_19_16,            RIF0_D1_A,      SEL_DRIF0_0),
1182         PINMUX_IPSR_MSEL(IP13_19_16,            SDA1_B,         SEL_I2C1_1),
1183         PINMUX_IPSR_MSEL(IP13_19_16,            TCLK2_B,        SEL_TIMER_TMU_1),
1184         PINMUX_IPSR_GPSR(IP13_19_16,            SIM0_D_A),
1185
1186         PINMUX_IPSR_GPSR(IP13_23_20,            MLB_DAT),
1187         PINMUX_IPSR_MSEL(IP13_23_20,            TX0_B,          SEL_SCIF0_1),
1188         PINMUX_IPSR_MSEL(IP13_23_20,            RIF0_SYNC_A,    SEL_DRIF0_0),
1189         PINMUX_IPSR_GPSR(IP13_23_20,            SIM0_CLK_A),
1190
1191         PINMUX_IPSR_GPSR(IP13_27_24,            SSI_SCK01239),
1192
1193         PINMUX_IPSR_GPSR(IP13_31_28,            SSI_WS01239),
1194
1195         /* IPSR14 */
1196         PINMUX_IPSR_GPSR(IP14_3_0,              SSI_SDATA0),
1197
1198         PINMUX_IPSR_GPSR(IP14_7_4,              SSI_SDATA1),
1199         PINMUX_IPSR_MSEL(IP14_7_4,              AUDIO_CLKC_B,   SEL_ADGC_1),
1200         PINMUX_IPSR_MSEL(IP14_7_4,              PWM0_B,         SEL_PWM0_1),
1201
1202         PINMUX_IPSR_GPSR(IP14_11_8,             SSI_SDATA2),
1203         PINMUX_IPSR_GPSR(IP14_11_8,             AUDIO_CLKOUT2_B),
1204         PINMUX_IPSR_MSEL(IP14_11_8,             SSI_SCK9_A,     SEL_SSI9_0),
1205         PINMUX_IPSR_MSEL(IP14_11_8,             PWM1_B,         SEL_PWM1_1),
1206
1207         PINMUX_IPSR_GPSR(IP14_15_12,            SSI_SCK349),
1208         PINMUX_IPSR_MSEL(IP14_15_12,            PWM2_C,         SEL_PWM2_2),
1209
1210         PINMUX_IPSR_GPSR(IP14_19_16,            SSI_WS349),
1211         PINMUX_IPSR_MSEL(IP14_19_16,            PWM3_C,         SEL_PWM3_2),
1212
1213         PINMUX_IPSR_GPSR(IP14_23_20,            SSI_SDATA3),
1214         PINMUX_IPSR_GPSR(IP14_23_20,            AUDIO_CLKOUT1_C),
1215         PINMUX_IPSR_MSEL(IP14_23_20,            AUDIO_CLKB_B,   SEL_ADGB_1),
1216         PINMUX_IPSR_MSEL(IP14_23_20,            PWM4_B,         SEL_PWM4_1),
1217
1218         PINMUX_IPSR_GPSR(IP14_27_24,            SSI_SDATA4),
1219         PINMUX_IPSR_MSEL(IP14_27_24,            SSI_WS9_A,      SEL_SSI9_0),
1220         PINMUX_IPSR_MSEL(IP14_27_24,            PWM5_B,         SEL_PWM5_1),
1221
1222         PINMUX_IPSR_GPSR(IP14_31_28,            SSI_SCK5),
1223         PINMUX_IPSR_MSEL(IP14_31_28,            HRX0_B,         SEL_HSCIF0_1),
1224         PINMUX_IPSR_GPSR(IP14_31_28,            USB0_PWEN_B),
1225         PINMUX_IPSR_MSEL(IP14_31_28,            SCL2_D,         SEL_I2C2_3),
1226         PINMUX_IPSR_MSEL(IP14_31_28,            PWM6_B,         SEL_PWM6_1),
1227
1228         /* IPSR15 */
1229         PINMUX_IPSR_GPSR(IP15_3_0,              SSI_WS5),
1230         PINMUX_IPSR_GPSR(IP15_3_0,              HTX0_B),
1231         PINMUX_IPSR_MSEL(IP15_3_0,              USB0_OVC_B,     SEL_USB_20_CH0_1),
1232         PINMUX_IPSR_MSEL(IP15_3_0,              SDA2_D,         SEL_I2C2_3),
1233
1234         PINMUX_IPSR_GPSR(IP15_7_4,              SSI_SDATA5),
1235         PINMUX_IPSR_MSEL(IP15_7_4,              HSCK0_B,        SEL_HSCIF0_1),
1236         PINMUX_IPSR_MSEL(IP15_7_4,              AUDIO_CLKB_C,   SEL_ADGB_2),
1237         PINMUX_IPSR_GPSR(IP15_7_4,              TPU0TO0),
1238
1239         PINMUX_IPSR_GPSR(IP15_11_8,             SSI_SCK6),
1240         PINMUX_IPSR_MSEL(IP15_11_8,             HSCK2_A,        SEL_HSCIF2_0),
1241         PINMUX_IPSR_MSEL(IP15_11_8,             AUDIO_CLKC_C,   SEL_ADGC_2),
1242         PINMUX_IPSR_GPSR(IP15_11_8,             TPU0TO1),
1243         PINMUX_IPSR_MSEL(IP15_11_8,             FSO_CFE_0_N_B,  SEL_FSO_1),
1244         PINMUX_IPSR_GPSR(IP15_11_8,             SIM0_RST_B),
1245
1246         PINMUX_IPSR_GPSR(IP15_15_12,            SSI_WS6),
1247         PINMUX_IPSR_MSEL(IP15_15_12,            HCTS2_N_A,      SEL_HSCIF2_0),
1248         PINMUX_IPSR_GPSR(IP15_15_12,            AUDIO_CLKOUT2_C),
1249         PINMUX_IPSR_GPSR(IP15_15_12,            TPU0TO2),
1250         PINMUX_IPSR_MSEL(IP15_15_12,            SDA1_D,         SEL_I2C1_3),
1251         PINMUX_IPSR_MSEL(IP15_15_12,            FSO_CFE_1_N_B,  SEL_FSO_1),
1252         PINMUX_IPSR_GPSR(IP15_15_12,            SIM0_D_B),
1253
1254         PINMUX_IPSR_GPSR(IP15_19_16,            SSI_SDATA6),
1255         PINMUX_IPSR_MSEL(IP15_19_16,            HRTS2_N_A,      SEL_HSCIF2_0),
1256         PINMUX_IPSR_GPSR(IP15_19_16,            AUDIO_CLKOUT3_C),
1257         PINMUX_IPSR_GPSR(IP15_19_16,            TPU0TO3),
1258         PINMUX_IPSR_MSEL(IP15_19_16,            SCL1_D,         SEL_I2C1_3),
1259         PINMUX_IPSR_MSEL(IP15_19_16,            FSO_TOE_N_B,    SEL_FSO_1),
1260         PINMUX_IPSR_GPSR(IP15_19_16,            SIM0_CLK_B),
1261
1262         PINMUX_IPSR_GPSR(IP15_23_20,            AUDIO_CLKA),
1263
1264         PINMUX_IPSR_GPSR(IP15_27_24,            USB30_PWEN),
1265         PINMUX_IPSR_GPSR(IP15_27_24,            USB0_PWEN_A),
1266
1267         PINMUX_IPSR_GPSR(IP15_31_28,            USB30_OVC),
1268         PINMUX_IPSR_MSEL(IP15_31_28,            USB0_OVC_A,     SEL_USB_20_CH0_0),
1269
1270 /*
1271  * Static pins can not be muxed between different functions but
1272  * still need mark entries in the pinmux list. Add each static
1273  * pin to the list without an associated function. The sh-pfc
1274  * core will do the right thing and skip trying to mux the pin
1275  * while still applying configuration to it.
1276  */
1277 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1278         PINMUX_STATIC
1279 #undef FM
1280 };
1281
1282 /*
1283  * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
1284  * Physical layout rows: A - AE, cols: 1 - 25.
1285  */
1286 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1287 #define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
1288 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1289 #define PIN_NONE U16_MAX
1290
1291 static const struct sh_pfc_pin pinmux_pins[] = {
1292         PINMUX_GPIO_GP_ALL(),
1293
1294         /*
1295          * Pins not associated with a GPIO port.
1296          *
1297          * The pin positions are different between different R8A77990
1298          * packages, all that is needed for the pfc driver is a unique
1299          * number for each pin. To this end use the pin layout from
1300          * R8A77990 to calculate a unique number for each pin.
1301          */
1302         SH_PFC_PIN_NAMED_CFG('F',  1, TRST_N,           CFG_FLAGS),
1303         SH_PFC_PIN_NAMED_CFG('F',  3, TMS,              CFG_FLAGS),
1304         SH_PFC_PIN_NAMED_CFG('F',  4, TCK,              CFG_FLAGS),
1305         SH_PFC_PIN_NAMED_CFG('G',  2, TDI,              CFG_FLAGS),
1306         SH_PFC_PIN_NAMED_CFG('G',  3, FSCLKST_N,        CFG_FLAGS),
1307         SH_PFC_PIN_NAMED_CFG('H',  1, ASEBRK,           CFG_FLAGS),
1308         SH_PFC_PIN_NAMED_CFG('N',  1, AVB_TXC,          CFG_FLAGS),
1309         SH_PFC_PIN_NAMED_CFG('N',  2, AVB_TD0,          CFG_FLAGS),
1310         SH_PFC_PIN_NAMED_CFG('N',  3, AVB_TD1,          CFG_FLAGS),
1311         SH_PFC_PIN_NAMED_CFG('N',  5, AVB_TD2,          CFG_FLAGS),
1312         SH_PFC_PIN_NAMED_CFG('N',  6, AVB_TD3,          CFG_FLAGS),
1313         SH_PFC_PIN_NAMED_CFG('P',  3, AVB_TX_CTL,       CFG_FLAGS),
1314         SH_PFC_PIN_NAMED_CFG('P',  4, AVB_MDIO,         CFG_FLAGS),
1315         SH_PFC_PIN_NAMED_CFG('P',  5, AVB_MDC,          CFG_FLAGS),
1316         SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF,          CFG_FLAGS),
1317         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
1318 };
1319
1320 /* - AUDIO CLOCK ------------------------------------------------------------ */
1321 static const unsigned int audio_clk_a_pins[] = {
1322         /* CLK A */
1323         RCAR_GP_PIN(6, 8),
1324 };
1325
1326 static const unsigned int audio_clk_a_mux[] = {
1327         AUDIO_CLKA_MARK,
1328 };
1329
1330 static const unsigned int audio_clk_b_a_pins[] = {
1331         /* CLK B_A */
1332         RCAR_GP_PIN(5, 7),
1333 };
1334
1335 static const unsigned int audio_clk_b_a_mux[] = {
1336         AUDIO_CLKB_A_MARK,
1337 };
1338
1339 static const unsigned int audio_clk_b_b_pins[] = {
1340         /* CLK B_B */
1341         RCAR_GP_PIN(6, 7),
1342 };
1343
1344 static const unsigned int audio_clk_b_b_mux[] = {
1345         AUDIO_CLKB_B_MARK,
1346 };
1347
1348 static const unsigned int audio_clk_b_c_pins[] = {
1349         /* CLK B_C */
1350         RCAR_GP_PIN(6, 13),
1351 };
1352
1353 static const unsigned int audio_clk_b_c_mux[] = {
1354         AUDIO_CLKB_C_MARK,
1355 };
1356
1357 static const unsigned int audio_clk_c_a_pins[] = {
1358         /* CLK C_A */
1359         RCAR_GP_PIN(5, 16),
1360 };
1361
1362 static const unsigned int audio_clk_c_a_mux[] = {
1363         AUDIO_CLKC_A_MARK,
1364 };
1365
1366 static const unsigned int audio_clk_c_b_pins[] = {
1367         /* CLK C_B */
1368         RCAR_GP_PIN(6, 3),
1369 };
1370
1371 static const unsigned int audio_clk_c_b_mux[] = {
1372         AUDIO_CLKC_B_MARK,
1373 };
1374
1375 static const unsigned int audio_clk_c_c_pins[] = {
1376         /* CLK C_C */
1377         RCAR_GP_PIN(6, 14),
1378 };
1379
1380 static const unsigned int audio_clk_c_c_mux[] = {
1381         AUDIO_CLKC_C_MARK,
1382 };
1383
1384 static const unsigned int audio_clkout_a_pins[] = {
1385         /* CLKOUT_A */
1386         RCAR_GP_PIN(5, 3),
1387 };
1388
1389 static const unsigned int audio_clkout_a_mux[] = {
1390         AUDIO_CLKOUT_A_MARK,
1391 };
1392
1393 static const unsigned int audio_clkout_b_pins[] = {
1394         /* CLKOUT_B */
1395         RCAR_GP_PIN(5, 13),
1396 };
1397
1398 static const unsigned int audio_clkout_b_mux[] = {
1399         AUDIO_CLKOUT_B_MARK,
1400 };
1401
1402 static const unsigned int audio_clkout1_a_pins[] = {
1403         /* CLKOUT1_A */
1404         RCAR_GP_PIN(5, 4),
1405 };
1406
1407 static const unsigned int audio_clkout1_a_mux[] = {
1408         AUDIO_CLKOUT1_A_MARK,
1409 };
1410
1411 static const unsigned int audio_clkout1_b_pins[] = {
1412         /* CLKOUT1_B */
1413         RCAR_GP_PIN(5, 5),
1414 };
1415
1416 static const unsigned int audio_clkout1_b_mux[] = {
1417         AUDIO_CLKOUT1_B_MARK,
1418 };
1419
1420 static const unsigned int audio_clkout1_c_pins[] = {
1421         /* CLKOUT1_C */
1422         RCAR_GP_PIN(6, 7),
1423 };
1424
1425 static const unsigned int audio_clkout1_c_mux[] = {
1426         AUDIO_CLKOUT1_C_MARK,
1427 };
1428
1429 static const unsigned int audio_clkout2_a_pins[] = {
1430         /* CLKOUT2_A */
1431         RCAR_GP_PIN(5, 8),
1432 };
1433
1434 static const unsigned int audio_clkout2_a_mux[] = {
1435         AUDIO_CLKOUT2_A_MARK,
1436 };
1437
1438 static const unsigned int audio_clkout2_b_pins[] = {
1439         /* CLKOUT2_B */
1440         RCAR_GP_PIN(6, 4),
1441 };
1442
1443 static const unsigned int audio_clkout2_b_mux[] = {
1444         AUDIO_CLKOUT2_B_MARK,
1445 };
1446
1447 static const unsigned int audio_clkout2_c_pins[] = {
1448         /* CLKOUT2_C */
1449         RCAR_GP_PIN(6, 15),
1450 };
1451
1452 static const unsigned int audio_clkout2_c_mux[] = {
1453         AUDIO_CLKOUT2_C_MARK,
1454 };
1455
1456 static const unsigned int audio_clkout3_a_pins[] = {
1457         /* CLKOUT3_A */
1458         RCAR_GP_PIN(5, 9),
1459 };
1460
1461 static const unsigned int audio_clkout3_a_mux[] = {
1462         AUDIO_CLKOUT3_A_MARK,
1463 };
1464
1465 static const unsigned int audio_clkout3_b_pins[] = {
1466         /* CLKOUT3_B */
1467         RCAR_GP_PIN(5, 6),
1468 };
1469
1470 static const unsigned int audio_clkout3_b_mux[] = {
1471         AUDIO_CLKOUT3_B_MARK,
1472 };
1473
1474 static const unsigned int audio_clkout3_c_pins[] = {
1475         /* CLKOUT3_C */
1476         RCAR_GP_PIN(6, 16),
1477 };
1478
1479 static const unsigned int audio_clkout3_c_mux[] = {
1480         AUDIO_CLKOUT3_C_MARK,
1481 };
1482
1483 /* - EtherAVB --------------------------------------------------------------- */
1484 static const unsigned int avb_link_pins[] = {
1485         /* AVB_LINK */
1486         RCAR_GP_PIN(2, 23),
1487 };
1488
1489 static const unsigned int avb_link_mux[] = {
1490         AVB_LINK_MARK,
1491 };
1492
1493 static const unsigned int avb_magic_pins[] = {
1494         /* AVB_MAGIC */
1495         RCAR_GP_PIN(2, 22),
1496 };
1497
1498 static const unsigned int avb_magic_mux[] = {
1499         AVB_MAGIC_MARK,
1500 };
1501
1502 static const unsigned int avb_phy_int_pins[] = {
1503         /* AVB_PHY_INT */
1504         RCAR_GP_PIN(2, 21),
1505 };
1506
1507 static const unsigned int avb_phy_int_mux[] = {
1508         AVB_PHY_INT_MARK,
1509 };
1510
1511 static const unsigned int avb_mii_pins[] = {
1512         /*
1513          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1514          * AVB_RD1, AVB_RD2, AVB_RD3,
1515          * AVB_TXCREFCLK
1516          */
1517         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1518         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1519         RCAR_GP_PIN(2, 20),
1520 };
1521
1522 static const unsigned int avb_mii_mux[] = {
1523         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1524         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1525         AVB_TXCREFCLK_MARK,
1526 };
1527
1528 static const unsigned int avb_avtp_pps_pins[] = {
1529         /* AVB_AVTP_PPS */
1530         RCAR_GP_PIN(1, 2),
1531 };
1532
1533 static const unsigned int avb_avtp_pps_mux[] = {
1534         AVB_AVTP_PPS_MARK,
1535 };
1536
1537 static const unsigned int avb_avtp_match_a_pins[] = {
1538         /* AVB_AVTP_MATCH_A */
1539         RCAR_GP_PIN(2, 24),
1540 };
1541
1542 static const unsigned int avb_avtp_match_a_mux[] = {
1543         AVB_AVTP_MATCH_A_MARK,
1544 };
1545
1546 static const unsigned int avb_avtp_capture_a_pins[] = {
1547         /* AVB_AVTP_CAPTURE_A */
1548         RCAR_GP_PIN(2, 25),
1549 };
1550
1551 static const unsigned int avb_avtp_capture_a_mux[] = {
1552         AVB_AVTP_CAPTURE_A_MARK,
1553 };
1554
1555 /* - CAN ------------------------------------------------------------------ */
1556 static const unsigned int can0_data_pins[] = {
1557         /* TX, RX */
1558         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1559 };
1560
1561 static const unsigned int can0_data_mux[] = {
1562         CAN0_TX_MARK, CAN0_RX_MARK,
1563 };
1564
1565 static const unsigned int can1_data_pins[] = {
1566         /* TX, RX */
1567         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1568 };
1569
1570 static const unsigned int can1_data_mux[] = {
1571         CAN1_TX_MARK, CAN1_RX_MARK,
1572 };
1573
1574 /* - CAN Clock -------------------------------------------------------------- */
1575 static const unsigned int can_clk_pins[] = {
1576         /* CLK */
1577         RCAR_GP_PIN(0, 14),
1578 };
1579
1580 static const unsigned int can_clk_mux[] = {
1581         CAN_CLK_MARK,
1582 };
1583
1584 /* - CAN FD --------------------------------------------------------------- */
1585 static const unsigned int canfd0_data_pins[] = {
1586         /* TX, RX */
1587         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1588 };
1589
1590 static const unsigned int canfd0_data_mux[] = {
1591         CANFD0_TX_MARK, CANFD0_RX_MARK,
1592 };
1593
1594 static const unsigned int canfd1_data_pins[] = {
1595         /* TX, RX */
1596         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1597 };
1598
1599 static const unsigned int canfd1_data_mux[] = {
1600         CANFD1_TX_MARK, CANFD1_RX_MARK,
1601 };
1602
1603 /* - DRIF0 --------------------------------------------------------------- */
1604 static const unsigned int drif0_ctrl_a_pins[] = {
1605         /* CLK, SYNC */
1606         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
1607 };
1608
1609 static const unsigned int drif0_ctrl_a_mux[] = {
1610         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1611 };
1612
1613 static const unsigned int drif0_data0_a_pins[] = {
1614         /* D0 */
1615         RCAR_GP_PIN(5, 17),
1616 };
1617
1618 static const unsigned int drif0_data0_a_mux[] = {
1619         RIF0_D0_A_MARK,
1620 };
1621
1622 static const unsigned int drif0_data1_a_pins[] = {
1623         /* D1 */
1624         RCAR_GP_PIN(5, 18),
1625 };
1626
1627 static const unsigned int drif0_data1_a_mux[] = {
1628         RIF0_D1_A_MARK,
1629 };
1630
1631 static const unsigned int drif0_ctrl_b_pins[] = {
1632         /* CLK, SYNC */
1633         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
1634 };
1635
1636 static const unsigned int drif0_ctrl_b_mux[] = {
1637         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1638 };
1639
1640 static const unsigned int drif0_data0_b_pins[] = {
1641         /* D0 */
1642         RCAR_GP_PIN(3, 13),
1643 };
1644
1645 static const unsigned int drif0_data0_b_mux[] = {
1646         RIF0_D0_B_MARK,
1647 };
1648
1649 static const unsigned int drif0_data1_b_pins[] = {
1650         /* D1 */
1651         RCAR_GP_PIN(3, 14),
1652 };
1653
1654 static const unsigned int drif0_data1_b_mux[] = {
1655         RIF0_D1_B_MARK,
1656 };
1657
1658 /* - DRIF1 --------------------------------------------------------------- */
1659 static const unsigned int drif1_ctrl_pins[] = {
1660         /* CLK, SYNC */
1661         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
1662 };
1663
1664 static const unsigned int drif1_ctrl_mux[] = {
1665         RIF1_CLK_MARK, RIF1_SYNC_MARK,
1666 };
1667
1668 static const unsigned int drif1_data0_pins[] = {
1669         /* D0 */
1670         RCAR_GP_PIN(5, 2),
1671 };
1672
1673 static const unsigned int drif1_data0_mux[] = {
1674         RIF1_D0_MARK,
1675 };
1676
1677 static const unsigned int drif1_data1_pins[] = {
1678         /* D1 */
1679         RCAR_GP_PIN(5, 3),
1680 };
1681
1682 static const unsigned int drif1_data1_mux[] = {
1683         RIF1_D1_MARK,
1684 };
1685
1686 /* - DRIF2 --------------------------------------------------------------- */
1687 static const unsigned int drif2_ctrl_a_pins[] = {
1688         /* CLK, SYNC */
1689         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1690 };
1691
1692 static const unsigned int drif2_ctrl_a_mux[] = {
1693         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1694 };
1695
1696 static const unsigned int drif2_data0_a_pins[] = {
1697         /* D0 */
1698         RCAR_GP_PIN(2, 8),
1699 };
1700
1701 static const unsigned int drif2_data0_a_mux[] = {
1702         RIF2_D0_A_MARK,
1703 };
1704
1705 static const unsigned int drif2_data1_a_pins[] = {
1706         /* D1 */
1707         RCAR_GP_PIN(2, 9),
1708 };
1709
1710 static const unsigned int drif2_data1_a_mux[] = {
1711         RIF2_D1_A_MARK,
1712 };
1713
1714 static const unsigned int drif2_ctrl_b_pins[] = {
1715         /* CLK, SYNC */
1716         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1717 };
1718
1719 static const unsigned int drif2_ctrl_b_mux[] = {
1720         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1721 };
1722
1723 static const unsigned int drif2_data0_b_pins[] = {
1724         /* D0 */
1725         RCAR_GP_PIN(1, 6),
1726 };
1727
1728 static const unsigned int drif2_data0_b_mux[] = {
1729         RIF2_D0_B_MARK,
1730 };
1731
1732 static const unsigned int drif2_data1_b_pins[] = {
1733         /* D1 */
1734         RCAR_GP_PIN(1, 7),
1735 };
1736
1737 static const unsigned int drif2_data1_b_mux[] = {
1738         RIF2_D1_B_MARK,
1739 };
1740
1741 /* - DRIF3 --------------------------------------------------------------- */
1742 static const unsigned int drif3_ctrl_a_pins[] = {
1743         /* CLK, SYNC */
1744         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1745 };
1746
1747 static const unsigned int drif3_ctrl_a_mux[] = {
1748         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1749 };
1750
1751 static const unsigned int drif3_data0_a_pins[] = {
1752         /* D0 */
1753         RCAR_GP_PIN(2, 12),
1754 };
1755
1756 static const unsigned int drif3_data0_a_mux[] = {
1757         RIF3_D0_A_MARK,
1758 };
1759
1760 static const unsigned int drif3_data1_a_pins[] = {
1761         /* D1 */
1762         RCAR_GP_PIN(2, 13),
1763 };
1764
1765 static const unsigned int drif3_data1_a_mux[] = {
1766         RIF3_D1_A_MARK,
1767 };
1768
1769 static const unsigned int drif3_ctrl_b_pins[] = {
1770         /* CLK, SYNC */
1771         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1772 };
1773
1774 static const unsigned int drif3_ctrl_b_mux[] = {
1775         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1776 };
1777
1778 static const unsigned int drif3_data0_b_pins[] = {
1779         /* D0 */
1780         RCAR_GP_PIN(0, 10),
1781 };
1782
1783 static const unsigned int drif3_data0_b_mux[] = {
1784         RIF3_D0_B_MARK,
1785 };
1786
1787 static const unsigned int drif3_data1_b_pins[] = {
1788         /* D1 */
1789         RCAR_GP_PIN(0, 11),
1790 };
1791
1792 static const unsigned int drif3_data1_b_mux[] = {
1793         RIF3_D1_B_MARK,
1794 };
1795
1796 /* - DU --------------------------------------------------------------------- */
1797 static const unsigned int du_rgb666_pins[] = {
1798         /* R[7:2], G[7:2], B[7:2] */
1799         RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 5),
1800         RCAR_GP_PIN(0, 3),  RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 0),
1801         RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1802         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1803         RCAR_GP_PIN(0, 1),  RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1804         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1805 };
1806 static const unsigned int du_rgb666_mux[] = {
1807         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1808         DU_DR3_MARK, DU_DR2_MARK,
1809         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1810         DU_DG3_MARK, DU_DG2_MARK,
1811         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1812         DU_DB3_MARK, DU_DB2_MARK,
1813 };
1814 static const unsigned int du_rgb888_pins[] = {
1815         /* R[7:0], G[7:0], B[7:0] */
1816         RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 5),
1817         RCAR_GP_PIN(0, 3),  RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 0),
1818         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1819         RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1820         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1821         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1822         RCAR_GP_PIN(0, 1),  RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1823         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1824         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1825 };
1826 static const unsigned int du_rgb888_mux[] = {
1827         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1828         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1829         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1830         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1831         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1832         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1833 };
1834 static const unsigned int du_clk_in_0_pins[] = {
1835         /* CLKIN0 */
1836         RCAR_GP_PIN(0, 16),
1837 };
1838 static const unsigned int du_clk_in_0_mux[] = {
1839         DU_DOTCLKIN0_MARK
1840 };
1841 static const unsigned int du_clk_in_1_pins[] = {
1842         /* CLKIN1 */
1843         RCAR_GP_PIN(1, 1),
1844 };
1845 static const unsigned int du_clk_in_1_mux[] = {
1846         DU_DOTCLKIN1_MARK
1847 };
1848 static const unsigned int du_clk_out_0_pins[] = {
1849         /* CLKOUT */
1850         RCAR_GP_PIN(1, 3),
1851 };
1852 static const unsigned int du_clk_out_0_mux[] = {
1853         DU_DOTCLKOUT0_MARK
1854 };
1855 static const unsigned int du_sync_pins[] = {
1856         /* VSYNC, HSYNC */
1857         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
1858 };
1859 static const unsigned int du_sync_mux[] = {
1860         DU_VSYNC_MARK, DU_HSYNC_MARK
1861 };
1862 static const unsigned int du_disp_cde_pins[] = {
1863         /* DISP_CDE */
1864         RCAR_GP_PIN(1, 1),
1865 };
1866 static const unsigned int du_disp_cde_mux[] = {
1867         DU_DISP_CDE_MARK,
1868 };
1869 static const unsigned int du_cde_pins[] = {
1870         /* CDE */
1871         RCAR_GP_PIN(1, 0),
1872 };
1873 static const unsigned int du_cde_mux[] = {
1874         DU_CDE_MARK,
1875 };
1876 static const unsigned int du_disp_pins[] = {
1877         /* DISP */
1878         RCAR_GP_PIN(1, 2),
1879 };
1880 static const unsigned int du_disp_mux[] = {
1881         DU_DISP_MARK,
1882 };
1883
1884 /* - HSCIF0 --------------------------------------------------*/
1885 static const unsigned int hscif0_data_a_pins[] = {
1886         /* RX, TX */
1887         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1888 };
1889
1890 static const unsigned int hscif0_data_a_mux[] = {
1891         HRX0_A_MARK, HTX0_A_MARK,
1892 };
1893
1894 static const unsigned int hscif0_clk_a_pins[] = {
1895         /* SCK */
1896         RCAR_GP_PIN(5, 7),
1897 };
1898
1899 static const unsigned int hscif0_clk_a_mux[] = {
1900         HSCK0_A_MARK,
1901 };
1902
1903 static const unsigned int hscif0_ctrl_a_pins[] = {
1904         /* RTS, CTS */
1905         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1906 };
1907
1908 static const unsigned int hscif0_ctrl_a_mux[] = {
1909         HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1910 };
1911
1912 static const unsigned int hscif0_data_b_pins[] = {
1913         /* RX, TX */
1914         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1915 };
1916
1917 static const unsigned int hscif0_data_b_mux[] = {
1918         HRX0_B_MARK, HTX0_B_MARK,
1919 };
1920
1921 static const unsigned int hscif0_clk_b_pins[] = {
1922         /* SCK */
1923         RCAR_GP_PIN(6, 13),
1924 };
1925
1926 static const unsigned int hscif0_clk_b_mux[] = {
1927         HSCK0_B_MARK,
1928 };
1929
1930 /* - HSCIF1 ------------------------------------------------- */
1931 static const unsigned int hscif1_data_a_pins[] = {
1932         /* RX, TX */
1933         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1934 };
1935
1936 static const unsigned int hscif1_data_a_mux[] = {
1937         HRX1_A_MARK, HTX1_A_MARK,
1938 };
1939
1940 static const unsigned int hscif1_clk_a_pins[] = {
1941         /* SCK */
1942         RCAR_GP_PIN(5, 0),
1943 };
1944
1945 static const unsigned int hscif1_clk_a_mux[] = {
1946         HSCK1_A_MARK,
1947 };
1948
1949 static const unsigned int hscif1_data_b_pins[] = {
1950         /* RX, TX */
1951         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1952 };
1953
1954 static const unsigned int hscif1_data_b_mux[] = {
1955         HRX1_B_MARK, HTX1_B_MARK,
1956 };
1957
1958 static const unsigned int hscif1_clk_b_pins[] = {
1959         /* SCK */
1960         RCAR_GP_PIN(3, 0),
1961 };
1962
1963 static const unsigned int hscif1_clk_b_mux[] = {
1964         HSCK1_B_MARK,
1965 };
1966
1967 static const unsigned int hscif1_ctrl_b_pins[] = {
1968         /* RTS, CTS */
1969         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
1970 };
1971
1972 static const unsigned int hscif1_ctrl_b_mux[] = {
1973         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1974 };
1975
1976 /* - HSCIF2 ------------------------------------------------- */
1977 static const unsigned int hscif2_data_a_pins[] = {
1978         /* RX, TX */
1979         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1980 };
1981
1982 static const unsigned int hscif2_data_a_mux[] = {
1983         HRX2_A_MARK, HTX2_A_MARK,
1984 };
1985
1986 static const unsigned int hscif2_clk_a_pins[] = {
1987         /* SCK */
1988         RCAR_GP_PIN(6, 14),
1989 };
1990
1991 static const unsigned int hscif2_clk_a_mux[] = {
1992         HSCK2_A_MARK,
1993 };
1994
1995 static const unsigned int hscif2_ctrl_a_pins[] = {
1996         /* RTS, CTS */
1997         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
1998 };
1999
2000 static const unsigned int hscif2_ctrl_a_mux[] = {
2001         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2002 };
2003
2004 static const unsigned int hscif2_data_b_pins[] = {
2005         /* RX, TX */
2006         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2007 };
2008
2009 static const unsigned int hscif2_data_b_mux[] = {
2010         HRX2_B_MARK, HTX2_B_MARK,
2011 };
2012
2013 /* - HSCIF3 ------------------------------------------------*/
2014 static const unsigned int hscif3_data_a_pins[] = {
2015         /* RX, TX */
2016         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2017 };
2018
2019 static const unsigned int hscif3_data_a_mux[] = {
2020         HRX3_A_MARK, HTX3_A_MARK,
2021 };
2022
2023 static const unsigned int hscif3_data_b_pins[] = {
2024         /* RX, TX */
2025         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2026 };
2027
2028 static const unsigned int hscif3_data_b_mux[] = {
2029         HRX3_B_MARK, HTX3_B_MARK,
2030 };
2031
2032 static const unsigned int hscif3_clk_b_pins[] = {
2033         /* SCK */
2034         RCAR_GP_PIN(0, 4),
2035 };
2036
2037 static const unsigned int hscif3_clk_b_mux[] = {
2038         HSCK3_B_MARK,
2039 };
2040
2041 static const unsigned int hscif3_data_c_pins[] = {
2042         /* RX, TX */
2043         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
2044 };
2045
2046 static const unsigned int hscif3_data_c_mux[] = {
2047         HRX3_C_MARK, HTX3_C_MARK,
2048 };
2049
2050 static const unsigned int hscif3_clk_c_pins[] = {
2051         /* SCK */
2052         RCAR_GP_PIN(2, 11),
2053 };
2054
2055 static const unsigned int hscif3_clk_c_mux[] = {
2056         HSCK3_C_MARK,
2057 };
2058
2059 static const unsigned int hscif3_ctrl_c_pins[] = {
2060         /* RTS, CTS */
2061         RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
2062 };
2063
2064 static const unsigned int hscif3_ctrl_c_mux[] = {
2065         HRTS3_N_C_MARK, HCTS3_N_C_MARK,
2066 };
2067
2068 static const unsigned int hscif3_data_d_pins[] = {
2069         /* RX, TX */
2070         RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
2071 };
2072
2073 static const unsigned int hscif3_data_d_mux[] = {
2074         HRX3_D_MARK, HTX3_D_MARK,
2075 };
2076
2077 static const unsigned int hscif3_data_e_pins[] = {
2078         /* RX, TX */
2079         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2080 };
2081
2082 static const unsigned int hscif3_data_e_mux[] = {
2083         HRX3_E_MARK, HTX3_E_MARK,
2084 };
2085
2086 static const unsigned int hscif3_ctrl_e_pins[] = {
2087         /* RTS, CTS */
2088         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
2089 };
2090
2091 static const unsigned int hscif3_ctrl_e_mux[] = {
2092         HRTS3_N_E_MARK, HCTS3_N_E_MARK,
2093 };
2094
2095 /* - HSCIF4 -------------------------------------------------- */
2096 static const unsigned int hscif4_data_a_pins[] = {
2097         /* RX, TX */
2098         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
2099 };
2100
2101 static const unsigned int hscif4_data_a_mux[] = {
2102         HRX4_A_MARK, HTX4_A_MARK,
2103 };
2104
2105 static const unsigned int hscif4_clk_a_pins[] = {
2106         /* SCK */
2107         RCAR_GP_PIN(2, 0),
2108 };
2109
2110 static const unsigned int hscif4_clk_a_mux[] = {
2111         HSCK4_A_MARK,
2112 };
2113
2114 static const unsigned int hscif4_ctrl_a_pins[] = {
2115         /* RTS, CTS */
2116         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
2117 };
2118
2119 static const unsigned int hscif4_ctrl_a_mux[] = {
2120         HRTS4_N_A_MARK, HCTS4_N_A_MARK,
2121 };
2122
2123 static const unsigned int hscif4_data_b_pins[] = {
2124         /* RX, TX */
2125         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2126 };
2127
2128 static const unsigned int hscif4_data_b_mux[] = {
2129         HRX4_B_MARK, HTX4_B_MARK,
2130 };
2131
2132 static const unsigned int hscif4_clk_b_pins[] = {
2133         /* SCK */
2134         RCAR_GP_PIN(2, 6),
2135 };
2136
2137 static const unsigned int hscif4_clk_b_mux[] = {
2138         HSCK4_B_MARK,
2139 };
2140
2141 static const unsigned int hscif4_data_c_pins[] = {
2142         /* RX, TX */
2143         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2144 };
2145
2146 static const unsigned int hscif4_data_c_mux[] = {
2147         HRX4_C_MARK, HTX4_C_MARK,
2148 };
2149
2150 static const unsigned int hscif4_data_d_pins[] = {
2151         /* RX, TX */
2152         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2153 };
2154
2155 static const unsigned int hscif4_data_d_mux[] = {
2156         HRX4_D_MARK, HTX4_D_MARK,
2157 };
2158
2159 static const unsigned int hscif4_data_e_pins[] = {
2160         /* RX, TX */
2161         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2162 };
2163
2164 static const unsigned int hscif4_data_e_mux[] = {
2165         HRX4_E_MARK, HTX4_E_MARK,
2166 };
2167
2168 /* - I2C -------------------------------------------------------------------- */
2169 static const unsigned int i2c1_a_pins[] = {
2170         /* SCL, SDA */
2171         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2172 };
2173
2174 static const unsigned int i2c1_a_mux[] = {
2175         SCL1_A_MARK, SDA1_A_MARK,
2176 };
2177
2178 static const unsigned int i2c1_b_pins[] = {
2179         /* SCL, SDA */
2180         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2181 };
2182
2183 static const unsigned int i2c1_b_mux[] = {
2184         SCL1_B_MARK, SDA1_B_MARK,
2185 };
2186
2187 static const unsigned int i2c1_c_pins[] = {
2188         /* SCL, SDA */
2189         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
2190 };
2191
2192 static const unsigned int i2c1_c_mux[] = {
2193         SCL1_C_MARK, SDA1_C_MARK,
2194 };
2195
2196 static const unsigned int i2c1_d_pins[] = {
2197         /* SCL, SDA */
2198         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
2199 };
2200
2201 static const unsigned int i2c1_d_mux[] = {
2202         SCL1_D_MARK, SDA1_D_MARK,
2203 };
2204
2205 static const unsigned int i2c2_a_pins[] = {
2206         /* SCL, SDA */
2207         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
2208 };
2209
2210 static const unsigned int i2c2_a_mux[] = {
2211         SCL2_A_MARK, SDA2_A_MARK,
2212 };
2213
2214 static const unsigned int i2c2_b_pins[] = {
2215         /* SCL, SDA */
2216         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2217 };
2218
2219 static const unsigned int i2c2_b_mux[] = {
2220         SCL2_B_MARK, SDA2_B_MARK,
2221 };
2222
2223 static const unsigned int i2c2_c_pins[] = {
2224         /* SCL, SDA */
2225         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
2226 };
2227
2228 static const unsigned int i2c2_c_mux[] = {
2229         SCL2_C_MARK, SDA2_C_MARK,
2230 };
2231
2232 static const unsigned int i2c2_d_pins[] = {
2233         /* SCL, SDA */
2234         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
2235 };
2236
2237 static const unsigned int i2c2_d_mux[] = {
2238         SCL2_D_MARK, SDA2_D_MARK,
2239 };
2240
2241 static const unsigned int i2c2_e_pins[] = {
2242         /* SCL, SDA */
2243         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
2244 };
2245
2246 static const unsigned int i2c2_e_mux[] = {
2247         SCL2_E_MARK, SDA2_E_MARK,
2248 };
2249
2250 static const unsigned int i2c4_pins[] = {
2251         /* SCL, SDA */
2252         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2253 };
2254
2255 static const unsigned int i2c4_mux[] = {
2256         SCL4_MARK, SDA4_MARK,
2257 };
2258
2259 static const unsigned int i2c5_pins[] = {
2260         /* SCL, SDA */
2261         RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2262 };
2263
2264 static const unsigned int i2c5_mux[] = {
2265         SCL5_MARK, SDA5_MARK,
2266 };
2267
2268 static const unsigned int i2c6_a_pins[] = {
2269         /* SCL, SDA */
2270         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
2271 };
2272
2273 static const unsigned int i2c6_a_mux[] = {
2274         SCL6_A_MARK, SDA6_A_MARK,
2275 };
2276
2277 static const unsigned int i2c6_b_pins[] = {
2278         /* SCL, SDA */
2279         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
2280 };
2281
2282 static const unsigned int i2c6_b_mux[] = {
2283         SCL6_B_MARK, SDA6_B_MARK,
2284 };
2285
2286 static const unsigned int i2c7_a_pins[] = {
2287         /* SCL, SDA */
2288         RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
2289 };
2290
2291 static const unsigned int i2c7_a_mux[] = {
2292         SCL7_A_MARK, SDA7_A_MARK,
2293 };
2294
2295 static const unsigned int i2c7_b_pins[] = {
2296         /* SCL, SDA */
2297         RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
2298 };
2299
2300 static const unsigned int i2c7_b_mux[] = {
2301         SCL7_B_MARK, SDA7_B_MARK,
2302 };
2303
2304 /* - INTC-EX ---------------------------------------------------------------- */
2305 static const unsigned int intc_ex_irq0_pins[] = {
2306         /* IRQ0 */
2307         RCAR_GP_PIN(1, 0),
2308 };
2309 static const unsigned int intc_ex_irq0_mux[] = {
2310         IRQ0_MARK,
2311 };
2312 static const unsigned int intc_ex_irq1_pins[] = {
2313         /* IRQ1 */
2314         RCAR_GP_PIN(1, 1),
2315 };
2316 static const unsigned int intc_ex_irq1_mux[] = {
2317         IRQ1_MARK,
2318 };
2319 static const unsigned int intc_ex_irq2_pins[] = {
2320         /* IRQ2 */
2321         RCAR_GP_PIN(1, 2),
2322 };
2323 static const unsigned int intc_ex_irq2_mux[] = {
2324         IRQ2_MARK,
2325 };
2326 static const unsigned int intc_ex_irq3_pins[] = {
2327         /* IRQ3 */
2328         RCAR_GP_PIN(1, 9),
2329 };
2330 static const unsigned int intc_ex_irq3_mux[] = {
2331         IRQ3_MARK,
2332 };
2333 static const unsigned int intc_ex_irq4_pins[] = {
2334         /* IRQ4 */
2335         RCAR_GP_PIN(1, 10),
2336 };
2337 static const unsigned int intc_ex_irq4_mux[] = {
2338         IRQ4_MARK,
2339 };
2340 static const unsigned int intc_ex_irq5_pins[] = {
2341         /* IRQ5 */
2342         RCAR_GP_PIN(0, 7),
2343 };
2344 static const unsigned int intc_ex_irq5_mux[] = {
2345         IRQ5_MARK,
2346 };
2347
2348 /* - MSIOF0 ----------------------------------------------------------------- */
2349 static const unsigned int msiof0_clk_pins[] = {
2350         /* SCK */
2351         RCAR_GP_PIN(5, 10),
2352 };
2353
2354 static const unsigned int msiof0_clk_mux[] = {
2355         MSIOF0_SCK_MARK,
2356 };
2357
2358 static const unsigned int msiof0_sync_pins[] = {
2359         /* SYNC */
2360         RCAR_GP_PIN(5, 13),
2361 };
2362
2363 static const unsigned int msiof0_sync_mux[] = {
2364         MSIOF0_SYNC_MARK,
2365 };
2366
2367 static const unsigned int msiof0_ss1_pins[] = {
2368         /* SS1 */
2369         RCAR_GP_PIN(5, 14),
2370 };
2371
2372 static const unsigned int msiof0_ss1_mux[] = {
2373         MSIOF0_SS1_MARK,
2374 };
2375
2376 static const unsigned int msiof0_ss2_pins[] = {
2377         /* SS2 */
2378         RCAR_GP_PIN(5, 15),
2379 };
2380
2381 static const unsigned int msiof0_ss2_mux[] = {
2382         MSIOF0_SS2_MARK,
2383 };
2384
2385 static const unsigned int msiof0_txd_pins[] = {
2386         /* TXD */
2387         RCAR_GP_PIN(5, 12),
2388 };
2389
2390 static const unsigned int msiof0_txd_mux[] = {
2391         MSIOF0_TXD_MARK,
2392 };
2393
2394 static const unsigned int msiof0_rxd_pins[] = {
2395         /* RXD */
2396         RCAR_GP_PIN(5, 11),
2397 };
2398
2399 static const unsigned int msiof0_rxd_mux[] = {
2400         MSIOF0_RXD_MARK,
2401 };
2402
2403 /* - MSIOF1 ----------------------------------------------------------------- */
2404 static const unsigned int msiof1_clk_pins[] = {
2405         /* SCK */
2406         RCAR_GP_PIN(1, 19),
2407 };
2408
2409 static const unsigned int msiof1_clk_mux[] = {
2410         MSIOF1_SCK_MARK,
2411 };
2412
2413 static const unsigned int msiof1_sync_pins[] = {
2414         /* SYNC */
2415         RCAR_GP_PIN(1, 16),
2416 };
2417
2418 static const unsigned int msiof1_sync_mux[] = {
2419         MSIOF1_SYNC_MARK,
2420 };
2421
2422 static const unsigned int msiof1_ss1_pins[] = {
2423         /* SS1 */
2424         RCAR_GP_PIN(1, 14),
2425 };
2426
2427 static const unsigned int msiof1_ss1_mux[] = {
2428         MSIOF1_SS1_MARK,
2429 };
2430
2431 static const unsigned int msiof1_ss2_pins[] = {
2432         /* SS2 */
2433         RCAR_GP_PIN(1, 15),
2434 };
2435
2436 static const unsigned int msiof1_ss2_mux[] = {
2437         MSIOF1_SS2_MARK,
2438 };
2439
2440 static const unsigned int msiof1_txd_pins[] = {
2441         /* TXD */
2442         RCAR_GP_PIN(1, 18),
2443 };
2444
2445 static const unsigned int msiof1_txd_mux[] = {
2446         MSIOF1_TXD_MARK,
2447 };
2448
2449 static const unsigned int msiof1_rxd_pins[] = {
2450         /* RXD */
2451         RCAR_GP_PIN(1, 17),
2452 };
2453
2454 static const unsigned int msiof1_rxd_mux[] = {
2455         MSIOF1_RXD_MARK,
2456 };
2457
2458 /* - MSIOF2 ----------------------------------------------------------------- */
2459 static const unsigned int msiof2_clk_a_pins[] = {
2460         /* SCK */
2461         RCAR_GP_PIN(0, 8),
2462 };
2463
2464 static const unsigned int msiof2_clk_a_mux[] = {
2465         MSIOF2_SCK_A_MARK,
2466 };
2467
2468 static const unsigned int msiof2_sync_a_pins[] = {
2469         /* SYNC */
2470         RCAR_GP_PIN(0, 9),
2471 };
2472
2473 static const unsigned int msiof2_sync_a_mux[] = {
2474         MSIOF2_SYNC_A_MARK,
2475 };
2476
2477 static const unsigned int msiof2_ss1_a_pins[] = {
2478         /* SS1 */
2479         RCAR_GP_PIN(0, 15),
2480 };
2481
2482 static const unsigned int msiof2_ss1_a_mux[] = {
2483         MSIOF2_SS1_A_MARK,
2484 };
2485
2486 static const unsigned int msiof2_ss2_a_pins[] = {
2487         /* SS2 */
2488         RCAR_GP_PIN(0, 14),
2489 };
2490
2491 static const unsigned int msiof2_ss2_a_mux[] = {
2492         MSIOF2_SS2_A_MARK,
2493 };
2494
2495 static const unsigned int msiof2_txd_a_pins[] = {
2496         /* TXD */
2497         RCAR_GP_PIN(0, 11),
2498 };
2499
2500 static const unsigned int msiof2_txd_a_mux[] = {
2501         MSIOF2_TXD_A_MARK,
2502 };
2503
2504 static const unsigned int msiof2_rxd_a_pins[] = {
2505         /* RXD */
2506         RCAR_GP_PIN(0, 10),
2507 };
2508
2509 static const unsigned int msiof2_rxd_a_mux[] = {
2510         MSIOF2_RXD_A_MARK,
2511 };
2512
2513 static const unsigned int msiof2_clk_b_pins[] = {
2514         /* SCK */
2515         RCAR_GP_PIN(1, 13),
2516 };
2517
2518 static const unsigned int msiof2_clk_b_mux[] = {
2519         MSIOF2_SCK_B_MARK,
2520 };
2521
2522 static const unsigned int msiof2_sync_b_pins[] = {
2523         /* SYNC */
2524         RCAR_GP_PIN(1, 10),
2525 };
2526
2527 static const unsigned int msiof2_sync_b_mux[] = {
2528         MSIOF2_SYNC_B_MARK,
2529 };
2530
2531 static const unsigned int msiof2_ss1_b_pins[] = {
2532         /* SS1 */
2533         RCAR_GP_PIN(1, 16),
2534 };
2535
2536 static const unsigned int msiof2_ss1_b_mux[] = {
2537         MSIOF2_SS1_B_MARK,
2538 };
2539
2540 static const unsigned int msiof2_ss2_b_pins[] = {
2541         /* SS2 */
2542         RCAR_GP_PIN(1, 12),
2543 };
2544
2545 static const unsigned int msiof2_ss2_b_mux[] = {
2546         MSIOF2_SS2_B_MARK,
2547 };
2548
2549 static const unsigned int msiof2_txd_b_pins[] = {
2550         /* TXD */
2551         RCAR_GP_PIN(1, 15),
2552 };
2553
2554 static const unsigned int msiof2_txd_b_mux[] = {
2555         MSIOF2_TXD_B_MARK,
2556 };
2557
2558 static const unsigned int msiof2_rxd_b_pins[] = {
2559         /* RXD */
2560         RCAR_GP_PIN(1, 14),
2561 };
2562
2563 static const unsigned int msiof2_rxd_b_mux[] = {
2564         MSIOF2_RXD_B_MARK,
2565 };
2566
2567 /* - MSIOF3 ----------------------------------------------------------------- */
2568 static const unsigned int msiof3_clk_a_pins[] = {
2569         /* SCK */
2570         RCAR_GP_PIN(0, 0),
2571 };
2572
2573 static const unsigned int msiof3_clk_a_mux[] = {
2574         MSIOF3_SCK_A_MARK,
2575 };
2576
2577 static const unsigned int msiof3_sync_a_pins[] = {
2578         /* SYNC */
2579         RCAR_GP_PIN(0, 1),
2580 };
2581
2582 static const unsigned int msiof3_sync_a_mux[] = {
2583         MSIOF3_SYNC_A_MARK,
2584 };
2585
2586 static const unsigned int msiof3_ss1_a_pins[] = {
2587         /* SS1 */
2588         RCAR_GP_PIN(0, 15),
2589 };
2590
2591 static const unsigned int msiof3_ss1_a_mux[] = {
2592         MSIOF3_SS1_A_MARK,
2593 };
2594
2595 static const unsigned int msiof3_ss2_a_pins[] = {
2596         /* SS2 */
2597         RCAR_GP_PIN(0, 4),
2598 };
2599
2600 static const unsigned int msiof3_ss2_a_mux[] = {
2601         MSIOF3_SS2_A_MARK,
2602 };
2603
2604 static const unsigned int msiof3_txd_a_pins[] = {
2605         /* TXD */
2606         RCAR_GP_PIN(0, 3),
2607 };
2608
2609 static const unsigned int msiof3_txd_a_mux[] = {
2610         MSIOF3_TXD_A_MARK,
2611 };
2612
2613 static const unsigned int msiof3_rxd_a_pins[] = {
2614         /* RXD */
2615         RCAR_GP_PIN(0, 2),
2616 };
2617
2618 static const unsigned int msiof3_rxd_a_mux[] = {
2619         MSIOF3_RXD_A_MARK,
2620 };
2621
2622 static const unsigned int msiof3_clk_b_pins[] = {
2623         /* SCK */
2624         RCAR_GP_PIN(1, 5),
2625 };
2626
2627 static const unsigned int msiof3_clk_b_mux[] = {
2628         MSIOF3_SCK_B_MARK,
2629 };
2630
2631 static const unsigned int msiof3_sync_b_pins[] = {
2632         /* SYNC */
2633         RCAR_GP_PIN(1, 4),
2634 };
2635
2636 static const unsigned int msiof3_sync_b_mux[] = {
2637         MSIOF3_SYNC_B_MARK,
2638 };
2639
2640 static const unsigned int msiof3_ss1_b_pins[] = {
2641         /* SS1 */
2642         RCAR_GP_PIN(1, 0),
2643 };
2644
2645 static const unsigned int msiof3_ss1_b_mux[] = {
2646         MSIOF3_SS1_B_MARK,
2647 };
2648
2649 static const unsigned int msiof3_txd_b_pins[] = {
2650         /* TXD */
2651         RCAR_GP_PIN(1, 7),
2652 };
2653
2654 static const unsigned int msiof3_txd_b_mux[] = {
2655         MSIOF3_TXD_B_MARK,
2656 };
2657
2658 static const unsigned int msiof3_rxd_b_pins[] = {
2659         /* RXD */
2660         RCAR_GP_PIN(1, 6),
2661 };
2662
2663 static const unsigned int msiof3_rxd_b_mux[] = {
2664         MSIOF3_RXD_B_MARK,
2665 };
2666
2667 /* - PWM0 --------------------------------------------------------------------*/
2668 static const unsigned int pwm0_a_pins[] = {
2669         /* PWM */
2670         RCAR_GP_PIN(2, 22),
2671 };
2672
2673 static const unsigned int pwm0_a_mux[] = {
2674         PWM0_A_MARK,
2675 };
2676
2677 static const unsigned int pwm0_b_pins[] = {
2678         /* PWM */
2679         RCAR_GP_PIN(6, 3),
2680 };
2681
2682 static const unsigned int pwm0_b_mux[] = {
2683         PWM0_B_MARK,
2684 };
2685
2686 /* - PWM1 --------------------------------------------------------------------*/
2687 static const unsigned int pwm1_a_pins[] = {
2688         /* PWM */
2689         RCAR_GP_PIN(2, 23),
2690 };
2691
2692 static const unsigned int pwm1_a_mux[] = {
2693         PWM1_A_MARK,
2694 };
2695
2696 static const unsigned int pwm1_b_pins[] = {
2697         /* PWM */
2698         RCAR_GP_PIN(6, 4),
2699 };
2700
2701 static const unsigned int pwm1_b_mux[] = {
2702         PWM1_B_MARK,
2703 };
2704
2705 /* - PWM2 --------------------------------------------------------------------*/
2706 static const unsigned int pwm2_a_pins[] = {
2707         /* PWM */
2708         RCAR_GP_PIN(1, 0),
2709 };
2710
2711 static const unsigned int pwm2_a_mux[] = {
2712         PWM2_A_MARK,
2713 };
2714
2715 static const unsigned int pwm2_b_pins[] = {
2716         /* PWM */
2717         RCAR_GP_PIN(1, 4),
2718 };
2719
2720 static const unsigned int pwm2_b_mux[] = {
2721         PWM2_B_MARK,
2722 };
2723
2724 static const unsigned int pwm2_c_pins[] = {
2725         /* PWM */
2726         RCAR_GP_PIN(6, 5),
2727 };
2728
2729 static const unsigned int pwm2_c_mux[] = {
2730         PWM2_C_MARK,
2731 };
2732
2733 /* - PWM3 --------------------------------------------------------------------*/
2734 static const unsigned int pwm3_a_pins[] = {
2735         /* PWM */
2736         RCAR_GP_PIN(1, 1),
2737 };
2738
2739 static const unsigned int pwm3_a_mux[] = {
2740         PWM3_A_MARK,
2741 };
2742
2743 static const unsigned int pwm3_b_pins[] = {
2744         /* PWM */
2745         RCAR_GP_PIN(1, 5),
2746 };
2747
2748 static const unsigned int pwm3_b_mux[] = {
2749         PWM3_B_MARK,
2750 };
2751
2752 static const unsigned int pwm3_c_pins[] = {
2753         /* PWM */
2754         RCAR_GP_PIN(6, 6),
2755 };
2756
2757 static const unsigned int pwm3_c_mux[] = {
2758         PWM3_C_MARK,
2759 };
2760
2761 /* - PWM4 --------------------------------------------------------------------*/
2762 static const unsigned int pwm4_a_pins[] = {
2763         /* PWM */
2764         RCAR_GP_PIN(1, 3),
2765 };
2766
2767 static const unsigned int pwm4_a_mux[] = {
2768         PWM4_A_MARK,
2769 };
2770
2771 static const unsigned int pwm4_b_pins[] = {
2772         /* PWM */
2773         RCAR_GP_PIN(6, 7),
2774 };
2775
2776 static const unsigned int pwm4_b_mux[] = {
2777         PWM4_B_MARK,
2778 };
2779
2780 /* - PWM5 --------------------------------------------------------------------*/
2781 static const unsigned int pwm5_a_pins[] = {
2782         /* PWM */
2783         RCAR_GP_PIN(2, 24),
2784 };
2785
2786 static const unsigned int pwm5_a_mux[] = {
2787         PWM5_A_MARK,
2788 };
2789
2790 static const unsigned int pwm5_b_pins[] = {
2791         /* PWM */
2792         RCAR_GP_PIN(6, 10),
2793 };
2794
2795 static const unsigned int pwm5_b_mux[] = {
2796         PWM5_B_MARK,
2797 };
2798
2799 /* - PWM6 --------------------------------------------------------------------*/
2800 static const unsigned int pwm6_a_pins[] = {
2801         /* PWM */
2802         RCAR_GP_PIN(2, 25),
2803 };
2804
2805 static const unsigned int pwm6_a_mux[] = {
2806         PWM6_A_MARK,
2807 };
2808
2809 static const unsigned int pwm6_b_pins[] = {
2810         /* PWM */
2811         RCAR_GP_PIN(6, 11),
2812 };
2813
2814 static const unsigned int pwm6_b_mux[] = {
2815         PWM6_B_MARK,
2816 };
2817
2818 /* - SCIF0 ------------------------------------------------------------------ */
2819 static const unsigned int scif0_data_a_pins[] = {
2820         /* RX, TX */
2821         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2822 };
2823
2824 static const unsigned int scif0_data_a_mux[] = {
2825         RX0_A_MARK, TX0_A_MARK,
2826 };
2827
2828 static const unsigned int scif0_clk_a_pins[] = {
2829         /* SCK */
2830         RCAR_GP_PIN(5, 0),
2831 };
2832
2833 static const unsigned int scif0_clk_a_mux[] = {
2834         SCK0_A_MARK,
2835 };
2836
2837 static const unsigned int scif0_ctrl_a_pins[] = {
2838         /* RTS, CTS */
2839         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2840 };
2841
2842 static const unsigned int scif0_ctrl_a_mux[] = {
2843         RTS0_N_A_MARK, CTS0_N_A_MARK,
2844 };
2845
2846 static const unsigned int scif0_data_b_pins[] = {
2847         /* RX, TX */
2848         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2849 };
2850
2851 static const unsigned int scif0_data_b_mux[] = {
2852         RX0_B_MARK, TX0_B_MARK,
2853 };
2854
2855 static const unsigned int scif0_clk_b_pins[] = {
2856         /* SCK */
2857         RCAR_GP_PIN(5, 18),
2858 };
2859
2860 static const unsigned int scif0_clk_b_mux[] = {
2861         SCK0_B_MARK,
2862 };
2863
2864 /* - SCIF1 ------------------------------------------------------------------ */
2865 static const unsigned int scif1_data_pins[] = {
2866         /* RX, TX */
2867         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2868 };
2869
2870 static const unsigned int scif1_data_mux[] = {
2871         RX1_MARK, TX1_MARK,
2872 };
2873
2874 static const unsigned int scif1_clk_pins[] = {
2875         /* SCK */
2876         RCAR_GP_PIN(5, 16),
2877 };
2878
2879 static const unsigned int scif1_clk_mux[] = {
2880         SCK1_MARK,
2881 };
2882
2883 static const unsigned int scif1_ctrl_pins[] = {
2884         /* RTS, CTS */
2885         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
2886 };
2887
2888 static const unsigned int scif1_ctrl_mux[] = {
2889         RTS1_N_MARK, CTS1_N_MARK,
2890 };
2891
2892 /* - SCIF2 ------------------------------------------------------------------ */
2893 static const unsigned int scif2_data_a_pins[] = {
2894         /* RX, TX */
2895         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
2896 };
2897
2898 static const unsigned int scif2_data_a_mux[] = {
2899         RX2_A_MARK, TX2_A_MARK,
2900 };
2901
2902 static const unsigned int scif2_clk_a_pins[] = {
2903         /* SCK */
2904         RCAR_GP_PIN(5, 7),
2905 };
2906
2907 static const unsigned int scif2_clk_a_mux[] = {
2908         SCK2_A_MARK,
2909 };
2910
2911 static const unsigned int scif2_data_b_pins[] = {
2912         /* RX, TX */
2913         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
2914 };
2915
2916 static const unsigned int scif2_data_b_mux[] = {
2917         RX2_B_MARK, TX2_B_MARK,
2918 };
2919
2920 /* - SCIF3 ------------------------------------------------------------------ */
2921 static const unsigned int scif3_data_a_pins[] = {
2922         /* RX, TX */
2923         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2924 };
2925
2926 static const unsigned int scif3_data_a_mux[] = {
2927         RX3_A_MARK, TX3_A_MARK,
2928 };
2929
2930 static const unsigned int scif3_clk_a_pins[] = {
2931         /* SCK */
2932         RCAR_GP_PIN(0, 1),
2933 };
2934
2935 static const unsigned int scif3_clk_a_mux[] = {
2936         SCK3_A_MARK,
2937 };
2938
2939 static const unsigned int scif3_ctrl_a_pins[] = {
2940         /* RTS, CTS */
2941         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
2942 };
2943
2944 static const unsigned int scif3_ctrl_a_mux[] = {
2945         RTS3_N_A_MARK, CTS3_N_A_MARK,
2946 };
2947
2948 static const unsigned int scif3_data_b_pins[] = {
2949         /* RX, TX */
2950         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2951 };
2952
2953 static const unsigned int scif3_data_b_mux[] = {
2954         RX3_B_MARK, TX3_B_MARK,
2955 };
2956
2957 static const unsigned int scif3_data_c_pins[] = {
2958         /* RX, TX */
2959         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2960 };
2961
2962 static const unsigned int scif3_data_c_mux[] = {
2963         RX3_C_MARK, TX3_C_MARK,
2964 };
2965
2966 static const unsigned int scif3_clk_c_pins[] = {
2967         /* SCK */
2968         RCAR_GP_PIN(2, 24),
2969 };
2970
2971 static const unsigned int scif3_clk_c_mux[] = {
2972         SCK3_C_MARK,
2973 };
2974
2975 /* - SCIF4 ------------------------------------------------------------------ */
2976 static const unsigned int scif4_data_a_pins[] = {
2977         /* RX, TX */
2978         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2979 };
2980
2981 static const unsigned int scif4_data_a_mux[] = {
2982         RX4_A_MARK, TX4_A_MARK,
2983 };
2984
2985 static const unsigned int scif4_clk_a_pins[] = {
2986         /* SCK */
2987         RCAR_GP_PIN(1, 5),
2988 };
2989
2990 static const unsigned int scif4_clk_a_mux[] = {
2991         SCK4_A_MARK,
2992 };
2993
2994 static const unsigned int scif4_ctrl_a_pins[] = {
2995         /* RTS, CTS */
2996         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
2997 };
2998
2999 static const unsigned int scif4_ctrl_a_mux[] = {
3000         RTS4_N_A_MARK, CTS4_N_A_MARK,
3001 };
3002
3003 static const unsigned int scif4_data_b_pins[] = {
3004         /* RX, TX */
3005         RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
3006 };
3007
3008 static const unsigned int scif4_data_b_mux[] = {
3009         RX4_B_MARK, TX4_B_MARK,
3010 };
3011
3012 static const unsigned int scif4_clk_b_pins[] = {
3013         /* SCK */
3014         RCAR_GP_PIN(0, 8),
3015 };
3016
3017 static const unsigned int scif4_clk_b_mux[] = {
3018         SCK4_B_MARK,
3019 };
3020
3021 static const unsigned int scif4_data_c_pins[] = {
3022         /* RX, TX */
3023         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3024 };
3025
3026 static const unsigned int scif4_data_c_mux[] = {
3027         RX4_C_MARK, TX4_C_MARK,
3028 };
3029
3030 static const unsigned int scif4_ctrl_c_pins[] = {
3031         /* RTS, CTS */
3032         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
3033 };
3034
3035 static const unsigned int scif4_ctrl_c_mux[] = {
3036         RTS4_N_C_MARK, CTS4_N_C_MARK,
3037 };
3038
3039 /* - SCIF5 ------------------------------------------------------------------ */
3040 static const unsigned int scif5_data_a_pins[] = {
3041         /* RX, TX */
3042         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
3043 };
3044
3045 static const unsigned int scif5_data_a_mux[] = {
3046         RX5_A_MARK, TX5_A_MARK,
3047 };
3048
3049 static const unsigned int scif5_clk_a_pins[] = {
3050         /* SCK */
3051         RCAR_GP_PIN(1, 13),
3052 };
3053
3054 static const unsigned int scif5_clk_a_mux[] = {
3055         SCK5_A_MARK,
3056 };
3057
3058 static const unsigned int scif5_data_b_pins[] = {
3059         /* RX, TX */
3060         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3061 };
3062
3063 static const unsigned int scif5_data_b_mux[] = {
3064         RX5_B_MARK, TX5_B_MARK,
3065 };
3066
3067 static const unsigned int scif5_data_c_pins[] = {
3068         /* RX, TX */
3069         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3070 };
3071
3072 static const unsigned int scif5_data_c_mux[] = {
3073         RX5_C_MARK, TX5_C_MARK,
3074 };
3075
3076 /* - SCIF Clock ------------------------------------------------------------- */
3077 static const unsigned int scif_clk_a_pins[] = {
3078         /* SCIF_CLK */
3079         RCAR_GP_PIN(5, 3),
3080 };
3081
3082 static const unsigned int scif_clk_a_mux[] = {
3083         SCIF_CLK_A_MARK,
3084 };
3085
3086 static const unsigned int scif_clk_b_pins[] = {
3087         /* SCIF_CLK */
3088         RCAR_GP_PIN(5, 7),
3089 };
3090
3091 static const unsigned int scif_clk_b_mux[] = {
3092         SCIF_CLK_B_MARK,
3093 };
3094
3095 /* - SDHI0 ------------------------------------------------------------------ */
3096 static const unsigned int sdhi0_data1_pins[] = {
3097         /* D0 */
3098         RCAR_GP_PIN(3, 2),
3099 };
3100
3101 static const unsigned int sdhi0_data1_mux[] = {
3102         SD0_DAT0_MARK,
3103 };
3104
3105 static const unsigned int sdhi0_data4_pins[] = {
3106         /* D[0:3] */
3107         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3108         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3109 };
3110
3111 static const unsigned int sdhi0_data4_mux[] = {
3112         SD0_DAT0_MARK, SD0_DAT1_MARK,
3113         SD0_DAT2_MARK, SD0_DAT3_MARK,
3114 };
3115
3116 static const unsigned int sdhi0_ctrl_pins[] = {
3117         /* CLK, CMD */
3118         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3119 };
3120
3121 static const unsigned int sdhi0_ctrl_mux[] = {
3122         SD0_CLK_MARK, SD0_CMD_MARK,
3123 };
3124
3125 static const unsigned int sdhi0_cd_pins[] = {
3126         /* CD */
3127         RCAR_GP_PIN(3, 12),
3128 };
3129
3130 static const unsigned int sdhi0_cd_mux[] = {
3131         SD0_CD_MARK,
3132 };
3133
3134 static const unsigned int sdhi0_wp_pins[] = {
3135         /* WP */
3136         RCAR_GP_PIN(3, 13),
3137 };
3138
3139 static const unsigned int sdhi0_wp_mux[] = {
3140         SD0_WP_MARK,
3141 };
3142
3143 /* - SDHI1 ------------------------------------------------------------------ */
3144 static const unsigned int sdhi1_data1_pins[] = {
3145         /* D0 */
3146         RCAR_GP_PIN(3, 8),
3147 };
3148
3149 static const unsigned int sdhi1_data1_mux[] = {
3150         SD1_DAT0_MARK,
3151 };
3152
3153 static const unsigned int sdhi1_data4_pins[] = {
3154         /* D[0:3] */
3155         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3156         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3157 };
3158
3159 static const unsigned int sdhi1_data4_mux[] = {
3160         SD1_DAT0_MARK, SD1_DAT1_MARK,
3161         SD1_DAT2_MARK, SD1_DAT3_MARK,
3162 };
3163
3164 static const unsigned int sdhi1_ctrl_pins[] = {
3165         /* CLK, CMD */
3166         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3167 };
3168
3169 static const unsigned int sdhi1_ctrl_mux[] = {
3170         SD1_CLK_MARK, SD1_CMD_MARK,
3171 };
3172
3173 static const unsigned int sdhi1_cd_pins[] = {
3174         /* CD */
3175         RCAR_GP_PIN(3, 14),
3176 };
3177
3178 static const unsigned int sdhi1_cd_mux[] = {
3179         SD1_CD_MARK,
3180 };
3181
3182 static const unsigned int sdhi1_wp_pins[] = {
3183         /* WP */
3184         RCAR_GP_PIN(3, 15),
3185 };
3186
3187 static const unsigned int sdhi1_wp_mux[] = {
3188         SD1_WP_MARK,
3189 };
3190
3191 /* - SDHI3 ------------------------------------------------------------------ */
3192 static const unsigned int sdhi3_data1_pins[] = {
3193         /* D0 */
3194         RCAR_GP_PIN(4, 2),
3195 };
3196
3197 static const unsigned int sdhi3_data1_mux[] = {
3198         SD3_DAT0_MARK,
3199 };
3200
3201 static const unsigned int sdhi3_data4_pins[] = {
3202         /* D[0:3] */
3203         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3204         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3205 };
3206
3207 static const unsigned int sdhi3_data4_mux[] = {
3208         SD3_DAT0_MARK, SD3_DAT1_MARK,
3209         SD3_DAT2_MARK, SD3_DAT3_MARK,
3210 };
3211
3212 static const unsigned int sdhi3_data8_pins[] = {
3213         /* D[0:7] */
3214         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3215         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3216         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
3217         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3218 };
3219
3220 static const unsigned int sdhi3_data8_mux[] = {
3221         SD3_DAT0_MARK, SD3_DAT1_MARK,
3222         SD3_DAT2_MARK, SD3_DAT3_MARK,
3223         SD3_DAT4_MARK, SD3_DAT5_MARK,
3224         SD3_DAT6_MARK, SD3_DAT7_MARK,
3225 };
3226
3227 static const unsigned int sdhi3_ctrl_pins[] = {
3228         /* CLK, CMD */
3229         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3230 };
3231
3232 static const unsigned int sdhi3_ctrl_mux[] = {
3233         SD3_CLK_MARK, SD3_CMD_MARK,
3234 };
3235
3236 static const unsigned int sdhi3_cd_pins[] = {
3237         /* CD */
3238         RCAR_GP_PIN(3, 12),
3239 };
3240
3241 static const unsigned int sdhi3_cd_mux[] = {
3242         SD3_CD_MARK,
3243 };
3244
3245 static const unsigned int sdhi3_wp_pins[] = {
3246         /* WP */
3247         RCAR_GP_PIN(3, 13),
3248 };
3249
3250 static const unsigned int sdhi3_wp_mux[] = {
3251         SD3_WP_MARK,
3252 };
3253
3254 static const unsigned int sdhi3_ds_pins[] = {
3255         /* DS */
3256         RCAR_GP_PIN(4, 10),
3257 };
3258
3259 static const unsigned int sdhi3_ds_mux[] = {
3260         SD3_DS_MARK,
3261 };
3262
3263 /* - SSI -------------------------------------------------------------------- */
3264 static const unsigned int ssi0_data_pins[] = {
3265         /* SDATA */
3266         RCAR_GP_PIN(6, 2),
3267 };
3268
3269 static const unsigned int ssi0_data_mux[] = {
3270         SSI_SDATA0_MARK,
3271 };
3272
3273 static const unsigned int ssi01239_ctrl_pins[] = {
3274         /* SCK, WS */
3275         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3276 };
3277
3278 static const unsigned int ssi01239_ctrl_mux[] = {
3279         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3280 };
3281
3282 static const unsigned int ssi1_data_pins[] = {
3283         /* SDATA */
3284         RCAR_GP_PIN(6, 3),
3285 };
3286
3287 static const unsigned int ssi1_data_mux[] = {
3288         SSI_SDATA1_MARK,
3289 };
3290
3291 static const unsigned int ssi1_ctrl_pins[] = {
3292         /* SCK, WS */
3293         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3294 };
3295
3296 static const unsigned int ssi1_ctrl_mux[] = {
3297         SSI_SCK1_MARK, SSI_WS1_MARK,
3298 };
3299
3300 static const unsigned int ssi2_data_pins[] = {
3301         /* SDATA */
3302         RCAR_GP_PIN(6, 4),
3303 };
3304
3305 static const unsigned int ssi2_data_mux[] = {
3306         SSI_SDATA2_MARK,
3307 };
3308
3309 static const unsigned int ssi2_ctrl_a_pins[] = {
3310         /* SCK, WS */
3311         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3312 };
3313
3314 static const unsigned int ssi2_ctrl_a_mux[] = {
3315         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3316 };
3317
3318 static const unsigned int ssi2_ctrl_b_pins[] = {
3319         /* SCK, WS */
3320         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3321 };
3322
3323 static const unsigned int ssi2_ctrl_b_mux[] = {
3324         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3325 };
3326
3327 static const unsigned int ssi3_data_pins[] = {
3328         /* SDATA */
3329         RCAR_GP_PIN(6, 7),
3330 };
3331
3332 static const unsigned int ssi3_data_mux[] = {
3333         SSI_SDATA3_MARK,
3334 };
3335
3336 static const unsigned int ssi349_ctrl_pins[] = {
3337         /* SCK, WS */
3338         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3339 };
3340
3341 static const unsigned int ssi349_ctrl_mux[] = {
3342         SSI_SCK349_MARK, SSI_WS349_MARK,
3343 };
3344
3345 static const unsigned int ssi4_data_pins[] = {
3346         /* SDATA */
3347         RCAR_GP_PIN(6, 10),
3348 };
3349
3350 static const unsigned int ssi4_data_mux[] = {
3351         SSI_SDATA4_MARK,
3352 };
3353
3354 static const unsigned int ssi4_ctrl_pins[] = {
3355         /* SCK, WS */
3356         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3357 };
3358
3359 static const unsigned int ssi4_ctrl_mux[] = {
3360         SSI_SCK4_MARK, SSI_WS4_MARK,
3361 };
3362
3363 static const unsigned int ssi5_data_pins[] = {
3364         /* SDATA */
3365         RCAR_GP_PIN(6, 13),
3366 };
3367
3368 static const unsigned int ssi5_data_mux[] = {
3369         SSI_SDATA5_MARK,
3370 };
3371
3372 static const unsigned int ssi5_ctrl_pins[] = {
3373         /* SCK, WS */
3374         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3375 };
3376
3377 static const unsigned int ssi5_ctrl_mux[] = {
3378         SSI_SCK5_MARK, SSI_WS5_MARK,
3379 };
3380
3381 static const unsigned int ssi6_data_pins[] = {
3382         /* SDATA */
3383         RCAR_GP_PIN(6, 16),
3384 };
3385
3386 static const unsigned int ssi6_data_mux[] = {
3387         SSI_SDATA6_MARK,
3388 };
3389
3390 static const unsigned int ssi6_ctrl_pins[] = {
3391         /* SCK, WS */
3392         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3393 };
3394
3395 static const unsigned int ssi6_ctrl_mux[] = {
3396         SSI_SCK6_MARK, SSI_WS6_MARK,
3397 };
3398
3399 static const unsigned int ssi7_data_pins[] = {
3400         /* SDATA */
3401         RCAR_GP_PIN(5, 12),
3402 };
3403
3404 static const unsigned int ssi7_data_mux[] = {
3405         SSI_SDATA7_MARK,
3406 };
3407
3408 static const unsigned int ssi78_ctrl_pins[] = {
3409         /* SCK, WS */
3410         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3411 };
3412
3413 static const unsigned int ssi78_ctrl_mux[] = {
3414         SSI_SCK78_MARK, SSI_WS78_MARK,
3415 };
3416
3417 static const unsigned int ssi8_data_pins[] = {
3418         /* SDATA */
3419         RCAR_GP_PIN(5, 13),
3420 };
3421
3422 static const unsigned int ssi8_data_mux[] = {
3423         SSI_SDATA8_MARK,
3424 };
3425
3426 static const unsigned int ssi9_data_pins[] = {
3427         /* SDATA */
3428         RCAR_GP_PIN(5, 16),
3429 };
3430
3431 static const unsigned int ssi9_data_mux[] = {
3432         SSI_SDATA9_MARK,
3433 };
3434
3435 static const unsigned int ssi9_ctrl_a_pins[] = {
3436         /* SCK, WS */
3437         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
3438 };
3439
3440 static const unsigned int ssi9_ctrl_a_mux[] = {
3441         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3442 };
3443
3444 static const unsigned int ssi9_ctrl_b_pins[] = {
3445         /* SCK, WS */
3446         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3447 };
3448
3449 static const unsigned int ssi9_ctrl_b_mux[] = {
3450         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3451 };
3452
3453 /* - TMU -------------------------------------------------------------------- */
3454 static const unsigned int tmu_tclk1_a_pins[] = {
3455         /* TCLK */
3456         RCAR_GP_PIN(3, 12),
3457 };
3458
3459 static const unsigned int tmu_tclk1_a_mux[] = {
3460         TCLK1_A_MARK,
3461 };
3462
3463 static const unsigned int tmu_tclk1_b_pins[] = {
3464         /* TCLK */
3465         RCAR_GP_PIN(5, 17),
3466 };
3467
3468 static const unsigned int tmu_tclk1_b_mux[] = {
3469         TCLK1_B_MARK,
3470 };
3471
3472 static const unsigned int tmu_tclk2_a_pins[] = {
3473         /* TCLK */
3474         RCAR_GP_PIN(3, 13),
3475 };
3476
3477 static const unsigned int tmu_tclk2_a_mux[] = {
3478         TCLK2_A_MARK,
3479 };
3480
3481 static const unsigned int tmu_tclk2_b_pins[] = {
3482         /* TCLK */
3483         RCAR_GP_PIN(5, 18),
3484 };
3485
3486 static const unsigned int tmu_tclk2_b_mux[] = {
3487         TCLK2_B_MARK,
3488 };
3489
3490 /* - USB0 ------------------------------------------------------------------- */
3491 static const unsigned int usb0_a_pins[] = {
3492         /* PWEN, OVC */
3493         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3494 };
3495
3496 static const unsigned int usb0_a_mux[] = {
3497         USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
3498 };
3499
3500 static const unsigned int usb0_b_pins[] = {
3501         /* PWEN, OVC */
3502         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3503 };
3504
3505 static const unsigned int usb0_b_mux[] = {
3506         USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
3507 };
3508
3509 static const unsigned int usb0_id_pins[] = {
3510         /* ID */
3511         RCAR_GP_PIN(5, 0)
3512 };
3513
3514 static const unsigned int usb0_id_mux[] = {
3515         USB0_ID_MARK,
3516 };
3517
3518 /* - USB30 ------------------------------------------------------------------ */
3519 static const unsigned int usb30_pins[] = {
3520         /* PWEN, OVC */
3521         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3522 };
3523
3524 static const unsigned int usb30_mux[] = {
3525         USB30_PWEN_MARK, USB30_OVC_MARK,
3526 };
3527
3528 static const unsigned int usb30_id_pins[] = {
3529         /* ID */
3530         RCAR_GP_PIN(5, 0),
3531 };
3532
3533 static const unsigned int usb30_id_mux[] = {
3534         USB3HS0_ID_MARK,
3535 };
3536
3537 /* - VIN4 ------------------------------------------------------------------- */
3538 static const unsigned int vin4_data18_a_pins[] = {
3539         RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),
3540         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3541         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3542         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3543         RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
3544         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3545         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3546         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3547         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3548 };
3549
3550 static const unsigned int vin4_data18_a_mux[] = {
3551         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3552         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3553         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3554         VI4_DATA10_MARK,  VI4_DATA11_MARK,
3555         VI4_DATA12_MARK,  VI4_DATA13_MARK,
3556         VI4_DATA14_MARK,  VI4_DATA15_MARK,
3557         VI4_DATA18_MARK,  VI4_DATA19_MARK,
3558         VI4_DATA20_MARK,  VI4_DATA21_MARK,
3559         VI4_DATA22_MARK,  VI4_DATA23_MARK,
3560 };
3561
3562 static const union vin_data vin4_data_a_pins = {
3563         .data24 = {
3564                 RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),
3565                 RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),
3566                 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3567                 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3568                 RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
3569                 RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3570                 RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
3571                 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3572                 RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12),
3573                 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3574                 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3575                 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3576         },
3577 };
3578
3579 static const union vin_data vin4_data_a_mux = {
3580         .data24 = {
3581                 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3582                 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3583                 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3584                 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3585                 VI4_DATA8_MARK,   VI4_DATA9_MARK,
3586                 VI4_DATA10_MARK,  VI4_DATA11_MARK,
3587                 VI4_DATA12_MARK,  VI4_DATA13_MARK,
3588                 VI4_DATA14_MARK,  VI4_DATA15_MARK,
3589                 VI4_DATA16_MARK,  VI4_DATA17_MARK,
3590                 VI4_DATA18_MARK,  VI4_DATA19_MARK,
3591                 VI4_DATA20_MARK,  VI4_DATA21_MARK,
3592                 VI4_DATA22_MARK,  VI4_DATA23_MARK,
3593         },
3594 };
3595
3596 static const unsigned int vin4_data18_b_pins[] = {
3597         RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3598         RCAR_GP_PIN(0, 5),  RCAR_GP_PIN(0, 6),
3599         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3600         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3601         RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
3602         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3603         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3604         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3605         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3606 };
3607
3608 static const unsigned int vin4_data18_b_mux[] = {
3609         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3610         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3611         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3612         VI4_DATA10_MARK,  VI4_DATA11_MARK,
3613         VI4_DATA12_MARK,  VI4_DATA13_MARK,
3614         VI4_DATA14_MARK,  VI4_DATA15_MARK,
3615         VI4_DATA18_MARK,  VI4_DATA19_MARK,
3616         VI4_DATA20_MARK,  VI4_DATA21_MARK,
3617         VI4_DATA22_MARK,  VI4_DATA23_MARK,
3618 };
3619
3620 static const union vin_data vin4_data_b_pins = {
3621         .data24 = {
3622                 RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 11),
3623                 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3624                 RCAR_GP_PIN(0, 5),  RCAR_GP_PIN(0, 6),
3625                 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3626                 RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
3627                 RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3628                 RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
3629                 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3630                 RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12),
3631                 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3632                 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3633                 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3634         },
3635 };
3636
3637 static const union vin_data vin4_data_b_mux = {
3638         .data24 = {
3639                 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3640                 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3641                 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3642                 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3643                 VI4_DATA8_MARK,   VI4_DATA9_MARK,
3644                 VI4_DATA10_MARK,  VI4_DATA11_MARK,
3645                 VI4_DATA12_MARK,  VI4_DATA13_MARK,
3646                 VI4_DATA14_MARK,  VI4_DATA15_MARK,
3647                 VI4_DATA16_MARK,  VI4_DATA17_MARK,
3648                 VI4_DATA18_MARK,  VI4_DATA19_MARK,
3649                 VI4_DATA20_MARK,  VI4_DATA21_MARK,
3650                 VI4_DATA22_MARK,  VI4_DATA23_MARK,
3651         },
3652 };
3653
3654 static const unsigned int vin4_sync_pins[] = {
3655         /* HSYNC, VSYNC */
3656         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3657 };
3658
3659 static const unsigned int vin4_sync_mux[] = {
3660         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3661 };
3662
3663 static const unsigned int vin4_field_pins[] = {
3664         RCAR_GP_PIN(2, 23),
3665 };
3666
3667 static const unsigned int vin4_field_mux[] = {
3668         VI4_FIELD_MARK,
3669 };
3670
3671 static const unsigned int vin4_clkenb_pins[] = {
3672         RCAR_GP_PIN(1, 2),
3673 };
3674
3675 static const unsigned int vin4_clkenb_mux[] = {
3676         VI4_CLKENB_MARK,
3677 };
3678
3679 static const unsigned int vin4_clk_pins[] = {
3680         RCAR_GP_PIN(2, 22),
3681 };
3682
3683 static const unsigned int vin4_clk_mux[] = {
3684         VI4_CLK_MARK,
3685 };
3686
3687 /* - VIN5 ------------------------------------------------------------------- */
3688 static const union vin_data16 vin5_data_a_pins = {
3689         .data16 = {
3690                 RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 2),
3691                 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3692                 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3693                 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3694                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3695                 RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 11),
3696                 RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 10),
3697                 RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
3698         },
3699 };
3700
3701 static const union vin_data16 vin5_data_a_mux = {
3702         .data16 = {
3703                 VI5_DATA0_A_MARK,  VI5_DATA1_A_MARK,
3704                 VI5_DATA2_A_MARK,  VI5_DATA3_A_MARK,
3705                 VI5_DATA4_A_MARK,  VI5_DATA5_A_MARK,
3706                 VI5_DATA6_A_MARK,  VI5_DATA7_A_MARK,
3707                 VI5_DATA8_A_MARK,  VI5_DATA9_A_MARK,
3708                 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
3709                 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
3710                 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
3711         },
3712 };
3713
3714 static const unsigned int vin5_data8_b_pins[] = {
3715         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
3716         RCAR_GP_PIN(0, 7),  RCAR_GP_PIN(0, 12),
3717         RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
3718         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3719 };
3720
3721 static const unsigned int vin5_data8_b_mux[] = {
3722         VI5_DATA0_B_MARK,  VI5_DATA1_B_MARK,
3723         VI5_DATA2_B_MARK,  VI5_DATA3_B_MARK,
3724         VI5_DATA4_B_MARK,  VI5_DATA5_B_MARK,
3725         VI5_DATA6_B_MARK,  VI5_DATA7_B_MARK,
3726 };
3727
3728 static const unsigned int vin5_sync_a_pins[] = {
3729         /* HSYNC_N, VSYNC_N */
3730         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
3731 };
3732
3733 static const unsigned int vin5_sync_a_mux[] = {
3734         VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
3735 };
3736
3737 static const unsigned int vin5_field_a_pins[] = {
3738         RCAR_GP_PIN(1, 10),
3739 };
3740
3741 static const unsigned int vin5_field_a_mux[] = {
3742         VI5_FIELD_A_MARK,
3743 };
3744
3745 static const unsigned int vin5_clkenb_a_pins[] = {
3746         RCAR_GP_PIN(0, 1),
3747 };
3748
3749 static const unsigned int vin5_clkenb_a_mux[] = {
3750         VI5_CLKENB_A_MARK,
3751 };
3752
3753 static const unsigned int vin5_clk_a_pins[] = {
3754         RCAR_GP_PIN(1, 0),
3755 };
3756
3757 static const unsigned int vin5_clk_a_mux[] = {
3758         VI5_CLK_A_MARK,
3759 };
3760
3761 static const unsigned int vin5_clk_b_pins[] = {
3762         RCAR_GP_PIN(2, 22),
3763 };
3764
3765 static const unsigned int vin5_clk_b_mux[] = {
3766         VI5_CLK_B_MARK,
3767 };
3768
3769 static const struct {
3770         struct sh_pfc_pin_group common[247];
3771         struct sh_pfc_pin_group automotive[21];
3772 } pinmux_groups = {
3773         .common = {
3774                 SH_PFC_PIN_GROUP(audio_clk_a),
3775                 SH_PFC_PIN_GROUP(audio_clk_b_a),
3776                 SH_PFC_PIN_GROUP(audio_clk_b_b),
3777                 SH_PFC_PIN_GROUP(audio_clk_b_c),
3778                 SH_PFC_PIN_GROUP(audio_clk_c_a),
3779                 SH_PFC_PIN_GROUP(audio_clk_c_b),
3780                 SH_PFC_PIN_GROUP(audio_clk_c_c),
3781                 SH_PFC_PIN_GROUP(audio_clkout_a),
3782                 SH_PFC_PIN_GROUP(audio_clkout_b),
3783                 SH_PFC_PIN_GROUP(audio_clkout1_a),
3784                 SH_PFC_PIN_GROUP(audio_clkout1_b),
3785                 SH_PFC_PIN_GROUP(audio_clkout1_c),
3786                 SH_PFC_PIN_GROUP(audio_clkout2_a),
3787                 SH_PFC_PIN_GROUP(audio_clkout2_b),
3788                 SH_PFC_PIN_GROUP(audio_clkout2_c),
3789                 SH_PFC_PIN_GROUP(audio_clkout3_a),
3790                 SH_PFC_PIN_GROUP(audio_clkout3_b),
3791                 SH_PFC_PIN_GROUP(audio_clkout3_c),
3792                 SH_PFC_PIN_GROUP(avb_link),
3793                 SH_PFC_PIN_GROUP(avb_magic),
3794                 SH_PFC_PIN_GROUP(avb_phy_int),
3795                 SH_PFC_PIN_GROUP(avb_mii),
3796                 SH_PFC_PIN_GROUP(avb_avtp_pps),
3797                 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3798                 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3799                 SH_PFC_PIN_GROUP(can0_data),
3800                 SH_PFC_PIN_GROUP(can1_data),
3801                 SH_PFC_PIN_GROUP(can_clk),
3802                 SH_PFC_PIN_GROUP(canfd0_data),
3803                 SH_PFC_PIN_GROUP(canfd1_data),
3804                 SH_PFC_PIN_GROUP(du_rgb666),
3805                 SH_PFC_PIN_GROUP(du_rgb888),
3806                 SH_PFC_PIN_GROUP(du_clk_in_0),
3807                 SH_PFC_PIN_GROUP(du_clk_in_1),
3808                 SH_PFC_PIN_GROUP(du_clk_out_0),
3809                 SH_PFC_PIN_GROUP(du_sync),
3810                 SH_PFC_PIN_GROUP(du_disp_cde),
3811                 SH_PFC_PIN_GROUP(du_cde),
3812                 SH_PFC_PIN_GROUP(du_disp),
3813                 SH_PFC_PIN_GROUP(hscif0_data_a),
3814                 SH_PFC_PIN_GROUP(hscif0_clk_a),
3815                 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
3816                 SH_PFC_PIN_GROUP(hscif0_data_b),
3817                 SH_PFC_PIN_GROUP(hscif0_clk_b),
3818                 SH_PFC_PIN_GROUP(hscif1_data_a),
3819                 SH_PFC_PIN_GROUP(hscif1_clk_a),
3820                 SH_PFC_PIN_GROUP(hscif1_data_b),
3821                 SH_PFC_PIN_GROUP(hscif1_clk_b),
3822                 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3823                 SH_PFC_PIN_GROUP(hscif2_data_a),
3824                 SH_PFC_PIN_GROUP(hscif2_clk_a),
3825                 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3826                 SH_PFC_PIN_GROUP(hscif2_data_b),
3827                 SH_PFC_PIN_GROUP(hscif3_data_a),
3828                 SH_PFC_PIN_GROUP(hscif3_data_b),
3829                 SH_PFC_PIN_GROUP(hscif3_clk_b),
3830                 SH_PFC_PIN_GROUP(hscif3_data_c),
3831                 SH_PFC_PIN_GROUP(hscif3_clk_c),
3832                 SH_PFC_PIN_GROUP(hscif3_ctrl_c),
3833                 SH_PFC_PIN_GROUP(hscif3_data_d),
3834                 SH_PFC_PIN_GROUP(hscif3_data_e),
3835                 SH_PFC_PIN_GROUP(hscif3_ctrl_e),
3836                 SH_PFC_PIN_GROUP(hscif4_data_a),
3837                 SH_PFC_PIN_GROUP(hscif4_clk_a),
3838                 SH_PFC_PIN_GROUP(hscif4_ctrl_a),
3839                 SH_PFC_PIN_GROUP(hscif4_data_b),
3840                 SH_PFC_PIN_GROUP(hscif4_clk_b),
3841                 SH_PFC_PIN_GROUP(hscif4_data_c),
3842                 SH_PFC_PIN_GROUP(hscif4_data_d),
3843                 SH_PFC_PIN_GROUP(hscif4_data_e),
3844                 SH_PFC_PIN_GROUP(i2c1_a),
3845                 SH_PFC_PIN_GROUP(i2c1_b),
3846                 SH_PFC_PIN_GROUP(i2c1_c),
3847                 SH_PFC_PIN_GROUP(i2c1_d),
3848                 SH_PFC_PIN_GROUP(i2c2_a),
3849                 SH_PFC_PIN_GROUP(i2c2_b),
3850                 SH_PFC_PIN_GROUP(i2c2_c),
3851                 SH_PFC_PIN_GROUP(i2c2_d),
3852                 SH_PFC_PIN_GROUP(i2c2_e),
3853                 SH_PFC_PIN_GROUP(i2c4),
3854                 SH_PFC_PIN_GROUP(i2c5),
3855                 SH_PFC_PIN_GROUP(i2c6_a),
3856                 SH_PFC_PIN_GROUP(i2c6_b),
3857                 SH_PFC_PIN_GROUP(i2c7_a),
3858                 SH_PFC_PIN_GROUP(i2c7_b),
3859                 SH_PFC_PIN_GROUP(intc_ex_irq0),
3860                 SH_PFC_PIN_GROUP(intc_ex_irq1),
3861                 SH_PFC_PIN_GROUP(intc_ex_irq2),
3862                 SH_PFC_PIN_GROUP(intc_ex_irq3),
3863                 SH_PFC_PIN_GROUP(intc_ex_irq4),
3864                 SH_PFC_PIN_GROUP(intc_ex_irq5),
3865                 SH_PFC_PIN_GROUP(msiof0_clk),
3866                 SH_PFC_PIN_GROUP(msiof0_sync),
3867                 SH_PFC_PIN_GROUP(msiof0_ss1),
3868                 SH_PFC_PIN_GROUP(msiof0_ss2),
3869                 SH_PFC_PIN_GROUP(msiof0_txd),
3870                 SH_PFC_PIN_GROUP(msiof0_rxd),
3871                 SH_PFC_PIN_GROUP(msiof1_clk),
3872                 SH_PFC_PIN_GROUP(msiof1_sync),
3873                 SH_PFC_PIN_GROUP(msiof1_ss1),
3874                 SH_PFC_PIN_GROUP(msiof1_ss2),
3875                 SH_PFC_PIN_GROUP(msiof1_txd),
3876                 SH_PFC_PIN_GROUP(msiof1_rxd),
3877                 SH_PFC_PIN_GROUP(msiof2_clk_a),
3878                 SH_PFC_PIN_GROUP(msiof2_sync_a),
3879                 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3880                 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3881                 SH_PFC_PIN_GROUP(msiof2_txd_a),
3882                 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3883                 SH_PFC_PIN_GROUP(msiof2_clk_b),
3884                 SH_PFC_PIN_GROUP(msiof2_sync_b),
3885                 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3886                 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3887                 SH_PFC_PIN_GROUP(msiof2_txd_b),
3888                 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3889                 SH_PFC_PIN_GROUP(msiof3_clk_a),
3890                 SH_PFC_PIN_GROUP(msiof3_sync_a),
3891                 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3892                 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3893                 SH_PFC_PIN_GROUP(msiof3_txd_a),
3894                 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3895                 SH_PFC_PIN_GROUP(msiof3_clk_b),
3896                 SH_PFC_PIN_GROUP(msiof3_sync_b),
3897                 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3898                 SH_PFC_PIN_GROUP(msiof3_txd_b),
3899                 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3900                 SH_PFC_PIN_GROUP(pwm0_a),
3901                 SH_PFC_PIN_GROUP(pwm0_b),
3902                 SH_PFC_PIN_GROUP(pwm1_a),
3903                 SH_PFC_PIN_GROUP(pwm1_b),
3904                 SH_PFC_PIN_GROUP(pwm2_a),
3905                 SH_PFC_PIN_GROUP(pwm2_b),
3906                 SH_PFC_PIN_GROUP(pwm2_c),
3907                 SH_PFC_PIN_GROUP(pwm3_a),
3908                 SH_PFC_PIN_GROUP(pwm3_b),
3909                 SH_PFC_PIN_GROUP(pwm3_c),
3910                 SH_PFC_PIN_GROUP(pwm4_a),
3911                 SH_PFC_PIN_GROUP(pwm4_b),
3912                 SH_PFC_PIN_GROUP(pwm5_a),
3913                 SH_PFC_PIN_GROUP(pwm5_b),
3914                 SH_PFC_PIN_GROUP(pwm6_a),
3915                 SH_PFC_PIN_GROUP(pwm6_b),
3916                 SH_PFC_PIN_GROUP(scif0_data_a),
3917                 SH_PFC_PIN_GROUP(scif0_clk_a),
3918                 SH_PFC_PIN_GROUP(scif0_ctrl_a),
3919                 SH_PFC_PIN_GROUP(scif0_data_b),
3920                 SH_PFC_PIN_GROUP(scif0_clk_b),
3921                 SH_PFC_PIN_GROUP(scif1_data),
3922                 SH_PFC_PIN_GROUP(scif1_clk),
3923                 SH_PFC_PIN_GROUP(scif1_ctrl),
3924                 SH_PFC_PIN_GROUP(scif2_data_a),
3925                 SH_PFC_PIN_GROUP(scif2_clk_a),
3926                 SH_PFC_PIN_GROUP(scif2_data_b),
3927                 SH_PFC_PIN_GROUP(scif3_data_a),
3928                 SH_PFC_PIN_GROUP(scif3_clk_a),
3929                 SH_PFC_PIN_GROUP(scif3_ctrl_a),
3930                 SH_PFC_PIN_GROUP(scif3_data_b),
3931                 SH_PFC_PIN_GROUP(scif3_data_c),
3932                 SH_PFC_PIN_GROUP(scif3_clk_c),
3933                 SH_PFC_PIN_GROUP(scif4_data_a),
3934                 SH_PFC_PIN_GROUP(scif4_clk_a),
3935                 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3936                 SH_PFC_PIN_GROUP(scif4_data_b),
3937                 SH_PFC_PIN_GROUP(scif4_clk_b),
3938                 SH_PFC_PIN_GROUP(scif4_data_c),
3939                 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3940                 SH_PFC_PIN_GROUP(scif5_data_a),
3941                 SH_PFC_PIN_GROUP(scif5_clk_a),
3942                 SH_PFC_PIN_GROUP(scif5_data_b),
3943                 SH_PFC_PIN_GROUP(scif5_data_c),
3944                 SH_PFC_PIN_GROUP(scif_clk_a),
3945                 SH_PFC_PIN_GROUP(scif_clk_b),
3946                 SH_PFC_PIN_GROUP(sdhi0_data1),
3947                 SH_PFC_PIN_GROUP(sdhi0_data4),
3948                 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3949                 SH_PFC_PIN_GROUP(sdhi0_cd),
3950                 SH_PFC_PIN_GROUP(sdhi0_wp),
3951                 SH_PFC_PIN_GROUP(sdhi1_data1),
3952                 SH_PFC_PIN_GROUP(sdhi1_data4),
3953                 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3954                 SH_PFC_PIN_GROUP(sdhi1_cd),
3955                 SH_PFC_PIN_GROUP(sdhi1_wp),
3956                 SH_PFC_PIN_GROUP(sdhi3_data1),
3957                 SH_PFC_PIN_GROUP(sdhi3_data4),
3958                 SH_PFC_PIN_GROUP(sdhi3_data8),
3959                 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3960                 SH_PFC_PIN_GROUP(sdhi3_cd),
3961                 SH_PFC_PIN_GROUP(sdhi3_wp),
3962                 SH_PFC_PIN_GROUP(sdhi3_ds),
3963                 SH_PFC_PIN_GROUP(ssi0_data),
3964                 SH_PFC_PIN_GROUP(ssi01239_ctrl),
3965                 SH_PFC_PIN_GROUP(ssi1_data),
3966                 SH_PFC_PIN_GROUP(ssi1_ctrl),
3967                 SH_PFC_PIN_GROUP(ssi2_data),
3968                 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3969                 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3970                 SH_PFC_PIN_GROUP(ssi3_data),
3971                 SH_PFC_PIN_GROUP(ssi349_ctrl),
3972                 SH_PFC_PIN_GROUP(ssi4_data),
3973                 SH_PFC_PIN_GROUP(ssi4_ctrl),
3974                 SH_PFC_PIN_GROUP(ssi5_data),
3975                 SH_PFC_PIN_GROUP(ssi5_ctrl),
3976                 SH_PFC_PIN_GROUP(ssi6_data),
3977                 SH_PFC_PIN_GROUP(ssi6_ctrl),
3978                 SH_PFC_PIN_GROUP(ssi7_data),
3979                 SH_PFC_PIN_GROUP(ssi78_ctrl),
3980                 SH_PFC_PIN_GROUP(ssi8_data),
3981                 SH_PFC_PIN_GROUP(ssi9_data),
3982                 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3983                 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3984                 SH_PFC_PIN_GROUP(tmu_tclk1_a),
3985                 SH_PFC_PIN_GROUP(tmu_tclk1_b),
3986                 SH_PFC_PIN_GROUP(tmu_tclk2_a),
3987                 SH_PFC_PIN_GROUP(tmu_tclk2_b),
3988                 SH_PFC_PIN_GROUP(usb0_a),
3989                 SH_PFC_PIN_GROUP(usb0_b),
3990                 SH_PFC_PIN_GROUP(usb0_id),
3991                 SH_PFC_PIN_GROUP(usb30),
3992                 SH_PFC_PIN_GROUP(usb30_id),
3993                 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
3994                 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
3995                 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
3996                 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
3997                 SH_PFC_PIN_GROUP(vin4_data18_a),
3998                 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
3999                 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4000                 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4001                 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4002                 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4003                 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4004                 SH_PFC_PIN_GROUP(vin4_data18_b),
4005                 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4006                 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4007                 SH_PFC_PIN_GROUP(vin4_sync),
4008                 SH_PFC_PIN_GROUP(vin4_field),
4009                 SH_PFC_PIN_GROUP(vin4_clkenb),
4010                 SH_PFC_PIN_GROUP(vin4_clk),
4011                 VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
4012                 VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
4013                 VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
4014                 VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
4015                 SH_PFC_PIN_GROUP(vin5_data8_b),
4016                 SH_PFC_PIN_GROUP(vin5_sync_a),
4017                 SH_PFC_PIN_GROUP(vin5_field_a),
4018                 SH_PFC_PIN_GROUP(vin5_clkenb_a),
4019                 SH_PFC_PIN_GROUP(vin5_clk_a),
4020                 SH_PFC_PIN_GROUP(vin5_clk_b),
4021         },
4022         .automotive = {
4023                 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4024                 SH_PFC_PIN_GROUP(drif0_data0_a),
4025                 SH_PFC_PIN_GROUP(drif0_data1_a),
4026                 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4027                 SH_PFC_PIN_GROUP(drif0_data0_b),
4028                 SH_PFC_PIN_GROUP(drif0_data1_b),
4029                 SH_PFC_PIN_GROUP(drif1_ctrl),
4030                 SH_PFC_PIN_GROUP(drif1_data0),
4031                 SH_PFC_PIN_GROUP(drif1_data1),
4032                 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4033                 SH_PFC_PIN_GROUP(drif2_data0_a),
4034                 SH_PFC_PIN_GROUP(drif2_data1_a),
4035                 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4036                 SH_PFC_PIN_GROUP(drif2_data0_b),
4037                 SH_PFC_PIN_GROUP(drif2_data1_b),
4038                 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4039                 SH_PFC_PIN_GROUP(drif3_data0_a),
4040                 SH_PFC_PIN_GROUP(drif3_data1_a),
4041                 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4042                 SH_PFC_PIN_GROUP(drif3_data0_b),
4043                 SH_PFC_PIN_GROUP(drif3_data1_b),
4044         }
4045 };
4046
4047 static const char * const audio_clk_groups[] = {
4048         "audio_clk_a",
4049         "audio_clk_b_a",
4050         "audio_clk_b_b",
4051         "audio_clk_b_c",
4052         "audio_clk_c_a",
4053         "audio_clk_c_b",
4054         "audio_clk_c_c",
4055         "audio_clkout_a",
4056         "audio_clkout_b",
4057         "audio_clkout1_a",
4058         "audio_clkout1_b",
4059         "audio_clkout1_c",
4060         "audio_clkout2_a",
4061         "audio_clkout2_b",
4062         "audio_clkout2_c",
4063         "audio_clkout3_a",
4064         "audio_clkout3_b",
4065         "audio_clkout3_c",
4066 };
4067
4068 static const char * const avb_groups[] = {
4069         "avb_link",
4070         "avb_magic",
4071         "avb_phy_int",
4072         "avb_mii",
4073         "avb_avtp_pps",
4074         "avb_avtp_match_a",
4075         "avb_avtp_capture_a",
4076 };
4077
4078 static const char * const can0_groups[] = {
4079         "can0_data",
4080 };
4081
4082 static const char * const can1_groups[] = {
4083         "can1_data",
4084 };
4085
4086 static const char * const can_clk_groups[] = {
4087         "can_clk",
4088 };
4089
4090 static const char * const canfd0_groups[] = {
4091         "canfd0_data",
4092 };
4093
4094 static const char * const canfd1_groups[] = {
4095         "canfd1_data",
4096 };
4097
4098 static const char * const drif0_groups[] = {
4099         "drif0_ctrl_a",
4100         "drif0_data0_a",
4101         "drif0_data1_a",
4102         "drif0_ctrl_b",
4103         "drif0_data0_b",
4104         "drif0_data1_b",
4105 };
4106
4107 static const char * const drif1_groups[] = {
4108         "drif1_ctrl",
4109         "drif1_data0",
4110         "drif1_data1",
4111 };
4112
4113 static const char * const drif2_groups[] = {
4114         "drif2_ctrl_a",
4115         "drif2_data0_a",
4116         "drif2_data1_a",
4117         "drif2_ctrl_b",
4118         "drif2_data0_b",
4119         "drif2_data1_b",
4120 };
4121
4122 static const char * const drif3_groups[] = {
4123         "drif3_ctrl_a",
4124         "drif3_data0_a",
4125         "drif3_data1_a",
4126         "drif3_ctrl_b",
4127         "drif3_data0_b",
4128         "drif3_data1_b",
4129 };
4130
4131 static const char * const du_groups[] = {
4132         "du_rgb666",
4133         "du_rgb888",
4134         "du_clk_in_0",
4135         "du_clk_in_1",
4136         "du_clk_out_0",
4137         "du_sync",
4138         "du_disp_cde",
4139         "du_cde",
4140         "du_disp",
4141 };
4142
4143 static const char * const hscif0_groups[] = {
4144         "hscif0_data_a",
4145         "hscif0_clk_a",
4146         "hscif0_ctrl_a",
4147         "hscif0_data_b",
4148         "hscif0_clk_b",
4149 };
4150
4151 static const char * const hscif1_groups[] = {
4152         "hscif1_data_a",
4153         "hscif1_clk_a",
4154         "hscif1_data_b",
4155         "hscif1_clk_b",
4156         "hscif1_ctrl_b",
4157 };
4158
4159 static const char * const hscif2_groups[] = {
4160         "hscif2_data_a",
4161         "hscif2_clk_a",
4162         "hscif2_ctrl_a",
4163         "hscif2_data_b",
4164 };
4165
4166 static const char * const hscif3_groups[] = {
4167         "hscif3_data_a",
4168         "hscif3_data_b",
4169         "hscif3_clk_b",
4170         "hscif3_data_c",
4171         "hscif3_clk_c",
4172         "hscif3_ctrl_c",
4173         "hscif3_data_d",
4174         "hscif3_data_e",
4175         "hscif3_ctrl_e",
4176 };
4177
4178 static const char * const hscif4_groups[] = {
4179         "hscif4_data_a",
4180         "hscif4_clk_a",
4181         "hscif4_ctrl_a",
4182         "hscif4_data_b",
4183         "hscif4_clk_b",
4184         "hscif4_data_c",
4185         "hscif4_data_d",
4186         "hscif4_data_e",
4187 };
4188
4189 static const char * const i2c1_groups[] = {
4190         "i2c1_a",
4191         "i2c1_b",
4192         "i2c1_c",
4193         "i2c1_d",
4194 };
4195
4196 static const char * const i2c2_groups[] = {
4197         "i2c2_a",
4198         "i2c2_b",
4199         "i2c2_c",
4200         "i2c2_d",
4201         "i2c2_e",
4202 };
4203
4204 static const char * const i2c4_groups[] = {
4205         "i2c4",
4206 };
4207
4208 static const char * const i2c5_groups[] = {
4209         "i2c5",
4210 };
4211
4212 static const char * const i2c6_groups[] = {
4213         "i2c6_a",
4214         "i2c6_b",
4215 };
4216
4217 static const char * const i2c7_groups[] = {
4218         "i2c7_a",
4219         "i2c7_b",
4220 };
4221
4222 static const char * const intc_ex_groups[] = {
4223         "intc_ex_irq0",
4224         "intc_ex_irq1",
4225         "intc_ex_irq2",
4226         "intc_ex_irq3",
4227         "intc_ex_irq4",
4228         "intc_ex_irq5",
4229 };
4230
4231 static const char * const msiof0_groups[] = {
4232         "msiof0_clk",
4233         "msiof0_sync",
4234         "msiof0_ss1",
4235         "msiof0_ss2",
4236         "msiof0_txd",
4237         "msiof0_rxd",
4238 };
4239
4240 static const char * const msiof1_groups[] = {
4241         "msiof1_clk",
4242         "msiof1_sync",
4243         "msiof1_ss1",
4244         "msiof1_ss2",
4245         "msiof1_txd",
4246         "msiof1_rxd",
4247 };
4248
4249 static const char * const msiof2_groups[] = {
4250         "msiof2_clk_a",
4251         "msiof2_sync_a",
4252         "msiof2_ss1_a",
4253         "msiof2_ss2_a",
4254         "msiof2_txd_a",
4255         "msiof2_rxd_a",
4256         "msiof2_clk_b",
4257         "msiof2_sync_b",
4258         "msiof2_ss1_b",
4259         "msiof2_ss2_b",
4260         "msiof2_txd_b",
4261         "msiof2_rxd_b",
4262 };
4263
4264 static const char * const msiof3_groups[] = {
4265         "msiof3_clk_a",
4266         "msiof3_sync_a",
4267         "msiof3_ss1_a",
4268         "msiof3_ss2_a",
4269         "msiof3_txd_a",
4270         "msiof3_rxd_a",
4271         "msiof3_clk_b",
4272         "msiof3_sync_b",
4273         "msiof3_ss1_b",
4274         "msiof3_txd_b",
4275         "msiof3_rxd_b",
4276 };
4277
4278 static const char * const pwm0_groups[] = {
4279         "pwm0_a",
4280         "pwm0_b",
4281 };
4282
4283 static const char * const pwm1_groups[] = {
4284         "pwm1_a",
4285         "pwm1_b",
4286 };
4287
4288 static const char * const pwm2_groups[] = {
4289         "pwm2_a",
4290         "pwm2_b",
4291         "pwm2_c",
4292 };
4293
4294 static const char * const pwm3_groups[] = {
4295         "pwm3_a",
4296         "pwm3_b",
4297         "pwm3_c",
4298 };
4299
4300 static const char * const pwm4_groups[] = {
4301         "pwm4_a",
4302         "pwm4_b",
4303 };
4304
4305 static const char * const pwm5_groups[] = {
4306         "pwm5_a",
4307         "pwm5_b",
4308 };
4309
4310 static const char * const pwm6_groups[] = {
4311         "pwm6_a",
4312         "pwm6_b",
4313 };
4314
4315 static const char * const scif0_groups[] = {
4316         "scif0_data_a",
4317         "scif0_clk_a",
4318         "scif0_ctrl_a",
4319         "scif0_data_b",
4320         "scif0_clk_b",
4321 };
4322
4323 static const char * const scif1_groups[] = {
4324         "scif1_data",
4325         "scif1_clk",
4326         "scif1_ctrl",
4327 };
4328
4329 static const char * const scif2_groups[] = {
4330         "scif2_data_a",
4331         "scif2_clk_a",
4332         "scif2_data_b",
4333 };
4334
4335 static const char * const scif3_groups[] = {
4336         "scif3_data_a",
4337         "scif3_clk_a",
4338         "scif3_ctrl_a",
4339         "scif3_data_b",
4340         "scif3_data_c",
4341         "scif3_clk_c",
4342 };
4343
4344 static const char * const scif4_groups[] = {
4345         "scif4_data_a",
4346         "scif4_clk_a",
4347         "scif4_ctrl_a",
4348         "scif4_data_b",
4349         "scif4_clk_b",
4350         "scif4_data_c",
4351         "scif4_ctrl_c",
4352 };
4353
4354 static const char * const scif5_groups[] = {
4355         "scif5_data_a",
4356         "scif5_clk_a",
4357         "scif5_data_b",
4358         "scif5_data_c",
4359 };
4360
4361 static const char * const scif_clk_groups[] = {
4362         "scif_clk_a",
4363         "scif_clk_b",
4364 };
4365
4366 static const char * const sdhi0_groups[] = {
4367         "sdhi0_data1",
4368         "sdhi0_data4",
4369         "sdhi0_ctrl",
4370         "sdhi0_cd",
4371         "sdhi0_wp",
4372 };
4373
4374 static const char * const sdhi1_groups[] = {
4375         "sdhi1_data1",
4376         "sdhi1_data4",
4377         "sdhi1_ctrl",
4378         "sdhi1_cd",
4379         "sdhi1_wp",
4380 };
4381
4382 static const char * const sdhi3_groups[] = {
4383         "sdhi3_data1",
4384         "sdhi3_data4",
4385         "sdhi3_data8",
4386         "sdhi3_ctrl",
4387         "sdhi3_cd",
4388         "sdhi3_wp",
4389         "sdhi3_ds",
4390 };
4391
4392 static const char * const ssi_groups[] = {
4393         "ssi0_data",
4394         "ssi01239_ctrl",
4395         "ssi1_data",
4396         "ssi1_ctrl",
4397         "ssi2_data",
4398         "ssi2_ctrl_a",
4399         "ssi2_ctrl_b",
4400         "ssi3_data",
4401         "ssi349_ctrl",
4402         "ssi4_data",
4403         "ssi4_ctrl",
4404         "ssi5_data",
4405         "ssi5_ctrl",
4406         "ssi6_data",
4407         "ssi6_ctrl",
4408         "ssi7_data",
4409         "ssi78_ctrl",
4410         "ssi8_data",
4411         "ssi9_data",
4412         "ssi9_ctrl_a",
4413         "ssi9_ctrl_b",
4414 };
4415
4416 static const char * const tmu_groups[] = {
4417         "tmu_tclk1_a",
4418         "tmu_tclk1_b",
4419         "tmu_tclk2_a",
4420         "tmu_tclk2_b",
4421 };
4422
4423 static const char * const usb0_groups[] = {
4424         "usb0_a",
4425         "usb0_b",
4426         "usb0_id",
4427 };
4428
4429 static const char * const usb30_groups[] = {
4430         "usb30",
4431         "usb30_id",
4432 };
4433
4434 static const char * const vin4_groups[] = {
4435         "vin4_data8_a",
4436         "vin4_data10_a",
4437         "vin4_data12_a",
4438         "vin4_data16_a",
4439         "vin4_data18_a",
4440         "vin4_data20_a",
4441         "vin4_data24_a",
4442         "vin4_data8_b",
4443         "vin4_data10_b",
4444         "vin4_data12_b",
4445         "vin4_data16_b",
4446         "vin4_data18_b",
4447         "vin4_data20_b",
4448         "vin4_data24_b",
4449         "vin4_sync",
4450         "vin4_field",
4451         "vin4_clkenb",
4452         "vin4_clk",
4453 };
4454
4455 static const char * const vin5_groups[] = {
4456         "vin5_data8_a",
4457         "vin5_data10_a",
4458         "vin5_data12_a",
4459         "vin5_data16_a",
4460         "vin5_data8_b",
4461         "vin5_sync_a",
4462         "vin5_field_a",
4463         "vin5_clkenb_a",
4464         "vin5_clk_a",
4465         "vin5_clk_b",
4466 };
4467
4468 static const struct {
4469         struct sh_pfc_function common[47];
4470         struct sh_pfc_function automotive[4];
4471 } pinmux_functions = {
4472         .common = {
4473                 SH_PFC_FUNCTION(audio_clk),
4474                 SH_PFC_FUNCTION(avb),
4475                 SH_PFC_FUNCTION(can0),
4476                 SH_PFC_FUNCTION(can1),
4477                 SH_PFC_FUNCTION(can_clk),
4478                 SH_PFC_FUNCTION(canfd0),
4479                 SH_PFC_FUNCTION(canfd1),
4480                 SH_PFC_FUNCTION(du),
4481                 SH_PFC_FUNCTION(hscif0),
4482                 SH_PFC_FUNCTION(hscif1),
4483                 SH_PFC_FUNCTION(hscif2),
4484                 SH_PFC_FUNCTION(hscif3),
4485                 SH_PFC_FUNCTION(hscif4),
4486                 SH_PFC_FUNCTION(i2c1),
4487                 SH_PFC_FUNCTION(i2c2),
4488                 SH_PFC_FUNCTION(i2c4),
4489                 SH_PFC_FUNCTION(i2c5),
4490                 SH_PFC_FUNCTION(i2c6),
4491                 SH_PFC_FUNCTION(i2c7),
4492                 SH_PFC_FUNCTION(intc_ex),
4493                 SH_PFC_FUNCTION(msiof0),
4494                 SH_PFC_FUNCTION(msiof1),
4495                 SH_PFC_FUNCTION(msiof2),
4496                 SH_PFC_FUNCTION(msiof3),
4497                 SH_PFC_FUNCTION(pwm0),
4498                 SH_PFC_FUNCTION(pwm1),
4499                 SH_PFC_FUNCTION(pwm2),
4500                 SH_PFC_FUNCTION(pwm3),
4501                 SH_PFC_FUNCTION(pwm4),
4502                 SH_PFC_FUNCTION(pwm5),
4503                 SH_PFC_FUNCTION(pwm6),
4504                 SH_PFC_FUNCTION(scif0),
4505                 SH_PFC_FUNCTION(scif1),
4506                 SH_PFC_FUNCTION(scif2),
4507                 SH_PFC_FUNCTION(scif3),
4508                 SH_PFC_FUNCTION(scif4),
4509                 SH_PFC_FUNCTION(scif5),
4510                 SH_PFC_FUNCTION(scif_clk),
4511                 SH_PFC_FUNCTION(sdhi0),
4512                 SH_PFC_FUNCTION(sdhi1),
4513                 SH_PFC_FUNCTION(sdhi3),
4514                 SH_PFC_FUNCTION(ssi),
4515                 SH_PFC_FUNCTION(tmu),
4516                 SH_PFC_FUNCTION(usb0),
4517                 SH_PFC_FUNCTION(usb30),
4518                 SH_PFC_FUNCTION(vin4),
4519                 SH_PFC_FUNCTION(vin5),
4520         },
4521         .automotive = {
4522                 SH_PFC_FUNCTION(drif0),
4523                 SH_PFC_FUNCTION(drif1),
4524                 SH_PFC_FUNCTION(drif2),
4525                 SH_PFC_FUNCTION(drif3),
4526         }
4527 };
4528
4529 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4530 #define F_(x, y)        FN_##y
4531 #define FM(x)           FN_##x
4532         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
4533                 0, 0,
4534                 0, 0,
4535                 0, 0,
4536                 0, 0,
4537                 0, 0,
4538                 0, 0,
4539                 0, 0,
4540                 0, 0,
4541                 0, 0,
4542                 0, 0,
4543                 0, 0,
4544                 0, 0,
4545                 0, 0,
4546                 0, 0,
4547                 GP_0_17_FN,     GPSR0_17,
4548                 GP_0_16_FN,     GPSR0_16,
4549                 GP_0_15_FN,     GPSR0_15,
4550                 GP_0_14_FN,     GPSR0_14,
4551                 GP_0_13_FN,     GPSR0_13,
4552                 GP_0_12_FN,     GPSR0_12,
4553                 GP_0_11_FN,     GPSR0_11,
4554                 GP_0_10_FN,     GPSR0_10,
4555                 GP_0_9_FN,      GPSR0_9,
4556                 GP_0_8_FN,      GPSR0_8,
4557                 GP_0_7_FN,      GPSR0_7,
4558                 GP_0_6_FN,      GPSR0_6,
4559                 GP_0_5_FN,      GPSR0_5,
4560                 GP_0_4_FN,      GPSR0_4,
4561                 GP_0_3_FN,      GPSR0_3,
4562                 GP_0_2_FN,      GPSR0_2,
4563                 GP_0_1_FN,      GPSR0_1,
4564                 GP_0_0_FN,      GPSR0_0, ))
4565         },
4566         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
4567                 0, 0,
4568                 0, 0,
4569                 0, 0,
4570                 0, 0,
4571                 0, 0,
4572                 0, 0,
4573                 0, 0,
4574                 0, 0,
4575                 0, 0,
4576                 GP_1_22_FN,     GPSR1_22,
4577                 GP_1_21_FN,     GPSR1_21,
4578                 GP_1_20_FN,     GPSR1_20,
4579                 GP_1_19_FN,     GPSR1_19,
4580                 GP_1_18_FN,     GPSR1_18,
4581                 GP_1_17_FN,     GPSR1_17,
4582                 GP_1_16_FN,     GPSR1_16,
4583                 GP_1_15_FN,     GPSR1_15,
4584                 GP_1_14_FN,     GPSR1_14,
4585                 GP_1_13_FN,     GPSR1_13,
4586                 GP_1_12_FN,     GPSR1_12,
4587                 GP_1_11_FN,     GPSR1_11,
4588                 GP_1_10_FN,     GPSR1_10,
4589                 GP_1_9_FN,      GPSR1_9,
4590                 GP_1_8_FN,      GPSR1_8,
4591                 GP_1_7_FN,      GPSR1_7,
4592                 GP_1_6_FN,      GPSR1_6,
4593                 GP_1_5_FN,      GPSR1_5,
4594                 GP_1_4_FN,      GPSR1_4,
4595                 GP_1_3_FN,      GPSR1_3,
4596                 GP_1_2_FN,      GPSR1_2,
4597                 GP_1_1_FN,      GPSR1_1,
4598                 GP_1_0_FN,      GPSR1_0, ))
4599         },
4600         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4601                 0, 0,
4602                 0, 0,
4603                 0, 0,
4604                 0, 0,
4605                 0, 0,
4606                 0, 0,
4607                 GP_2_25_FN,     GPSR2_25,
4608                 GP_2_24_FN,     GPSR2_24,
4609                 GP_2_23_FN,     GPSR2_23,
4610                 GP_2_22_FN,     GPSR2_22,
4611                 GP_2_21_FN,     GPSR2_21,
4612                 GP_2_20_FN,     GPSR2_20,
4613                 GP_2_19_FN,     GPSR2_19,
4614                 GP_2_18_FN,     GPSR2_18,
4615                 GP_2_17_FN,     GPSR2_17,
4616                 GP_2_16_FN,     GPSR2_16,
4617                 GP_2_15_FN,     GPSR2_15,
4618                 GP_2_14_FN,     GPSR2_14,
4619                 GP_2_13_FN,     GPSR2_13,
4620                 GP_2_12_FN,     GPSR2_12,
4621                 GP_2_11_FN,     GPSR2_11,
4622                 GP_2_10_FN,     GPSR2_10,
4623                 GP_2_9_FN,      GPSR2_9,
4624                 GP_2_8_FN,      GPSR2_8,
4625                 GP_2_7_FN,      GPSR2_7,
4626                 GP_2_6_FN,      GPSR2_6,
4627                 GP_2_5_FN,      GPSR2_5,
4628                 GP_2_4_FN,      GPSR2_4,
4629                 GP_2_3_FN,      GPSR2_3,
4630                 GP_2_2_FN,      GPSR2_2,
4631                 GP_2_1_FN,      GPSR2_1,
4632                 GP_2_0_FN,      GPSR2_0, ))
4633         },
4634         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
4635                 0, 0,
4636                 0, 0,
4637                 0, 0,
4638                 0, 0,
4639                 0, 0,
4640                 0, 0,
4641                 0, 0,
4642                 0, 0,
4643                 0, 0,
4644                 0, 0,
4645                 0, 0,
4646                 0, 0,
4647                 0, 0,
4648                 0, 0,
4649                 0, 0,
4650                 0, 0,
4651                 GP_3_15_FN,     GPSR3_15,
4652                 GP_3_14_FN,     GPSR3_14,
4653                 GP_3_13_FN,     GPSR3_13,
4654                 GP_3_12_FN,     GPSR3_12,
4655                 GP_3_11_FN,     GPSR3_11,
4656                 GP_3_10_FN,     GPSR3_10,
4657                 GP_3_9_FN,      GPSR3_9,
4658                 GP_3_8_FN,      GPSR3_8,
4659                 GP_3_7_FN,      GPSR3_7,
4660                 GP_3_6_FN,      GPSR3_6,
4661                 GP_3_5_FN,      GPSR3_5,
4662                 GP_3_4_FN,      GPSR3_4,
4663                 GP_3_3_FN,      GPSR3_3,
4664                 GP_3_2_FN,      GPSR3_2,
4665                 GP_3_1_FN,      GPSR3_1,
4666                 GP_3_0_FN,      GPSR3_0, ))
4667         },
4668         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
4669                 0, 0,
4670                 0, 0,
4671                 0, 0,
4672                 0, 0,
4673                 0, 0,
4674                 0, 0,
4675                 0, 0,
4676                 0, 0,
4677                 0, 0,
4678                 0, 0,
4679                 0, 0,
4680                 0, 0,
4681                 0, 0,
4682                 0, 0,
4683                 0, 0,
4684                 0, 0,
4685                 0, 0,
4686                 0, 0,
4687                 0, 0,
4688                 0, 0,
4689                 0, 0,
4690                 GP_4_10_FN,     GPSR4_10,
4691                 GP_4_9_FN,      GPSR4_9,
4692                 GP_4_8_FN,      GPSR4_8,
4693                 GP_4_7_FN,      GPSR4_7,
4694                 GP_4_6_FN,      GPSR4_6,
4695                 GP_4_5_FN,      GPSR4_5,
4696                 GP_4_4_FN,      GPSR4_4,
4697                 GP_4_3_FN,      GPSR4_3,
4698                 GP_4_2_FN,      GPSR4_2,
4699                 GP_4_1_FN,      GPSR4_1,
4700                 GP_4_0_FN,      GPSR4_0, ))
4701         },
4702         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
4703                 0, 0,
4704                 0, 0,
4705                 0, 0,
4706                 0, 0,
4707                 0, 0,
4708                 0, 0,
4709                 0, 0,
4710                 0, 0,
4711                 0, 0,
4712                 0, 0,
4713                 0, 0,
4714                 0, 0,
4715                 GP_5_19_FN,     GPSR5_19,
4716                 GP_5_18_FN,     GPSR5_18,
4717                 GP_5_17_FN,     GPSR5_17,
4718                 GP_5_16_FN,     GPSR5_16,
4719                 GP_5_15_FN,     GPSR5_15,
4720                 GP_5_14_FN,     GPSR5_14,
4721                 GP_5_13_FN,     GPSR5_13,
4722                 GP_5_12_FN,     GPSR5_12,
4723                 GP_5_11_FN,     GPSR5_11,
4724                 GP_5_10_FN,     GPSR5_10,
4725                 GP_5_9_FN,      GPSR5_9,
4726                 GP_5_8_FN,      GPSR5_8,
4727                 GP_5_7_FN,      GPSR5_7,
4728                 GP_5_6_FN,      GPSR5_6,
4729                 GP_5_5_FN,      GPSR5_5,
4730                 GP_5_4_FN,      GPSR5_4,
4731                 GP_5_3_FN,      GPSR5_3,
4732                 GP_5_2_FN,      GPSR5_2,
4733                 GP_5_1_FN,      GPSR5_1,
4734                 GP_5_0_FN,      GPSR5_0, ))
4735         },
4736         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
4737                 0, 0,
4738                 0, 0,
4739                 0, 0,
4740                 0, 0,
4741                 0, 0,
4742                 0, 0,
4743                 0, 0,
4744                 0, 0,
4745                 0, 0,
4746                 0, 0,
4747                 0, 0,
4748                 0, 0,
4749                 0, 0,
4750                 0, 0,
4751                 GP_6_17_FN,     GPSR6_17,
4752                 GP_6_16_FN,     GPSR6_16,
4753                 GP_6_15_FN,     GPSR6_15,
4754                 GP_6_14_FN,     GPSR6_14,
4755                 GP_6_13_FN,     GPSR6_13,
4756                 GP_6_12_FN,     GPSR6_12,
4757                 GP_6_11_FN,     GPSR6_11,
4758                 GP_6_10_FN,     GPSR6_10,
4759                 GP_6_9_FN,      GPSR6_9,
4760                 GP_6_8_FN,      GPSR6_8,
4761                 GP_6_7_FN,      GPSR6_7,
4762                 GP_6_6_FN,      GPSR6_6,
4763                 GP_6_5_FN,      GPSR6_5,
4764                 GP_6_4_FN,      GPSR6_4,
4765                 GP_6_3_FN,      GPSR6_3,
4766                 GP_6_2_FN,      GPSR6_2,
4767                 GP_6_1_FN,      GPSR6_1,
4768                 GP_6_0_FN,      GPSR6_0, ))
4769         },
4770 #undef F_
4771 #undef FM
4772
4773 #define F_(x, y)        x,
4774 #define FM(x)           FN_##x,
4775         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
4776                 IP0_31_28
4777                 IP0_27_24
4778                 IP0_23_20
4779                 IP0_19_16
4780                 IP0_15_12
4781                 IP0_11_8
4782                 IP0_7_4
4783                 IP0_3_0 ))
4784         },
4785         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
4786                 IP1_31_28
4787                 IP1_27_24
4788                 IP1_23_20
4789                 IP1_19_16
4790                 IP1_15_12
4791                 IP1_11_8
4792                 IP1_7_4
4793                 IP1_3_0 ))
4794         },
4795         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
4796                 IP2_31_28
4797                 IP2_27_24
4798                 IP2_23_20
4799                 IP2_19_16
4800                 IP2_15_12
4801                 IP2_11_8
4802                 IP2_7_4
4803                 IP2_3_0 ))
4804         },
4805         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
4806                 IP3_31_28
4807                 IP3_27_24
4808                 IP3_23_20
4809                 IP3_19_16
4810                 IP3_15_12
4811                 IP3_11_8
4812                 IP3_7_4
4813                 IP3_3_0 ))
4814         },
4815         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
4816                 IP4_31_28
4817                 IP4_27_24
4818                 IP4_23_20
4819                 IP4_19_16
4820                 IP4_15_12
4821                 IP4_11_8
4822                 IP4_7_4
4823                 IP4_3_0 ))
4824         },
4825         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
4826                 IP5_31_28
4827                 IP5_27_24
4828                 IP5_23_20
4829                 IP5_19_16
4830                 IP5_15_12
4831                 IP5_11_8
4832                 IP5_7_4
4833                 IP5_3_0 ))
4834         },
4835         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
4836                 IP6_31_28
4837                 IP6_27_24
4838                 IP6_23_20
4839                 IP6_19_16
4840                 IP6_15_12
4841                 IP6_11_8
4842                 IP6_7_4
4843                 IP6_3_0 ))
4844         },
4845         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
4846                 IP7_31_28
4847                 IP7_27_24
4848                 IP7_23_20
4849                 IP7_19_16
4850                 IP7_15_12
4851                 IP7_11_8
4852                 IP7_7_4
4853                 IP7_3_0 ))
4854         },
4855         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
4856                 IP8_31_28
4857                 IP8_27_24
4858                 IP8_23_20
4859                 IP8_19_16
4860                 IP8_15_12
4861                 IP8_11_8
4862                 IP8_7_4
4863                 IP8_3_0 ))
4864         },
4865         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
4866                 IP9_31_28
4867                 IP9_27_24
4868                 IP9_23_20
4869                 IP9_19_16
4870                 IP9_15_12
4871                 IP9_11_8
4872                 IP9_7_4
4873                 IP9_3_0 ))
4874         },
4875         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
4876                 IP10_31_28
4877                 IP10_27_24
4878                 IP10_23_20
4879                 IP10_19_16
4880                 IP10_15_12
4881                 IP10_11_8
4882                 IP10_7_4
4883                 IP10_3_0 ))
4884         },
4885         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
4886                 IP11_31_28
4887                 IP11_27_24
4888                 IP11_23_20
4889                 IP11_19_16
4890                 IP11_15_12
4891                 IP11_11_8
4892                 IP11_7_4
4893                 IP11_3_0 ))
4894         },
4895         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
4896                 IP12_31_28
4897                 IP12_27_24
4898                 IP12_23_20
4899                 IP12_19_16
4900                 IP12_15_12
4901                 IP12_11_8
4902                 IP12_7_4
4903                 IP12_3_0 ))
4904         },
4905         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
4906                 IP13_31_28
4907                 IP13_27_24
4908                 IP13_23_20
4909                 IP13_19_16
4910                 IP13_15_12
4911                 IP13_11_8
4912                 IP13_7_4
4913                 IP13_3_0 ))
4914         },
4915         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
4916                 IP14_31_28
4917                 IP14_27_24
4918                 IP14_23_20
4919                 IP14_19_16
4920                 IP14_15_12
4921                 IP14_11_8
4922                 IP14_7_4
4923                 IP14_3_0 ))
4924         },
4925         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
4926                 IP15_31_28
4927                 IP15_27_24
4928                 IP15_23_20
4929                 IP15_19_16
4930                 IP15_15_12
4931                 IP15_11_8
4932                 IP15_7_4
4933                 IP15_3_0 ))
4934         },
4935 #undef F_
4936 #undef FM
4937
4938 #define F_(x, y)        x,
4939 #define FM(x)           FN_##x,
4940         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4941                              GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
4942                                    1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
4943                              GROUP(
4944                 /* RESERVED 31 */
4945                 0, 0,
4946                 MOD_SEL0_30_29
4947                 MOD_SEL0_28
4948                 MOD_SEL0_27_26
4949                 MOD_SEL0_25
4950                 MOD_SEL0_24
4951                 MOD_SEL0_23
4952                 MOD_SEL0_22
4953                 MOD_SEL0_21_20
4954                 MOD_SEL0_19_18_17
4955                 MOD_SEL0_16
4956                 MOD_SEL0_15
4957                 MOD_SEL0_14
4958                 MOD_SEL0_13_12
4959                 MOD_SEL0_11_10
4960                 MOD_SEL0_9
4961                 MOD_SEL0_8
4962                 MOD_SEL0_7
4963                 MOD_SEL0_6_5
4964                 MOD_SEL0_4
4965                 MOD_SEL0_3
4966                 MOD_SEL0_2
4967                 MOD_SEL0_1_0 ))
4968         },
4969         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4970                              GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
4971                                    2, 2, 2, 1, 1, 2, 1, 4),
4972                              GROUP(
4973                 /* RESERVED 31, 30 */
4974                 0, 0, 0, 0,
4975                 MOD_SEL1_29
4976                 MOD_SEL1_28
4977                 /* RESERVED 27 */
4978                 0, 0,
4979                 MOD_SEL1_26
4980                 MOD_SEL1_25
4981                 MOD_SEL1_24_23_22
4982                 MOD_SEL1_21_20_19
4983                 MOD_SEL1_18
4984                 MOD_SEL1_17
4985                 MOD_SEL1_16
4986                 MOD_SEL1_15
4987                 MOD_SEL1_14_13
4988                 MOD_SEL1_12_11
4989                 MOD_SEL1_10_9
4990                 MOD_SEL1_8
4991                 MOD_SEL1_7
4992                 MOD_SEL1_6_5
4993                 MOD_SEL1_4
4994                 /* RESERVED 3, 2, 1, 0  */
4995                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
4996         },
4997         { },
4998 };
4999
5000 enum ioctrl_regs {
5001         POCCTRL0,
5002         TDSELCTRL,
5003 };
5004
5005 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5006         [POCCTRL0] = { 0xe6060380, },
5007         [TDSELCTRL] = { 0xe60603c0, },
5008         { /* sentinel */ },
5009 };
5010
5011 static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5012                                    u32 *pocctrl)
5013 {
5014         int bit = -EINVAL;
5015
5016         *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
5017
5018         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5019                 bit = pin & 0x1f;
5020
5021         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
5022                 bit = (pin & 0x1f) + 19;
5023
5024         return bit;
5025 }
5026
5027 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5028         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5029                  [0] = RCAR_GP_PIN(2, 23),      /* RD# */
5030                  [1] = RCAR_GP_PIN(2, 22),      /* BS# */
5031                  [2] = RCAR_GP_PIN(2, 21),      /* AVB_PHY_INT */
5032                  [3] = PIN_NUMBER('P', 5),      /* AVB_MDC */
5033                  [4] = PIN_NUMBER('P', 4),      /* AVB_MDIO */
5034                  [5] = RCAR_GP_PIN(2, 20),      /* AVB_TXCREFCLK */
5035                  [6] = PIN_NUMBER('N', 6),      /* AVB_TD3 */
5036                  [7] = PIN_NUMBER('N', 5),      /* AVB_TD2 */
5037                  [8] = PIN_NUMBER('N', 3),      /* AVB_TD1 */
5038                  [9] = PIN_NUMBER('N', 2),      /* AVB_TD0 */
5039                 [10] = PIN_NUMBER('N', 1),      /* AVB_TXC */
5040                 [11] = PIN_NUMBER('P', 3),      /* AVB_TX_CTL */
5041                 [12] = RCAR_GP_PIN(2, 19),      /* AVB_RD3 */
5042                 [13] = RCAR_GP_PIN(2, 18),      /* AVB_RD2 */
5043                 [14] = RCAR_GP_PIN(2, 17),      /* AVB_RD1 */
5044                 [15] = RCAR_GP_PIN(2, 16),      /* AVB_RD0 */
5045                 [16] = RCAR_GP_PIN(2, 15),      /* AVB_RXC */
5046                 [17] = RCAR_GP_PIN(2, 14),      /* AVB_RX_CTL */
5047                 [18] = RCAR_GP_PIN(2, 13),      /* RPC_RESET# */
5048                 [19] = RCAR_GP_PIN(2, 12),      /* RPC_INT# */
5049                 [20] = RCAR_GP_PIN(2, 11),      /* QSPI1_SSL */
5050                 [21] = RCAR_GP_PIN(2, 10),      /* QSPI1_IO3 */
5051                 [22] = RCAR_GP_PIN(2,  9),      /* QSPI1_IO2 */
5052                 [23] = RCAR_GP_PIN(2,  8),      /* QSPI1_MISO/IO1 */
5053                 [24] = RCAR_GP_PIN(2,  7),      /* QSPI1_MOSI/IO0 */
5054                 [25] = RCAR_GP_PIN(2,  6),      /* QSPI1_SPCLK */
5055                 [26] = RCAR_GP_PIN(2,  5),      /* QSPI0_SSL */
5056                 [27] = RCAR_GP_PIN(2,  4),      /* QSPI0_IO3 */
5057                 [28] = RCAR_GP_PIN(2,  3),      /* QSPI0_IO2 */
5058                 [29] = RCAR_GP_PIN(2,  2),      /* QSPI0_MISO/IO1 */
5059                 [30] = RCAR_GP_PIN(2,  1),      /* QSPI0_MOSI/IO0 */
5060                 [31] = RCAR_GP_PIN(2,  0),      /* QSPI0_SPCLK */
5061         } },
5062         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5063                  [0] = RCAR_GP_PIN(0,  4),      /* D4 */
5064                  [1] = RCAR_GP_PIN(0,  3),      /* D3 */
5065                  [2] = RCAR_GP_PIN(0,  2),      /* D2 */
5066                  [3] = RCAR_GP_PIN(0,  1),      /* D1 */
5067                  [4] = RCAR_GP_PIN(0,  0),      /* D0 */
5068                  [5] = RCAR_GP_PIN(1, 22),      /* WE0# */
5069                  [6] = RCAR_GP_PIN(1, 21),      /* CS0# */
5070                  [7] = RCAR_GP_PIN(1, 20),      /* CLKOUT */
5071                  [8] = RCAR_GP_PIN(1, 19),      /* A19 */
5072                  [9] = RCAR_GP_PIN(1, 18),      /* A18 */
5073                 [10] = RCAR_GP_PIN(1, 17),      /* A17 */
5074                 [11] = RCAR_GP_PIN(1, 16),      /* A16 */
5075                 [12] = RCAR_GP_PIN(1, 15),      /* A15 */
5076                 [13] = RCAR_GP_PIN(1, 14),      /* A14 */
5077                 [14] = RCAR_GP_PIN(1, 13),      /* A13 */
5078                 [15] = RCAR_GP_PIN(1, 12),      /* A12 */
5079                 [16] = RCAR_GP_PIN(1, 11),      /* A11 */
5080                 [17] = RCAR_GP_PIN(1, 10),      /* A10 */
5081                 [18] = RCAR_GP_PIN(1,  9),      /* A9 */
5082                 [19] = RCAR_GP_PIN(1,  8),      /* A8 */
5083                 [20] = RCAR_GP_PIN(1,  7),      /* A7 */
5084                 [21] = RCAR_GP_PIN(1,  6),      /* A6 */
5085                 [22] = RCAR_GP_PIN(1,  5),      /* A5 */
5086                 [23] = RCAR_GP_PIN(1,  4),      /* A4 */
5087                 [24] = RCAR_GP_PIN(1,  3),      /* A3 */
5088                 [25] = RCAR_GP_PIN(1,  2),      /* A2 */
5089                 [26] = RCAR_GP_PIN(1,  1),      /* A1 */
5090                 [27] = RCAR_GP_PIN(1,  0),      /* A0 */
5091                 [28] = PIN_NONE,
5092                 [29] = PIN_NONE,
5093                 [30] = RCAR_GP_PIN(2, 25),      /* PUEN_EX_WAIT0 */
5094                 [31] = RCAR_GP_PIN(2, 24),      /* PUEN_RD/WR# */
5095         } },
5096         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5097                  [0] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
5098                  [1] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
5099                  [2] = PIN_NUMBER('H', 1),      /* ASEBRK */
5100                  [3] = PIN_NONE,
5101                  [4] = PIN_NUMBER('G', 2),      /* TDI */
5102                  [5] = PIN_NUMBER('F', 3),      /* TMS */
5103                  [6] = PIN_NUMBER('F', 4),      /* TCK */
5104                  [7] = PIN_NUMBER('F', 1),      /* TRST# */
5105                  [8] = PIN_NONE,
5106                  [9] = PIN_NONE,
5107                 [10] = PIN_NONE,
5108                 [11] = PIN_NONE,
5109                 [12] = PIN_NONE,
5110                 [13] = PIN_NONE,
5111                 [14] = PIN_NONE,
5112                 [15] = PIN_NUMBER('G', 3),      /* FSCLKST# */
5113                 [16] = RCAR_GP_PIN(0, 17),      /* SDA4 */
5114                 [17] = RCAR_GP_PIN(0, 16),      /* SCL4 */
5115                 [18] = PIN_NONE,
5116                 [19] = PIN_NONE,
5117                 [20] = PIN_A_NUMBER('D', 3),    /* PRESETOUT# */
5118                 [21] = RCAR_GP_PIN(0, 15),      /* D15 */
5119                 [22] = RCAR_GP_PIN(0, 14),      /* D14 */
5120                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
5121                 [24] = RCAR_GP_PIN(0, 12),      /* D12 */
5122                 [25] = RCAR_GP_PIN(0, 11),      /* D11 */
5123                 [26] = RCAR_GP_PIN(0, 10),      /* D10 */
5124                 [27] = RCAR_GP_PIN(0,  9),      /* D9 */
5125                 [28] = RCAR_GP_PIN(0,  8),      /* D8 */
5126                 [29] = RCAR_GP_PIN(0,  7),      /* D7 */
5127                 [30] = RCAR_GP_PIN(0,  6),      /* D6 */
5128                 [31] = RCAR_GP_PIN(0,  5),      /* D5 */
5129         } },
5130         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5131                  [0] = RCAR_GP_PIN(5,  0),      /* SCK0_A */
5132                  [1] = RCAR_GP_PIN(5,  4),      /* RTS0#_A */
5133                  [2] = RCAR_GP_PIN(5,  3),      /* CTS0#_A */
5134                  [3] = RCAR_GP_PIN(5,  2),      /* TX0_A */
5135                  [4] = RCAR_GP_PIN(5,  1),      /* RX0_A */
5136                  [5] = PIN_NONE,
5137                  [6] = PIN_NONE,
5138                  [7] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
5139                  [8] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
5140                  [9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
5141                 [10] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
5142                 [11] = RCAR_GP_PIN(4, 10),      /* SD3_DS */
5143                 [12] = RCAR_GP_PIN(4,  9),      /* SD3_DAT7 */
5144                 [13] = RCAR_GP_PIN(4,  8),      /* SD3_DAT6 */
5145                 [14] = RCAR_GP_PIN(4,  7),      /* SD3_DAT5 */
5146                 [15] = RCAR_GP_PIN(4,  6),      /* SD3_DAT4 */
5147                 [16] = RCAR_GP_PIN(4,  5),      /* SD3_DAT3 */
5148                 [17] = RCAR_GP_PIN(4,  4),      /* SD3_DAT2 */
5149                 [18] = RCAR_GP_PIN(4,  3),      /* SD3_DAT1 */
5150                 [19] = RCAR_GP_PIN(4,  2),      /* SD3_DAT0 */
5151                 [20] = RCAR_GP_PIN(4,  1),      /* SD3_CMD */
5152                 [21] = RCAR_GP_PIN(4,  0),      /* SD3_CLK */
5153                 [22] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
5154                 [23] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
5155                 [24] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
5156                 [25] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
5157                 [26] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
5158                 [27] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
5159                 [28] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
5160                 [29] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
5161                 [30] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
5162                 [31] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
5163         } },
5164         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5165                  [0] = RCAR_GP_PIN(6,  8),      /* AUDIO_CLKA */
5166                  [1] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
5167                  [2] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
5168                  [3] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
5169                  [4] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
5170                  [5] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
5171                  [6] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
5172                  [7] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
5173                  [8] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
5174                  [9] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
5175                 [10] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
5176                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2 */
5177                 [12] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1 */
5178                 [13] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
5179                 [14] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
5180                 [15] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
5181                 [16] = PIN_NUMBER('T', 21),     /* MLB_REF */
5182                 [17] = RCAR_GP_PIN(5, 19),      /* MLB_DAT */
5183                 [18] = RCAR_GP_PIN(5, 18),      /* MLB_SIG */
5184                 [19] = RCAR_GP_PIN(5, 17),      /* MLB_CLK */
5185                 [20] = RCAR_GP_PIN(5, 16),      /* SSI_SDATA9 */
5186                 [21] = RCAR_GP_PIN(5, 15),      /* MSIOF0_SS2 */
5187                 [22] = RCAR_GP_PIN(5, 14),      /* MSIOF0_SS1 */
5188                 [23] = RCAR_GP_PIN(5, 13),      /* MSIOF0_SYNC */
5189                 [24] = RCAR_GP_PIN(5, 12),      /* MSIOF0_TXD */
5190                 [25] = RCAR_GP_PIN(5, 11),      /* MSIOF0_RXD */
5191                 [26] = RCAR_GP_PIN(5, 10),      /* MSIOF0_SCK */
5192                 [27] = RCAR_GP_PIN(5,  9),      /* RX2_A */
5193                 [28] = RCAR_GP_PIN(5,  8),      /* TX2_A */
5194                 [29] = RCAR_GP_PIN(5,  7),      /* SCK2_A */
5195                 [30] = RCAR_GP_PIN(5,  6),      /* TX1 */
5196                 [31] = RCAR_GP_PIN(5,  5),      /* RX1 */
5197         } },
5198         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5199                  [0] = PIN_NONE,
5200                  [1] = PIN_NONE,
5201                  [2] = PIN_NONE,
5202                  [3] = PIN_NONE,
5203                  [4] = PIN_NONE,
5204                  [5] = PIN_NONE,
5205                  [6] = PIN_NONE,
5206                  [7] = PIN_NONE,
5207                  [8] = PIN_NONE,
5208                  [9] = PIN_NONE,
5209                 [10] = PIN_NONE,
5210                 [11] = PIN_NONE,
5211                 [12] = PIN_NONE,
5212                 [13] = PIN_NONE,
5213                 [14] = PIN_NONE,
5214                 [15] = PIN_NONE,
5215                 [16] = PIN_NONE,
5216                 [17] = PIN_NONE,
5217                 [18] = PIN_NONE,
5218                 [19] = PIN_NONE,
5219                 [20] = PIN_NONE,
5220                 [21] = PIN_NONE,
5221                 [22] = PIN_NONE,
5222                 [23] = PIN_NONE,
5223                 [24] = PIN_NONE,
5224                 [25] = PIN_NONE,
5225                 [26] = PIN_NONE,
5226                 [27] = PIN_NONE,
5227                 [28] = PIN_NONE,
5228                 [29] = PIN_NONE,
5229                 [30] = RCAR_GP_PIN(6,  9),      /* PUEN_USB30_OVC */
5230                 [31] = RCAR_GP_PIN(6, 17),      /* PUEN_USB30_PWEN */
5231         } },
5232         { /* sentinel */ },
5233 };
5234
5235 static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
5236                                              unsigned int pin)
5237 {
5238         const struct pinmux_bias_reg *reg;
5239         unsigned int bit;
5240
5241         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5242         if (!reg)
5243                 return PIN_CONFIG_BIAS_DISABLE;
5244
5245         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5246                 return PIN_CONFIG_BIAS_DISABLE;
5247         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5248                 return PIN_CONFIG_BIAS_PULL_UP;
5249         else
5250                 return PIN_CONFIG_BIAS_PULL_DOWN;
5251 }
5252
5253 static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5254                                      unsigned int bias)
5255 {
5256         const struct pinmux_bias_reg *reg;
5257         u32 enable, updown;
5258         unsigned int bit;
5259
5260         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5261         if (!reg)
5262                 return;
5263
5264         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5265         if (bias != PIN_CONFIG_BIAS_DISABLE)
5266                 enable |= BIT(bit);
5267
5268         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5269         if (bias == PIN_CONFIG_BIAS_PULL_UP)
5270                 updown |= BIT(bit);
5271
5272         sh_pfc_write(pfc, reg->pud, updown);
5273         sh_pfc_write(pfc, reg->puen, enable);
5274 }
5275
5276 static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
5277         .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
5278         .get_bias = r8a77990_pinmux_get_bias,
5279         .set_bias = r8a77990_pinmux_set_bias,
5280 };
5281
5282 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
5283 const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
5284         .name = "r8a774c0_pfc",
5285         .ops = &r8a77990_pinmux_ops,
5286         .unlock_reg = 0xe6060000, /* PMMR */
5287
5288         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5289
5290         .pins = pinmux_pins,
5291         .nr_pins = ARRAY_SIZE(pinmux_pins),
5292         .groups = pinmux_groups.common,
5293         .nr_groups = ARRAY_SIZE(pinmux_groups.common),
5294         .functions = pinmux_functions.common,
5295         .nr_functions = ARRAY_SIZE(pinmux_functions.common),
5296
5297         .cfg_regs = pinmux_config_regs,
5298         .bias_regs = pinmux_bias_regs,
5299         .ioctrl_regs = pinmux_ioctrl_regs,
5300
5301         .pinmux_data = pinmux_data,
5302         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5303 };
5304 #endif
5305
5306 #ifdef CONFIG_PINCTRL_PFC_R8A77990
5307 const struct sh_pfc_soc_info r8a77990_pinmux_info = {
5308         .name = "r8a77990_pfc",
5309         .ops = &r8a77990_pinmux_ops,
5310         .unlock_reg = 0xe6060000, /* PMMR */
5311
5312         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5313
5314         .pins = pinmux_pins,
5315         .nr_pins = ARRAY_SIZE(pinmux_pins),
5316         .groups = pinmux_groups.common,
5317         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
5318                 ARRAY_SIZE(pinmux_groups.automotive),
5319         .functions = pinmux_functions.common,
5320         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
5321                 ARRAY_SIZE(pinmux_functions.automotive),
5322
5323         .cfg_regs = pinmux_config_regs,
5324         .bias_regs = pinmux_bias_regs,
5325         .ioctrl_regs = pinmux_ioctrl_regs,
5326
5327         .pinmux_data = pinmux_data,
5328         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5329 };
5330 #endif