1 // SPDX-License-Identifier: GPL-2.0
3 * R8A77980 processor support - PFC hardware block.
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
10 * R-Car Gen3 processor support - PFC hardware block.
12 * Copyright (C) 2015 Renesas Electronics Corporation
18 #include <dm/pinctrl.h>
19 #include <linux/kernel.h>
23 #define CPU_ALL_PORT(fn, sfx) \
24 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_28(1, fn, sfx), \
26 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_25(4, fn, sfx), \
29 PORT_GP_15(5, fn, sfx)
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
37 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
38 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
39 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
40 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
41 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
42 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
43 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
44 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
45 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
46 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
47 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
48 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
49 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
50 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
51 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
52 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
53 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
54 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
55 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
56 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
57 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
58 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
61 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
62 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
63 #define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
64 #define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
65 #define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
66 #define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
67 #define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
68 #define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
69 #define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
70 #define GPSR1_18 FM(AVB_LINK)
71 #define GPSR1_17 FM(AVB_PHY_INT)
72 #define GPSR1_16 FM(AVB_MAGIC)
73 #define GPSR1_15 FM(AVB_MDC)
74 #define GPSR1_14 FM(AVB_MDIO)
75 #define GPSR1_13 FM(AVB_TXCREFCLK)
76 #define GPSR1_12 FM(AVB_TD3)
77 #define GPSR1_11 FM(AVB_TD2)
78 #define GPSR1_10 FM(AVB_TD1)
79 #define GPSR1_9 FM(AVB_TD0)
80 #define GPSR1_8 FM(AVB_TXC)
81 #define GPSR1_7 FM(AVB_TX_CTL)
82 #define GPSR1_6 FM(AVB_RD3)
83 #define GPSR1_5 FM(AVB_RD2)
84 #define GPSR1_4 FM(AVB_RD1)
85 #define GPSR1_3 FM(AVB_RD0)
86 #define GPSR1_2 FM(AVB_RXC)
87 #define GPSR1_1 FM(AVB_RX_CTL)
88 #define GPSR1_0 F_(IRQ0, IP2_27_24)
91 #define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
92 #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
93 #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
94 #define GPSR2_26 F_(SDA3, IP10_7_4)
95 #define GPSR2_25 F_(SCL3, IP10_3_0)
96 #define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
97 #define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
98 #define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
99 #define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
100 #define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
101 #define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
102 #define GPSR2_18 F_(IRQ5, IP9_7_4)
103 #define GPSR2_17 F_(IRQ4, IP9_3_0)
104 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
105 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
106 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
107 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
108 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
109 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
110 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
111 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
112 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
113 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
114 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
115 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
116 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
117 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
118 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
119 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
120 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
123 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
124 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
125 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
126 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
127 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
128 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
129 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
130 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
131 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
132 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
133 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
134 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
135 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
136 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
137 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
138 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
139 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
142 #define GPSR4_24 FM(GETHER_LINK_A)
143 #define GPSR4_23 FM(GETHER_PHY_INT_A)
144 #define GPSR4_22 FM(GETHER_MAGIC)
145 #define GPSR4_21 FM(GETHER_MDC_A)
146 #define GPSR4_20 FM(GETHER_MDIO_A)
147 #define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
148 #define GPSR4_18 FM(GETHER_TXCREFCLK)
149 #define GPSR4_17 FM(GETHER_TD3)
150 #define GPSR4_16 FM(GETHER_TD2)
151 #define GPSR4_15 FM(GETHER_TD1)
152 #define GPSR4_14 FM(GETHER_TD0)
153 #define GPSR4_13 FM(GETHER_TXC)
154 #define GPSR4_12 FM(GETHER_TX_CTL)
155 #define GPSR4_11 FM(GETHER_RD3)
156 #define GPSR4_10 FM(GETHER_RD2)
157 #define GPSR4_9 FM(GETHER_RD1)
158 #define GPSR4_8 FM(GETHER_RD0)
159 #define GPSR4_7 FM(GETHER_RXC)
160 #define GPSR4_6 FM(GETHER_RX_CTL)
161 #define GPSR4_5 F_(SDA2, IP7_27_24)
162 #define GPSR4_4 F_(SCL2, IP7_23_20)
163 #define GPSR4_3 F_(SDA1, IP7_19_16)
164 #define GPSR4_2 F_(SCL1, IP7_15_12)
165 #define GPSR4_1 F_(SDA0, IP7_11_8)
166 #define GPSR4_0 F_(SCL0, IP7_7_4)
169 #define GPSR5_14 FM(RPC_INT_N)
170 #define GPSR5_13 FM(RPC_WP_N)
171 #define GPSR5_12 FM(RPC_RESET_N)
172 #define GPSR5_11 FM(QSPI1_SSL)
173 #define GPSR5_10 FM(QSPI1_IO3)
174 #define GPSR5_9 FM(QSPI1_IO2)
175 #define GPSR5_8 FM(QSPI1_MISO_IO1)
176 #define GPSR5_7 FM(QSPI1_MOSI_IO0)
177 #define GPSR5_6 FM(QSPI1_SPCLK)
178 #define GPSR5_5 FM(QSPI0_SSL)
179 #define GPSR5_4 FM(QSPI0_IO3)
180 #define GPSR5_3 FM(QSPI0_IO2)
181 #define GPSR5_2 FM(QSPI0_MISO_IO1)
182 #define GPSR5_1 FM(QSPI0_MOSI_IO0)
183 #define GPSR5_0 FM(QSPI0_SPCLK)
186 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
187 #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188 #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189 #define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define PINMUX_GPSR \
283 GPSR1_24 GPSR2_24 GPSR4_24 \
284 GPSR1_23 GPSR2_23 GPSR4_23 \
285 GPSR1_22 GPSR2_22 GPSR4_22 \
286 GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
287 GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
288 GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
289 GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
290 GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
291 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
292 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
293 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
294 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
295 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
296 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
297 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
298 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
299 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
300 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
301 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
302 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
303 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
304 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
305 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
306 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
307 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
309 #define PINMUX_IPSR \
311 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
312 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
313 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
314 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
315 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
316 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
317 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
318 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
320 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
321 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
322 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
323 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
324 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
325 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
326 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
327 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
329 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
330 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
331 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
332 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
333 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
334 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \
335 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \
336 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28
338 /* MOD_SEL0 */ /* 0 */ /* 1 */
339 #define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
340 #define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
341 #define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
342 #define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
343 #define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
344 #define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
345 #define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
346 #define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
347 #define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
348 #define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
349 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
351 #define PINMUX_MOD_SELS \
373 #define FM(x) FN_##x,
374 PINMUX_FUNCTION_BEGIN,
384 #define FM(x) x##_MARK,
394 static const u16 pinmux_data[] = {
395 PINMUX_DATA_GP_ALL(),
397 PINMUX_SINGLE(AVB_RX_CTL),
398 PINMUX_SINGLE(AVB_RXC),
399 PINMUX_SINGLE(AVB_RD0),
400 PINMUX_SINGLE(AVB_RD1),
401 PINMUX_SINGLE(AVB_RD2),
402 PINMUX_SINGLE(AVB_RD3),
403 PINMUX_SINGLE(AVB_TX_CTL),
404 PINMUX_SINGLE(AVB_TXC),
405 PINMUX_SINGLE(AVB_TD0),
406 PINMUX_SINGLE(AVB_TD1),
407 PINMUX_SINGLE(AVB_TD2),
408 PINMUX_SINGLE(AVB_TD3),
409 PINMUX_SINGLE(AVB_TXCREFCLK),
410 PINMUX_SINGLE(AVB_MDIO),
411 PINMUX_SINGLE(AVB_MDC),
412 PINMUX_SINGLE(AVB_MAGIC),
413 PINMUX_SINGLE(AVB_PHY_INT),
414 PINMUX_SINGLE(AVB_LINK),
416 PINMUX_SINGLE(GETHER_RX_CTL),
417 PINMUX_SINGLE(GETHER_RXC),
418 PINMUX_SINGLE(GETHER_RD0),
419 PINMUX_SINGLE(GETHER_RD1),
420 PINMUX_SINGLE(GETHER_RD2),
421 PINMUX_SINGLE(GETHER_RD3),
422 PINMUX_SINGLE(GETHER_TX_CTL),
423 PINMUX_SINGLE(GETHER_TXC),
424 PINMUX_SINGLE(GETHER_TD0),
425 PINMUX_SINGLE(GETHER_TD1),
426 PINMUX_SINGLE(GETHER_TD2),
427 PINMUX_SINGLE(GETHER_TD3),
428 PINMUX_SINGLE(GETHER_TXCREFCLK),
429 PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
430 PINMUX_SINGLE(GETHER_MDIO_A),
431 PINMUX_SINGLE(GETHER_MDC_A),
432 PINMUX_SINGLE(GETHER_MAGIC),
433 PINMUX_SINGLE(GETHER_PHY_INT_A),
434 PINMUX_SINGLE(GETHER_LINK_A),
436 PINMUX_SINGLE(QSPI0_SPCLK),
437 PINMUX_SINGLE(QSPI0_MOSI_IO0),
438 PINMUX_SINGLE(QSPI0_MISO_IO1),
439 PINMUX_SINGLE(QSPI0_IO2),
440 PINMUX_SINGLE(QSPI0_IO3),
441 PINMUX_SINGLE(QSPI0_SSL),
442 PINMUX_SINGLE(QSPI1_SPCLK),
443 PINMUX_SINGLE(QSPI1_MOSI_IO0),
444 PINMUX_SINGLE(QSPI1_MISO_IO1),
445 PINMUX_SINGLE(QSPI1_IO2),
446 PINMUX_SINGLE(QSPI1_IO3),
447 PINMUX_SINGLE(QSPI1_SSL),
448 PINMUX_SINGLE(RPC_RESET_N),
449 PINMUX_SINGLE(RPC_WP_N),
450 PINMUX_SINGLE(RPC_INT_N),
453 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
454 PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
455 PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
456 PINMUX_IPSR_GPSR(IP0_3_0, A0),
458 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
459 PINMUX_IPSR_GPSR(IP0_7_4, RX4),
460 PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
461 PINMUX_IPSR_GPSR(IP0_7_4, A1),
463 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
464 PINMUX_IPSR_GPSR(IP0_11_8, TX4),
465 PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
466 PINMUX_IPSR_GPSR(IP0_11_8, A2),
468 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
469 PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
470 PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
471 PINMUX_IPSR_GPSR(IP0_15_12, A3),
473 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
474 PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
475 PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
476 PINMUX_IPSR_GPSR(IP0_19_16, A4),
478 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
479 PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
480 PINMUX_IPSR_GPSR(IP0_23_20, A5),
482 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
483 PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
484 PINMUX_IPSR_GPSR(IP0_27_24, A6),
486 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
487 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
488 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
489 PINMUX_IPSR_GPSR(IP0_31_28, A7),
490 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
493 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
494 PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
495 PINMUX_IPSR_GPSR(IP1_3_0, A8),
497 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
498 PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
499 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
500 PINMUX_IPSR_GPSR(IP1_7_4, A9),
502 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
503 PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
504 PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
505 PINMUX_IPSR_GPSR(IP1_11_8, A10),
507 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
508 PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
509 PINMUX_IPSR_GPSR(IP1_15_12, A11),
511 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
512 PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
513 PINMUX_IPSR_GPSR(IP1_19_16, A12),
514 PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
516 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
517 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
518 PINMUX_IPSR_GPSR(IP1_23_20, A13),
519 PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
521 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
522 PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
523 PINMUX_IPSR_GPSR(IP1_27_24, A14),
524 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
526 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
527 PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
528 PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
529 PINMUX_IPSR_GPSR(IP1_31_28, A15),
532 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
533 PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
534 PINMUX_IPSR_GPSR(IP2_3_0, A16),
536 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
537 PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
538 PINMUX_IPSR_GPSR(IP2_7_4, A17),
540 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
541 PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
542 PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
543 PINMUX_IPSR_GPSR(IP2_11_8, A18),
545 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
546 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
547 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
548 PINMUX_IPSR_GPSR(IP2_15_12, A19),
549 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
551 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
552 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
553 PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
555 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
556 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
558 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
560 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
561 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
562 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
563 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
566 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
567 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
568 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
569 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
570 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
572 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
573 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
574 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
575 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
577 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
578 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
579 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
580 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
582 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
583 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
584 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
585 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
587 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
588 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
589 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
590 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
592 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
593 PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
595 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
596 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
598 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
599 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
600 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
603 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
604 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
605 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
607 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
608 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
609 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
611 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
612 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
613 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
615 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
616 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
618 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
619 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
620 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
622 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
623 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
624 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
626 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
627 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
628 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
630 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
631 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
632 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
633 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
636 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
637 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
638 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
640 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
641 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
642 PINMUX_IPSR_GPSR(IP5_7_4, D0),
644 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
645 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
646 PINMUX_IPSR_GPSR(IP5_11_8, D1),
648 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
649 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
650 PINMUX_IPSR_GPSR(IP5_15_12, D2),
652 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
653 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
654 PINMUX_IPSR_GPSR(IP5_19_16, D3),
655 PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
657 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
658 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
659 PINMUX_IPSR_GPSR(IP5_23_20, D4),
660 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
662 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
663 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
664 PINMUX_IPSR_GPSR(IP5_27_24, D5),
665 PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
667 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
668 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
669 PINMUX_IPSR_GPSR(IP5_31_28, D6),
670 PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
673 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
674 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
675 PINMUX_IPSR_GPSR(IP6_3_0, D7),
676 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
678 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
679 PINMUX_IPSR_GPSR(IP6_7_4, D8),
680 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
682 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
683 PINMUX_IPSR_GPSR(IP6_11_8, D9),
684 PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
686 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
687 PINMUX_IPSR_GPSR(IP6_15_12, D10),
688 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
690 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
691 PINMUX_IPSR_GPSR(IP6_19_16, D11),
692 PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
694 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
695 PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
696 PINMUX_IPSR_GPSR(IP6_23_20, D12),
697 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
699 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
700 PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
701 PINMUX_IPSR_GPSR(IP6_27_24, D13),
702 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
704 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
705 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
706 PINMUX_IPSR_GPSR(IP6_31_28, D14),
707 PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
710 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
711 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
712 PINMUX_IPSR_GPSR(IP7_3_0, D15),
713 PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
715 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
716 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
718 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
719 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
720 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
721 PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
723 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
724 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
725 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
726 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
727 PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
729 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
730 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
731 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
732 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
733 PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
735 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
736 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
737 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
738 PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
740 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
741 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
742 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
743 PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
745 PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
746 PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
749 PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
750 PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
752 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
753 PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
754 PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
755 PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
757 PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
758 PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
759 PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
760 PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
762 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
763 PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
764 PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
765 PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
766 PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
768 PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
769 PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
770 PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
771 PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
772 PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
774 PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
775 PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
776 PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
777 PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
778 PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
780 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
781 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
783 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
784 PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
787 PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
788 PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
790 PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
791 PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
793 PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
794 PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
795 PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
797 PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
798 PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
799 PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
801 PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
802 PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
803 PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
805 PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
806 PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
807 PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
809 PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
810 PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
811 PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
812 PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
814 PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
815 PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
816 PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
817 PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
820 PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
821 PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
823 PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
824 PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
826 PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
827 PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
829 PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
830 PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
832 PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
835 static const struct sh_pfc_pin pinmux_pins[] = {
836 PINMUX_GPIO_GP_ALL(),
839 /* - AVB -------------------------------------------------------------------- */
840 static const unsigned int avb_link_pins[] = {
844 static const unsigned int avb_link_mux[] = {
847 static const unsigned int avb_magic_pins[] = {
851 static const unsigned int avb_magic_mux[] = {
854 static const unsigned int avb_phy_int_pins[] = {
858 static const unsigned int avb_phy_int_mux[] = {
861 static const unsigned int avb_mdio_pins[] = {
862 /* AVB_MDC, AVB_MDIO */
863 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
865 static const unsigned int avb_mdio_mux[] = {
866 AVB_MDC_MARK, AVB_MDIO_MARK,
868 static const unsigned int avb_rgmii_pins[] = {
870 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
871 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
873 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
874 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
875 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
876 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
877 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
878 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
880 static const unsigned int avb_rgmii_mux[] = {
881 AVB_TX_CTL_MARK, AVB_TXC_MARK,
882 AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
883 AVB_RX_CTL_MARK, AVB_RXC_MARK,
884 AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
886 static const unsigned int avb_txcrefclk_pins[] = {
890 static const unsigned int avb_txcrefclk_mux[] = {
893 static const unsigned int avb_avtp_pps_pins[] = {
897 static const unsigned int avb_avtp_pps_mux[] = {
900 static const unsigned int avb_avtp_capture_pins[] = {
901 /* AVB_AVTP_CAPTURE */
904 static const unsigned int avb_avtp_capture_mux[] = {
905 AVB_AVTP_CAPTURE_MARK,
907 static const unsigned int avb_avtp_match_pins[] = {
911 static const unsigned int avb_avtp_match_mux[] = {
915 /* - CANFD0 ----------------------------------------------------------------- */
916 static const unsigned int canfd0_data_a_pins[] = {
917 /* CANFD0_TX, CANFD0_RX */
918 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
920 static const unsigned int canfd0_data_a_mux[] = {
921 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
923 static const unsigned int canfd0_data_b_pins[] = {
924 /* CANFD0_TX, CANFD0_RX */
925 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
927 static const unsigned int canfd0_data_b_mux[] = {
928 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
931 /* - CANFD1 ----------------------------------------------------------------- */
932 static const unsigned int canfd1_data_pins[] = {
933 /* CANFD1_TX, CANFD1_RX */
934 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
936 static const unsigned int canfd1_data_mux[] = {
937 CANFD1_TX_MARK, CANFD1_RX_MARK,
940 /* - CANFD Clock ------------------------------------------------------------ */
941 static const unsigned int canfd_clk_a_pins[] = {
945 static const unsigned int canfd_clk_a_mux[] = {
948 static const unsigned int canfd_clk_b_pins[] = {
952 static const unsigned int canfd_clk_b_mux[] = {
956 /* - DU --------------------------------------------------------------------- */
957 static const unsigned int du_rgb666_pins[] = {
958 /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
959 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
960 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
961 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
962 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
963 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
964 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
966 static const unsigned int du_rgb666_mux[] = {
967 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
968 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
969 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
970 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
971 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
972 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
974 static const unsigned int du_rgb888_pins[] = {
975 /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
976 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
977 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
978 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
979 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
980 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
981 RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
982 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
983 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
984 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
986 static const unsigned int du_rgb888_mux[] = {
987 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
988 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
989 DU_DR1_MARK, DU_DR0_MARK,
990 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
991 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
992 DU_DG1_MARK, DU_DG0_MARK,
993 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
994 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
995 DU_DB1_MARK, DU_DB0_MARK,
997 static const unsigned int du_clk_out_pins[] = {
1001 static const unsigned int du_clk_out_mux[] = {
1004 static const unsigned int du_sync_pins[] = {
1005 /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
1006 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1008 static const unsigned int du_sync_mux[] = {
1009 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1011 static const unsigned int du_oddf_pins[] = {
1012 /* DU_EXODDF/DU_ODDF/DISP/CDE */
1015 static const unsigned int du_oddf_mux[] = {
1016 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1018 static const unsigned int du_cde_pins[] = {
1022 static const unsigned int du_cde_mux[] = {
1025 static const unsigned int du_disp_pins[] = {
1029 static const unsigned int du_disp_mux[] = {
1033 /* - GETHER ----------------------------------------------------------------- */
1034 static const unsigned int gether_link_a_pins[] = {
1038 static const unsigned int gether_link_a_mux[] = {
1041 static const unsigned int gether_phy_int_a_pins[] = {
1042 /* GETHER_PHY_INT */
1045 static const unsigned int gether_phy_int_a_mux[] = {
1046 GETHER_PHY_INT_A_MARK,
1048 static const unsigned int gether_mdio_a_pins[] = {
1049 /* GETHER_MDC, GETHER_MDIO */
1050 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1052 static const unsigned int gether_mdio_a_mux[] = {
1053 GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
1055 static const unsigned int gether_link_b_pins[] = {
1059 static const unsigned int gether_link_b_mux[] = {
1062 static const unsigned int gether_phy_int_b_pins[] = {
1063 /* GETHER_PHY_INT */
1066 static const unsigned int gether_phy_int_b_mux[] = {
1067 GETHER_PHY_INT_B_MARK,
1069 static const unsigned int gether_mdio_b_mux[] = {
1070 GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
1072 static const unsigned int gether_mdio_b_pins[] = {
1073 /* GETHER_MDC, GETHER_MDIO */
1074 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1076 static const unsigned int gether_magic_pins[] = {
1080 static const unsigned int gether_magic_mux[] = {
1083 static const unsigned int gether_rgmii_pins[] = {
1085 * GETHER_TX_CTL, GETHER_TXC,
1086 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
1087 * GETHER_RX_CTL, GETHER_RXC,
1088 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
1090 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1091 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1092 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1093 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1094 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1095 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1097 static const unsigned int gether_rgmii_mux[] = {
1098 GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
1099 GETHER_TD0_MARK, GETHER_TD1_MARK,
1100 GETHER_TD2_MARK, GETHER_TD3_MARK,
1101 GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
1102 GETHER_RD0_MARK, AVB_RD1_MARK,
1103 GETHER_RD2_MARK, AVB_RD3_MARK,
1105 static const unsigned int gether_txcrefclk_pins[] = {
1106 /* GETHER_TXCREFCLK */
1109 static const unsigned int gether_txcrefclk_mux[] = {
1110 GETHER_TXCREFCLK_MARK,
1112 static const unsigned int gether_txcrefclk_mega_pins[] = {
1113 /* GETHER_TXCREFCLK_MEGA */
1116 static const unsigned int gether_txcrefclk_mega_mux[] = {
1117 GETHER_TXCREFCLK_MEGA_MARK,
1119 static const unsigned int gether_rmii_pins[] = {
1121 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
1122 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
1123 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
1124 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
1126 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1127 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1128 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1129 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
1131 static const unsigned int gether_rmii_mux[] = {
1132 GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
1133 GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
1134 GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
1135 GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
1138 /* - HSCIF0 ----------------------------------------------------------------- */
1139 static const unsigned int hscif0_data_a_pins[] = {
1141 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
1143 static const unsigned int hscif0_data_a_mux[] = {
1144 HRX0_A_MARK, HTX0_A_MARK,
1146 static const unsigned int hscif0_clk_a_pins[] = {
1150 static const unsigned int hscif0_clk_a_mux[] = {
1153 static const unsigned int hscif0_ctrl_a_pins[] = {
1154 /* HRTS0#, HCTS0# */
1155 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1157 static const unsigned int hscif0_ctrl_a_mux[] = {
1158 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1160 static const unsigned int hscif0_data_b_pins[] = {
1162 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1164 static const unsigned int hscif0_data_b_mux[] = {
1165 HRX0_B_MARK, HTX0_B_MARK,
1167 static const unsigned int hscif0_clk_b_pins[] = {
1171 static const unsigned int hscif0_clk_b_mux[] = {
1174 static const unsigned int hscif0_ctrl_b_pins[] = {
1175 /* HRTS0#, HCTS0# */
1176 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1178 static const unsigned int hscif0_ctrl_b_mux[] = {
1179 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1182 /* - HSCIF1 ----------------------------------------------------------------- */
1183 static const unsigned int hscif1_data_pins[] = {
1185 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1187 static const unsigned int hscif1_data_mux[] = {
1188 HRX1_MARK, HTX1_MARK,
1190 static const unsigned int hscif1_clk_pins[] = {
1194 static const unsigned int hscif1_clk_mux[] = {
1197 static const unsigned int hscif1_ctrl_pins[] = {
1198 /* HRTS1#, HCTS1# */
1199 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1201 static const unsigned int hscif1_ctrl_mux[] = {
1202 HRTS1_N_MARK, HCTS1_N_MARK,
1205 /* - HSCIF2 ----------------------------------------------------------------- */
1206 static const unsigned int hscif2_data_pins[] = {
1208 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1210 static const unsigned int hscif2_data_mux[] = {
1211 HRX2_MARK, HTX2_MARK,
1213 static const unsigned int hscif2_clk_pins[] = {
1217 static const unsigned int hscif2_clk_mux[] = {
1220 static const unsigned int hscif2_ctrl_pins[] = {
1221 /* HRTS2#, HCTS2# */
1222 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1224 static const unsigned int hscif2_ctrl_mux[] = {
1225 HRTS2_N_MARK, HCTS2_N_MARK,
1228 /* - HSCIF3 ----------------------------------------------------------------- */
1229 static const unsigned int hscif3_data_pins[] = {
1231 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1233 static const unsigned int hscif3_data_mux[] = {
1234 HRX3_MARK, HTX3_MARK,
1236 static const unsigned int hscif3_clk_pins[] = {
1240 static const unsigned int hscif3_clk_mux[] = {
1243 static const unsigned int hscif3_ctrl_pins[] = {
1244 /* HRTS3#, HCTS3# */
1245 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1247 static const unsigned int hscif3_ctrl_mux[] = {
1248 HRTS3_N_MARK, HCTS3_N_MARK,
1251 /* - I2C0 ------------------------------------------------------------------- */
1252 static const unsigned int i2c0_pins[] = {
1254 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1256 static const unsigned int i2c0_mux[] = {
1257 SDA0_MARK, SCL0_MARK,
1260 /* - I2C1 ------------------------------------------------------------------- */
1261 static const unsigned int i2c1_pins[] = {
1263 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1265 static const unsigned int i2c1_mux[] = {
1266 SDA1_MARK, SCL1_MARK,
1269 /* - I2C2 ------------------------------------------------------------------- */
1270 static const unsigned int i2c2_pins[] = {
1272 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1274 static const unsigned int i2c2_mux[] = {
1275 SDA2_MARK, SCL2_MARK,
1278 /* - I2C3 ------------------------------------------------------------------- */
1279 static const unsigned int i2c3_pins[] = {
1281 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1283 static const unsigned int i2c3_mux[] = {
1284 SDA3_MARK, SCL3_MARK,
1287 /* - I2C4 ------------------------------------------------------------------- */
1288 static const unsigned int i2c4_pins[] = {
1290 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1292 static const unsigned int i2c4_mux[] = {
1293 SDA4_MARK, SCL4_MARK,
1296 /* - I2C5 ------------------------------------------------------------------- */
1297 static const unsigned int i2c5_pins[] = {
1299 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1301 static const unsigned int i2c5_mux[] = {
1302 SDA5_MARK, SCL5_MARK,
1305 /* - INTC-EX ---------------------------------------------------------------- */
1306 static const unsigned int intc_ex_irq0_pins[] = {
1310 static const unsigned int intc_ex_irq0_mux[] = {
1313 static const unsigned int intc_ex_irq1_pins[] = {
1317 static const unsigned int intc_ex_irq1_mux[] = {
1320 static const unsigned int intc_ex_irq2_pins[] = {
1324 static const unsigned int intc_ex_irq2_mux[] = {
1327 static const unsigned int intc_ex_irq3_pins[] = {
1331 static const unsigned int intc_ex_irq3_mux[] = {
1334 static const unsigned int intc_ex_irq4_pins[] = {
1338 static const unsigned int intc_ex_irq4_mux[] = {
1341 static const unsigned int intc_ex_irq5_pins[] = {
1345 static const unsigned int intc_ex_irq5_mux[] = {
1349 /* - MMC -------------------------------------------------------------------- */
1350 static const unsigned int mmc_data1_pins[] = {
1354 static const unsigned int mmc_data1_mux[] = {
1357 static const unsigned int mmc_data4_pins[] = {
1359 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1360 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1362 static const unsigned int mmc_data4_mux[] = {
1363 MMC_D0_MARK, MMC_D1_MARK,
1364 MMC_D2_MARK, MMC_D3_MARK,
1366 static const unsigned int mmc_data8_pins[] = {
1368 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1369 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1370 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1371 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1373 static const unsigned int mmc_data8_mux[] = {
1374 MMC_D0_MARK, MMC_D1_MARK,
1375 MMC_D2_MARK, MMC_D3_MARK,
1376 MMC_D4_MARK, MMC_D5_MARK,
1377 MMC_D6_MARK, MMC_D7_MARK,
1379 static const unsigned int mmc_ctrl_pins[] = {
1380 /* MMC_CLK, MMC_CMD */
1381 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
1383 static const unsigned int mmc_ctrl_mux[] = {
1384 MMC_CLK_MARK, MMC_CMD_MARK,
1386 static const unsigned int mmc_cd_pins[] = {
1390 static const unsigned int mmc_cd_mux[] = {
1393 static const unsigned int mmc_wp_pins[] = {
1397 static const unsigned int mmc_wp_mux[] = {
1400 static const unsigned int mmc_ds_pins[] = {
1404 static const unsigned int mmc_ds_mux[] = {
1408 /* - MSIOF0 ----------------------------------------------------------------- */
1409 static const unsigned int msiof0_clk_pins[] = {
1413 static const unsigned int msiof0_clk_mux[] = {
1416 static const unsigned int msiof0_sync_pins[] = {
1420 static const unsigned int msiof0_sync_mux[] = {
1423 static const unsigned int msiof0_ss1_pins[] = {
1427 static const unsigned int msiof0_ss1_mux[] = {
1430 static const unsigned int msiof0_ss2_pins[] = {
1434 static const unsigned int msiof0_ss2_mux[] = {
1437 static const unsigned int msiof0_txd_pins[] = {
1441 static const unsigned int msiof0_txd_mux[] = {
1444 static const unsigned int msiof0_rxd_pins[] = {
1448 static const unsigned int msiof0_rxd_mux[] = {
1452 /* - MSIOF1 ----------------------------------------------------------------- */
1453 static const unsigned int msiof1_clk_pins[] = {
1457 static const unsigned int msiof1_clk_mux[] = {
1460 static const unsigned int msiof1_sync_pins[] = {
1464 static const unsigned int msiof1_sync_mux[] = {
1467 static const unsigned int msiof1_ss1_pins[] = {
1471 static const unsigned int msiof1_ss1_mux[] = {
1474 static const unsigned int msiof1_ss2_pins[] = {
1478 static const unsigned int msiof1_ss2_mux[] = {
1481 static const unsigned int msiof1_txd_pins[] = {
1485 static const unsigned int msiof1_txd_mux[] = {
1488 static const unsigned int msiof1_rxd_pins[] = {
1492 static const unsigned int msiof1_rxd_mux[] = {
1496 /* - MSIOF2 ----------------------------------------------------------------- */
1497 static const unsigned int msiof2_clk_pins[] = {
1501 static const unsigned int msiof2_clk_mux[] = {
1504 static const unsigned int msiof2_sync_pins[] = {
1508 static const unsigned int msiof2_sync_mux[] = {
1511 static const unsigned int msiof2_ss1_pins[] = {
1515 static const unsigned int msiof2_ss1_mux[] = {
1518 static const unsigned int msiof2_ss2_pins[] = {
1522 static const unsigned int msiof2_ss2_mux[] = {
1525 static const unsigned int msiof2_txd_pins[] = {
1529 static const unsigned int msiof2_txd_mux[] = {
1532 static const unsigned int msiof2_rxd_pins[] = {
1536 static const unsigned int msiof2_rxd_mux[] = {
1540 /* - MSIOF3 ----------------------------------------------------------------- */
1541 static const unsigned int msiof3_clk_pins[] = {
1545 static const unsigned int msiof3_clk_mux[] = {
1548 static const unsigned int msiof3_sync_pins[] = {
1552 static const unsigned int msiof3_sync_mux[] = {
1555 static const unsigned int msiof3_ss1_pins[] = {
1559 static const unsigned int msiof3_ss1_mux[] = {
1562 static const unsigned int msiof3_ss2_pins[] = {
1566 static const unsigned int msiof3_ss2_mux[] = {
1569 static const unsigned int msiof3_txd_pins[] = {
1573 static const unsigned int msiof3_txd_mux[] = {
1576 static const unsigned int msiof3_rxd_pins[] = {
1580 static const unsigned int msiof3_rxd_mux[] = {
1584 /* - PWM0 ------------------------------------------------------------------- */
1585 static const unsigned int pwm0_a_pins[] = {
1589 static const unsigned int pwm0_a_mux[] = {
1592 static const unsigned int pwm0_b_pins[] = {
1596 static const unsigned int pwm0_b_mux[] = {
1600 /* - PWM1 ------------------------------------------------------------------- */
1601 static const unsigned int pwm1_a_pins[] = {
1605 static const unsigned int pwm1_a_mux[] = {
1608 static const unsigned int pwm1_b_pins[] = {
1612 static const unsigned int pwm1_b_mux[] = {
1616 /* - PWM2 ------------------------------------------------------------------- */
1617 static const unsigned int pwm2_a_pins[] = {
1621 static const unsigned int pwm2_a_mux[] = {
1624 static const unsigned int pwm2_b_pins[] = {
1628 static const unsigned int pwm2_b_mux[] = {
1632 /* - PWM3 ------------------------------------------------------------------- */
1633 static const unsigned int pwm3_a_pins[] = {
1637 static const unsigned int pwm3_a_mux[] = {
1640 static const unsigned int pwm3_b_pins[] = {
1644 static const unsigned int pwm3_b_mux[] = {
1648 /* - PWM4 ------------------------------------------------------------------- */
1649 static const unsigned int pwm4_a_pins[] = {
1653 static const unsigned int pwm4_a_mux[] = {
1656 static const unsigned int pwm4_b_pins[] = {
1660 static const unsigned int pwm4_b_mux[] = {
1664 /* - QSPI0 ------------------------------------------------------------------ */
1665 static const unsigned int qspi0_ctrl_pins[] = {
1667 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1669 static const unsigned int qspi0_ctrl_mux[] = {
1670 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1672 static const unsigned int qspi0_data2_pins[] = {
1673 /* MOSI_IO0, MISO_IO1 */
1674 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1676 static const unsigned int qspi0_data2_mux[] = {
1677 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1679 static const unsigned int qspi0_data4_pins[] = {
1680 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1681 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1682 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1684 static const unsigned int qspi0_data4_mux[] = {
1685 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1686 QSPI0_IO2_MARK, QSPI0_IO3_MARK
1689 /* - QSPI1 ------------------------------------------------------------------ */
1690 static const unsigned int qspi1_ctrl_pins[] = {
1692 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1694 static const unsigned int qspi1_ctrl_mux[] = {
1695 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1697 static const unsigned int qspi1_data2_pins[] = {
1698 /* MOSI_IO0, MISO_IO1 */
1699 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1701 static const unsigned int qspi1_data2_mux[] = {
1702 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1704 static const unsigned int qspi1_data4_pins[] = {
1705 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1706 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1707 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1709 static const unsigned int qspi1_data4_mux[] = {
1710 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1711 QSPI1_IO2_MARK, QSPI1_IO3_MARK
1714 /* - SCIF0 ------------------------------------------------------------------ */
1715 static const unsigned int scif0_data_pins[] = {
1717 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1719 static const unsigned int scif0_data_mux[] = {
1722 static const unsigned int scif0_clk_pins[] = {
1726 static const unsigned int scif0_clk_mux[] = {
1729 static const unsigned int scif0_ctrl_pins[] = {
1731 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1733 static const unsigned int scif0_ctrl_mux[] = {
1734 RTS0_N_MARK, CTS0_N_MARK,
1737 /* - SCIF1 ------------------------------------------------------------------ */
1738 static const unsigned int scif1_data_a_pins[] = {
1740 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1742 static const unsigned int scif1_data_a_mux[] = {
1743 RX1_A_MARK, TX1_A_MARK,
1745 static const unsigned int scif1_clk_pins[] = {
1749 static const unsigned int scif1_clk_mux[] = {
1752 static const unsigned int scif1_ctrl_pins[] = {
1754 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1756 static const unsigned int scif1_ctrl_mux[] = {
1757 RTS1_N_MARK, CTS1_N_MARK,
1759 static const unsigned int scif1_data_b_pins[] = {
1761 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1763 static const unsigned int scif1_data_b_mux[] = {
1764 RX1_B_MARK, TX1_B_MARK,
1767 /* - SCIF3 ------------------------------------------------------------------ */
1768 static const unsigned int scif3_data_pins[] = {
1770 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1772 static const unsigned int scif3_data_mux[] = {
1775 static const unsigned int scif3_clk_pins[] = {
1779 static const unsigned int scif3_clk_mux[] = {
1782 static const unsigned int scif3_ctrl_pins[] = {
1784 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1786 static const unsigned int scif3_ctrl_mux[] = {
1787 RTS3_N_MARK, CTS3_N_MARK,
1790 /* - SCIF4 ------------------------------------------------------------------ */
1791 static const unsigned int scif4_data_pins[] = {
1793 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1795 static const unsigned int scif4_data_mux[] = {
1798 static const unsigned int scif4_clk_pins[] = {
1802 static const unsigned int scif4_clk_mux[] = {
1805 static const unsigned int scif4_ctrl_pins[] = {
1807 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1809 static const unsigned int scif4_ctrl_mux[] = {
1810 RTS4_N_MARK, CTS4_N_MARK,
1813 /* - SCIF Clock ------------------------------------------------------------- */
1814 static const unsigned int scif_clk_a_pins[] = {
1818 static const unsigned int scif_clk_a_mux[] = {
1821 static const unsigned int scif_clk_b_pins[] = {
1825 static const unsigned int scif_clk_b_mux[] = {
1829 /* - TMU -------------------------------------------------------------------- */
1830 static const unsigned int tmu_tclk1_a_pins[] = {
1834 static const unsigned int tmu_tclk1_a_mux[] = {
1837 static const unsigned int tmu_tclk1_b_pins[] = {
1841 static const unsigned int tmu_tclk1_b_mux[] = {
1844 static const unsigned int tmu_tclk2_a_pins[] = {
1848 static const unsigned int tmu_tclk2_a_mux[] = {
1851 static const unsigned int tmu_tclk2_b_pins[] = {
1855 static const unsigned int tmu_tclk2_b_mux[] = {
1859 /* - TPU ------------------------------------------------------------------- */
1860 static const unsigned int tpu_to0_pins[] = {
1864 static const unsigned int tpu_to0_mux[] = {
1867 static const unsigned int tpu_to1_pins[] = {
1871 static const unsigned int tpu_to1_mux[] = {
1874 static const unsigned int tpu_to2_pins[] = {
1878 static const unsigned int tpu_to2_mux[] = {
1881 static const unsigned int tpu_to3_pins[] = {
1885 static const unsigned int tpu_to3_mux[] = {
1889 /* - VIN0 ------------------------------------------------------------------- */
1890 static const union vin_data vin0_data_pins = {
1892 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1893 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1894 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1895 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1896 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1897 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1898 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1899 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1900 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1901 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1902 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1903 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1906 static const union vin_data vin0_data_mux = {
1908 VI0_DATA0_MARK, VI0_DATA1_MARK,
1909 VI0_DATA2_MARK, VI0_DATA3_MARK,
1910 VI0_DATA4_MARK, VI0_DATA5_MARK,
1911 VI0_DATA6_MARK, VI0_DATA7_MARK,
1912 VI0_DATA8_MARK, VI0_DATA9_MARK,
1913 VI0_DATA10_MARK, VI0_DATA11_MARK,
1914 VI0_DATA12_MARK, VI0_DATA13_MARK,
1915 VI0_DATA14_MARK, VI0_DATA15_MARK,
1916 VI0_DATA16_MARK, VI0_DATA17_MARK,
1917 VI0_DATA18_MARK, VI0_DATA19_MARK,
1918 VI0_DATA20_MARK, VI0_DATA21_MARK,
1919 VI0_DATA22_MARK, VI0_DATA23_MARK,
1922 static const unsigned int vin0_data18_pins[] = {
1923 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1924 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1925 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1926 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1927 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1928 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1929 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1930 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1931 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1933 static const unsigned int vin0_data18_mux[] = {
1934 VI0_DATA2_MARK, VI0_DATA3_MARK,
1935 VI0_DATA4_MARK, VI0_DATA5_MARK,
1936 VI0_DATA6_MARK, VI0_DATA7_MARK,
1937 VI0_DATA10_MARK, VI0_DATA11_MARK,
1938 VI0_DATA12_MARK, VI0_DATA13_MARK,
1939 VI0_DATA14_MARK, VI0_DATA15_MARK,
1940 VI0_DATA18_MARK, VI0_DATA19_MARK,
1941 VI0_DATA20_MARK, VI0_DATA21_MARK,
1942 VI0_DATA22_MARK, VI0_DATA23_MARK,
1944 static const unsigned int vin0_sync_pins[] = {
1945 /* VI0_VSYNC#, VI0_HSYNC# */
1946 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1948 static const unsigned int vin0_sync_mux[] = {
1949 VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
1951 static const unsigned int vin0_field_pins[] = {
1955 static const unsigned int vin0_field_mux[] = {
1958 static const unsigned int vin0_clkenb_pins[] = {
1962 static const unsigned int vin0_clkenb_mux[] = {
1965 static const unsigned int vin0_clk_pins[] = {
1969 static const unsigned int vin0_clk_mux[] = {
1973 /* - VIN1 ------------------------------------------------------------------- */
1974 static const union vin_data12 vin1_data_pins = {
1976 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1977 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1978 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1979 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1980 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1981 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1984 static const union vin_data12 vin1_data_mux = {
1986 VI1_DATA0_MARK, VI1_DATA1_MARK,
1987 VI1_DATA2_MARK, VI1_DATA3_MARK,
1988 VI1_DATA4_MARK, VI1_DATA5_MARK,
1989 VI1_DATA6_MARK, VI1_DATA7_MARK,
1990 VI1_DATA8_MARK, VI1_DATA9_MARK,
1991 VI1_DATA10_MARK, VI1_DATA11_MARK,
1994 static const unsigned int vin1_sync_pins[] = {
1995 /* VI1_VSYNC#, VI1_HSYNC# */
1996 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1998 static const unsigned int vin1_sync_mux[] = {
1999 VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
2001 static const unsigned int vin1_field_pins[] = {
2005 static const unsigned int vin1_field_mux[] = {
2008 static const unsigned int vin1_clkenb_pins[] = {
2012 static const unsigned int vin1_clkenb_mux[] = {
2015 static const unsigned int vin1_clk_pins[] = {
2019 static const unsigned int vin1_clk_mux[] = {
2023 static const struct sh_pfc_pin_group pinmux_groups[] = {
2024 SH_PFC_PIN_GROUP(avb_link),
2025 SH_PFC_PIN_GROUP(avb_magic),
2026 SH_PFC_PIN_GROUP(avb_phy_int),
2027 SH_PFC_PIN_GROUP(avb_mdio),
2028 SH_PFC_PIN_GROUP(avb_rgmii),
2029 SH_PFC_PIN_GROUP(avb_txcrefclk),
2030 SH_PFC_PIN_GROUP(avb_avtp_pps),
2031 SH_PFC_PIN_GROUP(avb_avtp_capture),
2032 SH_PFC_PIN_GROUP(avb_avtp_match),
2033 SH_PFC_PIN_GROUP(canfd0_data_a),
2034 SH_PFC_PIN_GROUP(canfd0_data_b),
2035 SH_PFC_PIN_GROUP(canfd1_data),
2036 SH_PFC_PIN_GROUP(canfd_clk_a),
2037 SH_PFC_PIN_GROUP(canfd_clk_b),
2038 SH_PFC_PIN_GROUP(du_rgb666),
2039 SH_PFC_PIN_GROUP(du_rgb888),
2040 SH_PFC_PIN_GROUP(du_clk_out),
2041 SH_PFC_PIN_GROUP(du_sync),
2042 SH_PFC_PIN_GROUP(du_oddf),
2043 SH_PFC_PIN_GROUP(du_cde),
2044 SH_PFC_PIN_GROUP(du_disp),
2045 SH_PFC_PIN_GROUP(gether_link_a),
2046 SH_PFC_PIN_GROUP(gether_phy_int_a),
2047 SH_PFC_PIN_GROUP(gether_mdio_a),
2048 SH_PFC_PIN_GROUP(gether_link_b),
2049 SH_PFC_PIN_GROUP(gether_phy_int_b),
2050 SH_PFC_PIN_GROUP(gether_mdio_b),
2051 SH_PFC_PIN_GROUP(gether_magic),
2052 SH_PFC_PIN_GROUP(gether_rgmii),
2053 SH_PFC_PIN_GROUP(gether_txcrefclk),
2054 SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
2055 SH_PFC_PIN_GROUP(gether_rmii),
2056 SH_PFC_PIN_GROUP(hscif0_data_a),
2057 SH_PFC_PIN_GROUP(hscif0_clk_a),
2058 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
2059 SH_PFC_PIN_GROUP(hscif0_data_b),
2060 SH_PFC_PIN_GROUP(hscif0_clk_b),
2061 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2062 SH_PFC_PIN_GROUP(hscif1_data),
2063 SH_PFC_PIN_GROUP(hscif1_clk),
2064 SH_PFC_PIN_GROUP(hscif1_ctrl),
2065 SH_PFC_PIN_GROUP(hscif2_data),
2066 SH_PFC_PIN_GROUP(hscif2_clk),
2067 SH_PFC_PIN_GROUP(hscif2_ctrl),
2068 SH_PFC_PIN_GROUP(hscif3_data),
2069 SH_PFC_PIN_GROUP(hscif3_clk),
2070 SH_PFC_PIN_GROUP(hscif3_ctrl),
2071 SH_PFC_PIN_GROUP(i2c0),
2072 SH_PFC_PIN_GROUP(i2c1),
2073 SH_PFC_PIN_GROUP(i2c2),
2074 SH_PFC_PIN_GROUP(i2c3),
2075 SH_PFC_PIN_GROUP(i2c4),
2076 SH_PFC_PIN_GROUP(i2c5),
2077 SH_PFC_PIN_GROUP(intc_ex_irq0),
2078 SH_PFC_PIN_GROUP(intc_ex_irq1),
2079 SH_PFC_PIN_GROUP(intc_ex_irq2),
2080 SH_PFC_PIN_GROUP(intc_ex_irq3),
2081 SH_PFC_PIN_GROUP(intc_ex_irq4),
2082 SH_PFC_PIN_GROUP(intc_ex_irq5),
2083 SH_PFC_PIN_GROUP(mmc_data1),
2084 SH_PFC_PIN_GROUP(mmc_data4),
2085 SH_PFC_PIN_GROUP(mmc_data8),
2086 SH_PFC_PIN_GROUP(mmc_ctrl),
2087 SH_PFC_PIN_GROUP(mmc_cd),
2088 SH_PFC_PIN_GROUP(mmc_wp),
2089 SH_PFC_PIN_GROUP(mmc_ds),
2090 SH_PFC_PIN_GROUP(msiof0_clk),
2091 SH_PFC_PIN_GROUP(msiof0_sync),
2092 SH_PFC_PIN_GROUP(msiof0_ss1),
2093 SH_PFC_PIN_GROUP(msiof0_ss2),
2094 SH_PFC_PIN_GROUP(msiof0_txd),
2095 SH_PFC_PIN_GROUP(msiof0_rxd),
2096 SH_PFC_PIN_GROUP(msiof1_clk),
2097 SH_PFC_PIN_GROUP(msiof1_sync),
2098 SH_PFC_PIN_GROUP(msiof1_ss1),
2099 SH_PFC_PIN_GROUP(msiof1_ss2),
2100 SH_PFC_PIN_GROUP(msiof1_txd),
2101 SH_PFC_PIN_GROUP(msiof1_rxd),
2102 SH_PFC_PIN_GROUP(msiof2_clk),
2103 SH_PFC_PIN_GROUP(msiof2_sync),
2104 SH_PFC_PIN_GROUP(msiof2_ss1),
2105 SH_PFC_PIN_GROUP(msiof2_ss2),
2106 SH_PFC_PIN_GROUP(msiof2_txd),
2107 SH_PFC_PIN_GROUP(msiof2_rxd),
2108 SH_PFC_PIN_GROUP(msiof3_clk),
2109 SH_PFC_PIN_GROUP(msiof3_sync),
2110 SH_PFC_PIN_GROUP(msiof3_ss1),
2111 SH_PFC_PIN_GROUP(msiof3_ss2),
2112 SH_PFC_PIN_GROUP(msiof3_txd),
2113 SH_PFC_PIN_GROUP(msiof3_rxd),
2114 SH_PFC_PIN_GROUP(pwm0_a),
2115 SH_PFC_PIN_GROUP(pwm0_b),
2116 SH_PFC_PIN_GROUP(pwm1_a),
2117 SH_PFC_PIN_GROUP(pwm1_b),
2118 SH_PFC_PIN_GROUP(pwm2_a),
2119 SH_PFC_PIN_GROUP(pwm2_b),
2120 SH_PFC_PIN_GROUP(pwm3_a),
2121 SH_PFC_PIN_GROUP(pwm3_b),
2122 SH_PFC_PIN_GROUP(pwm4_a),
2123 SH_PFC_PIN_GROUP(pwm4_b),
2124 SH_PFC_PIN_GROUP(qspi0_ctrl),
2125 SH_PFC_PIN_GROUP(qspi0_data2),
2126 SH_PFC_PIN_GROUP(qspi0_data4),
2127 SH_PFC_PIN_GROUP(qspi1_ctrl),
2128 SH_PFC_PIN_GROUP(qspi1_data2),
2129 SH_PFC_PIN_GROUP(qspi1_data4),
2130 SH_PFC_PIN_GROUP(scif0_data),
2131 SH_PFC_PIN_GROUP(scif0_clk),
2132 SH_PFC_PIN_GROUP(scif0_ctrl),
2133 SH_PFC_PIN_GROUP(scif1_data_a),
2134 SH_PFC_PIN_GROUP(scif1_clk),
2135 SH_PFC_PIN_GROUP(scif1_ctrl),
2136 SH_PFC_PIN_GROUP(scif1_data_b),
2137 SH_PFC_PIN_GROUP(scif3_data),
2138 SH_PFC_PIN_GROUP(scif3_clk),
2139 SH_PFC_PIN_GROUP(scif3_ctrl),
2140 SH_PFC_PIN_GROUP(scif4_data),
2141 SH_PFC_PIN_GROUP(scif4_clk),
2142 SH_PFC_PIN_GROUP(scif4_ctrl),
2143 SH_PFC_PIN_GROUP(scif_clk_a),
2144 SH_PFC_PIN_GROUP(scif_clk_b),
2145 SH_PFC_PIN_GROUP(tmu_tclk1_a),
2146 SH_PFC_PIN_GROUP(tmu_tclk1_b),
2147 SH_PFC_PIN_GROUP(tmu_tclk2_a),
2148 SH_PFC_PIN_GROUP(tmu_tclk2_b),
2149 SH_PFC_PIN_GROUP(tpu_to0),
2150 SH_PFC_PIN_GROUP(tpu_to1),
2151 SH_PFC_PIN_GROUP(tpu_to2),
2152 SH_PFC_PIN_GROUP(tpu_to3),
2153 VIN_DATA_PIN_GROUP(vin0_data, 8),
2154 VIN_DATA_PIN_GROUP(vin0_data, 10),
2155 VIN_DATA_PIN_GROUP(vin0_data, 12),
2156 VIN_DATA_PIN_GROUP(vin0_data, 16),
2157 SH_PFC_PIN_GROUP(vin0_data18),
2158 VIN_DATA_PIN_GROUP(vin0_data, 20),
2159 VIN_DATA_PIN_GROUP(vin0_data, 24),
2160 SH_PFC_PIN_GROUP(vin0_sync),
2161 SH_PFC_PIN_GROUP(vin0_field),
2162 SH_PFC_PIN_GROUP(vin0_clkenb),
2163 SH_PFC_PIN_GROUP(vin0_clk),
2164 VIN_DATA_PIN_GROUP(vin1_data, 8),
2165 VIN_DATA_PIN_GROUP(vin1_data, 10),
2166 VIN_DATA_PIN_GROUP(vin1_data, 12),
2167 SH_PFC_PIN_GROUP(vin1_sync),
2168 SH_PFC_PIN_GROUP(vin1_field),
2169 SH_PFC_PIN_GROUP(vin1_clkenb),
2170 SH_PFC_PIN_GROUP(vin1_clk),
2173 static const char * const avb_groups[] = {
2185 static const char * const canfd0_groups[] = {
2190 static const char * const canfd1_groups[] = {
2194 static const char * const canfd_clk_groups[] = {
2199 static const char * const du_groups[] = {
2209 static const char * const gether_groups[] = {
2219 "gether_txcrefclk_mega",
2223 static const char * const hscif0_groups[] = {
2232 static const char * const hscif1_groups[] = {
2238 static const char * const hscif2_groups[] = {
2244 static const char * const hscif3_groups[] = {
2250 static const char * const i2c0_groups[] = {
2254 static const char * const i2c1_groups[] = {
2258 static const char * const i2c2_groups[] = {
2262 static const char * const i2c3_groups[] = {
2266 static const char * const i2c4_groups[] = {
2270 static const char * const i2c5_groups[] = {
2274 static const char * const intc_ex_groups[] = {
2283 static const char * const mmc_groups[] = {
2293 static const char * const msiof0_groups[] = {
2302 static const char * const msiof1_groups[] = {
2311 static const char * const msiof2_groups[] = {
2320 static const char * const msiof3_groups[] = {
2329 static const char * const pwm0_groups[] = {
2334 static const char * const pwm1_groups[] = {
2339 static const char * const pwm2_groups[] = {
2344 static const char * const pwm3_groups[] = {
2349 static const char * const pwm4_groups[] = {
2354 static const char * const qspi0_groups[] = {
2360 static const char * const qspi1_groups[] = {
2366 static const char * const scif0_groups[] = {
2372 static const char * const scif1_groups[] = {
2379 static const char * const scif3_groups[] = {
2385 static const char * const scif4_groups[] = {
2391 static const char * const scif_clk_groups[] = {
2396 static const char * const tmu_groups[] = {
2403 static const char * const tpu_groups[] = {
2410 static const char * const vin0_groups[] = {
2424 static const char * const vin1_groups[] = {
2434 static const struct sh_pfc_function pinmux_functions[] = {
2435 SH_PFC_FUNCTION(avb),
2436 SH_PFC_FUNCTION(canfd0),
2437 SH_PFC_FUNCTION(canfd1),
2438 SH_PFC_FUNCTION(canfd_clk),
2439 SH_PFC_FUNCTION(du),
2440 SH_PFC_FUNCTION(gether),
2441 SH_PFC_FUNCTION(hscif0),
2442 SH_PFC_FUNCTION(hscif1),
2443 SH_PFC_FUNCTION(hscif2),
2444 SH_PFC_FUNCTION(hscif3),
2445 SH_PFC_FUNCTION(i2c0),
2446 SH_PFC_FUNCTION(i2c1),
2447 SH_PFC_FUNCTION(i2c2),
2448 SH_PFC_FUNCTION(i2c3),
2449 SH_PFC_FUNCTION(i2c4),
2450 SH_PFC_FUNCTION(i2c5),
2451 SH_PFC_FUNCTION(intc_ex),
2452 SH_PFC_FUNCTION(mmc),
2453 SH_PFC_FUNCTION(msiof0),
2454 SH_PFC_FUNCTION(msiof1),
2455 SH_PFC_FUNCTION(msiof2),
2456 SH_PFC_FUNCTION(msiof3),
2457 SH_PFC_FUNCTION(pwm0),
2458 SH_PFC_FUNCTION(pwm1),
2459 SH_PFC_FUNCTION(pwm2),
2460 SH_PFC_FUNCTION(pwm3),
2461 SH_PFC_FUNCTION(pwm4),
2462 SH_PFC_FUNCTION(qspi0),
2463 SH_PFC_FUNCTION(qspi1),
2464 SH_PFC_FUNCTION(scif0),
2465 SH_PFC_FUNCTION(scif1),
2466 SH_PFC_FUNCTION(scif3),
2467 SH_PFC_FUNCTION(scif4),
2468 SH_PFC_FUNCTION(scif_clk),
2469 SH_PFC_FUNCTION(tmu),
2470 SH_PFC_FUNCTION(tpu),
2471 SH_PFC_FUNCTION(vin0),
2472 SH_PFC_FUNCTION(vin1),
2475 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2476 #define F_(x, y) FN_##y
2477 #define FM(x) FN_##x
2478 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2489 GP_0_21_FN, GPSR0_21,
2490 GP_0_20_FN, GPSR0_20,
2491 GP_0_19_FN, GPSR0_19,
2492 GP_0_18_FN, GPSR0_18,
2493 GP_0_17_FN, GPSR0_17,
2494 GP_0_16_FN, GPSR0_16,
2495 GP_0_15_FN, GPSR0_15,
2496 GP_0_14_FN, GPSR0_14,
2497 GP_0_13_FN, GPSR0_13,
2498 GP_0_12_FN, GPSR0_12,
2499 GP_0_11_FN, GPSR0_11,
2500 GP_0_10_FN, GPSR0_10,
2510 GP_0_0_FN, GPSR0_0, ))
2512 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2517 GP_1_27_FN, GPSR1_27,
2518 GP_1_26_FN, GPSR1_26,
2519 GP_1_25_FN, GPSR1_25,
2520 GP_1_24_FN, GPSR1_24,
2521 GP_1_23_FN, GPSR1_23,
2522 GP_1_22_FN, GPSR1_22,
2523 GP_1_21_FN, GPSR1_21,
2524 GP_1_20_FN, GPSR1_20,
2525 GP_1_19_FN, GPSR1_19,
2526 GP_1_18_FN, GPSR1_18,
2527 GP_1_17_FN, GPSR1_17,
2528 GP_1_16_FN, GPSR1_16,
2529 GP_1_15_FN, GPSR1_15,
2530 GP_1_14_FN, GPSR1_14,
2531 GP_1_13_FN, GPSR1_13,
2532 GP_1_12_FN, GPSR1_12,
2533 GP_1_11_FN, GPSR1_11,
2534 GP_1_10_FN, GPSR1_10,
2544 GP_1_0_FN, GPSR1_0, ))
2546 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2549 GP_2_29_FN, GPSR2_29,
2550 GP_2_28_FN, GPSR2_28,
2551 GP_2_27_FN, GPSR2_27,
2552 GP_2_26_FN, GPSR2_26,
2553 GP_2_25_FN, GPSR2_25,
2554 GP_2_24_FN, GPSR2_24,
2555 GP_2_23_FN, GPSR2_23,
2556 GP_2_22_FN, GPSR2_22,
2557 GP_2_21_FN, GPSR2_21,
2558 GP_2_20_FN, GPSR2_20,
2559 GP_2_19_FN, GPSR2_19,
2560 GP_2_18_FN, GPSR2_18,
2561 GP_2_17_FN, GPSR2_17,
2562 GP_2_16_FN, GPSR2_16,
2563 GP_2_15_FN, GPSR2_15,
2564 GP_2_14_FN, GPSR2_14,
2565 GP_2_13_FN, GPSR2_13,
2566 GP_2_12_FN, GPSR2_12,
2567 GP_2_11_FN, GPSR2_11,
2568 GP_2_10_FN, GPSR2_10,
2578 GP_2_0_FN, GPSR2_0, ))
2580 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2596 GP_3_16_FN, GPSR3_16,
2597 GP_3_15_FN, GPSR3_15,
2598 GP_3_14_FN, GPSR3_14,
2599 GP_3_13_FN, GPSR3_13,
2600 GP_3_12_FN, GPSR3_12,
2601 GP_3_11_FN, GPSR3_11,
2602 GP_3_10_FN, GPSR3_10,
2612 GP_3_0_FN, GPSR3_0, ))
2614 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2622 GP_4_24_FN, GPSR4_24,
2623 GP_4_23_FN, GPSR4_23,
2624 GP_4_22_FN, GPSR4_22,
2625 GP_4_21_FN, GPSR4_21,
2626 GP_4_20_FN, GPSR4_20,
2627 GP_4_19_FN, GPSR4_19,
2628 GP_4_18_FN, GPSR4_18,
2629 GP_4_17_FN, GPSR4_17,
2630 GP_4_16_FN, GPSR4_16,
2631 GP_4_15_FN, GPSR4_15,
2632 GP_4_14_FN, GPSR4_14,
2633 GP_4_13_FN, GPSR4_13,
2634 GP_4_12_FN, GPSR4_12,
2635 GP_4_11_FN, GPSR4_11,
2636 GP_4_10_FN, GPSR4_10,
2646 GP_4_0_FN, GPSR4_0, ))
2648 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2666 GP_5_14_FN, GPSR5_14,
2667 GP_5_13_FN, GPSR5_13,
2668 GP_5_12_FN, GPSR5_12,
2669 GP_5_11_FN, GPSR5_11,
2670 GP_5_10_FN, GPSR5_10,
2680 GP_5_0_FN, GPSR5_0, ))
2686 #define FM(x) FN_##x,
2687 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2697 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2707 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2717 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2727 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2737 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2747 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2757 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2767 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2777 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2787 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
2801 #define FM(x) FN_##x,
2802 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2803 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
2806 /* RESERVED 31, 30, 29, 28 */
2807 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2808 /* RESERVED 27, 26, 25, 24 */
2809 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2810 /* RESERVED 23, 22, 21, 20 */
2811 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2812 /* RESERVED 19, 18, 17, 16 */
2813 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2814 /* RESERVED 15, 14, 13, 12 */
2815 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2840 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2841 [POCCTRL0] = { 0xe6060380, },
2842 [POCCTRL1] = { 0xe6060384, },
2843 [POCCTRL2] = { 0xe6060388, },
2844 [POCCTRL3] = { 0xe606038c, },
2845 [TDSELCTRL] = { 0xe60603c0, },
2849 static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2852 int bit = pin & 0x1f;
2854 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2855 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2857 else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2860 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2861 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2863 if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
2864 (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
2867 *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
2868 if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
2874 static const struct sh_pfc_soc_operations pinmux_ops = {
2875 .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
2878 const struct sh_pfc_soc_info r8a77980_pinmux_info = {
2879 .name = "r8a77980_pfc",
2881 .unlock_reg = 0xe6060000, /* PMMR */
2883 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2885 .pins = pinmux_pins,
2886 .nr_pins = ARRAY_SIZE(pinmux_pins),
2887 .groups = pinmux_groups,
2888 .nr_groups = ARRAY_SIZE(pinmux_groups),
2889 .functions = pinmux_functions,
2890 .nr_functions = ARRAY_SIZE(pinmux_functions),
2892 .cfg_regs = pinmux_config_regs,
2893 .ioctrl_regs = pinmux_ioctrl_regs,
2895 .pinmux_data = pinmux_data,
2896 .pinmux_data_size = ARRAY_SIZE(pinmux_data),