drivers/pinctrl/renesas/pfc-r8a77970.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A77970 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2016 Renesas Electronics Corp.
   6  * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
   7  *
   8  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
   9  *
  10  * R-Car Gen3 processor support - PFC hardware block.
  11  *
  12  * Copyright (C) 2015  Renesas Electronics Corporation
  13  */
  14
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/kernel.h>
  20
  21 #include "sh_pfc.h"
  22
  23 #define CPU_ALL_PORT(fn, sfx)                                           \
  24         PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  25         PORT_GP_28(1, fn, sfx),                                         \
  26         PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  27         PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  28         PORT_GP_6(4,  fn, sfx),                                         \
  29         PORT_GP_15(5, fn, sfx)
  30 /*
  31  * F_() : just information
  32  * FM() : macro for FN_xxx / xxx_MARK
  33  */
  34
  35 /* GPSR0 */
  36 #define GPSR0_21        F_(DU_EXODDF_DU_ODDF_DISP_CDE,  IP2_23_20)
  37 #define GPSR0_20        F_(DU_EXVSYNC_DU_VSYNC,         IP2_19_16)
  38 #define GPSR0_19        F_(DU_EXHSYNC_DU_HSYNC,         IP2_15_12)
  39 #define GPSR0_18        F_(DU_DOTCLKOUT,                IP2_11_8)
  40 #define GPSR0_17        F_(DU_DB7,                      IP2_7_4)
  41 #define GPSR0_16        F_(DU_DB6,                      IP2_3_0)
  42 #define GPSR0_15        F_(DU_DB5,                      IP1_31_28)
  43 #define GPSR0_14        F_(DU_DB4,                      IP1_27_24)
  44 #define GPSR0_13        F_(DU_DB3,                      IP1_23_20)
  45 #define GPSR0_12        F_(DU_DB2,                      IP1_19_16)
  46 #define GPSR0_11        F_(DU_DG7,                      IP1_15_12)
  47 #define GPSR0_10        F_(DU_DG6,                      IP1_11_8)
  48 #define GPSR0_9         F_(DU_DG5,                      IP1_7_4)
  49 #define GPSR0_8         F_(DU_DG4,                      IP1_3_0)
  50 #define GPSR0_7         F_(DU_DG3,                      IP0_31_28)
  51 #define GPSR0_6         F_(DU_DG2,                      IP0_27_24)
  52 #define GPSR0_5         F_(DU_DR7,                      IP0_23_20)
  53 #define GPSR0_4         F_(DU_DR6,                      IP0_19_16)
  54 #define GPSR0_3         F_(DU_DR5,                      IP0_15_12)
  55 #define GPSR0_2         F_(DU_DR4,                      IP0_11_8)
  56 #define GPSR0_1         F_(DU_DR3,                      IP0_7_4)
  57 #define GPSR0_0         F_(DU_DR2,                      IP0_3_0)
  58
  59 /* GPSR1 */
  60 #define GPSR1_27        F_(DIGRF_CLKOUT,        IP8_27_24)
  61 #define GPSR1_26        F_(DIGRF_CLKIN,         IP8_23_20)
  62 #define GPSR1_25        F_(CANFD_CLK_A,         IP8_19_16)
  63 #define GPSR1_24        F_(CANFD1_RX,           IP8_15_12)
  64 #define GPSR1_23        F_(CANFD1_TX,           IP8_11_8)
  65 #define GPSR1_22        F_(CANFD0_RX_A,         IP8_7_4)
  66 #define GPSR1_21        F_(CANFD0_TX_A,         IP8_3_0)
  67 #define GPSR1_20        F_(AVB0_AVTP_CAPTURE,   IP7_31_28)
  68 #define GPSR1_19        FM(AVB0_AVTP_MATCH)
  69 #define GPSR1_18        FM(AVB0_LINK)
  70 #define GPSR1_17        FM(AVB0_PHY_INT)
  71 #define GPSR1_16        FM(AVB0_MAGIC)
  72 #define GPSR1_15        FM(AVB0_MDC)
  73 #define GPSR1_14        FM(AVB0_MDIO)
  74 #define GPSR1_13        FM(AVB0_TXCREFCLK)
  75 #define GPSR1_12        FM(AVB0_TD3)
  76 #define GPSR1_11        FM(AVB0_TD2)
  77 #define GPSR1_10        FM(AVB0_TD1)
  78 #define GPSR1_9         FM(AVB0_TD0)
  79 #define GPSR1_8         FM(AVB0_TXC)
  80 #define GPSR1_7         FM(AVB0_TX_CTL)
  81 #define GPSR1_6         FM(AVB0_RD3)
  82 #define GPSR1_5         FM(AVB0_RD2)
  83 #define GPSR1_4         FM(AVB0_RD1)
  84 #define GPSR1_3         FM(AVB0_RD0)
  85 #define GPSR1_2         FM(AVB0_RXC)
  86 #define GPSR1_1         FM(AVB0_RX_CTL)
  87 #define GPSR1_0         F_(IRQ0,                IP2_27_24)
  88
  89 /* GPSR2 */
  90 #define GPSR2_16        F_(VI0_FIELD,           IP4_31_28)
  91 #define GPSR2_15        F_(VI0_DATA11,          IP4_27_24)
  92 #define GPSR2_14        F_(VI0_DATA10,          IP4_23_20)
  93 #define GPSR2_13        F_(VI0_DATA9,           IP4_19_16)
  94 #define GPSR2_12        F_(VI0_DATA8,           IP4_15_12)
  95 #define GPSR2_11        F_(VI0_DATA7,           IP4_11_8)
  96 #define GPSR2_10        F_(VI0_DATA6,           IP4_7_4)
  97 #define GPSR2_9         F_(VI0_DATA5,           IP4_3_0)
  98 #define GPSR2_8         F_(VI0_DATA4,           IP3_31_28)
  99 #define GPSR2_7         F_(VI0_DATA3,           IP3_27_24)
 100 #define GPSR2_6         F_(VI0_DATA2,           IP3_23_20)
 101 #define GPSR2_5         F_(VI0_DATA1,           IP3_19_16)
 102 #define GPSR2_4         F_(VI0_DATA0,           IP3_15_12)
 103 #define GPSR2_3         F_(VI0_VSYNC_N,         IP3_11_8)
 104 #define GPSR2_2         F_(VI0_HSYNC_N,         IP3_7_4)
 105 #define GPSR2_1         F_(VI0_CLKENB,          IP3_3_0)
 106 #define GPSR2_0         F_(VI0_CLK,             IP2_31_28)
 107
 108 /* GPSR3 */
 109 #define GPSR3_16        F_(VI1_FIELD,           IP7_3_0)
 110 #define GPSR3_15        F_(VI1_DATA11,          IP6_31_28)
 111 #define GPSR3_14        F_(VI1_DATA10,          IP6_27_24)
 112 #define GPSR3_13        F_(VI1_DATA9,           IP6_23_20)
 113 #define GPSR3_12        F_(VI1_DATA8,           IP6_19_16)
 114 #define GPSR3_11        F_(VI1_DATA7,           IP6_15_12)
 115 #define GPSR3_10        F_(VI1_DATA6,           IP6_11_8)
 116 #define GPSR3_9         F_(VI1_DATA5,           IP6_7_4)
 117 #define GPSR3_8         F_(VI1_DATA4,           IP6_3_0)
 118 #define GPSR3_7         F_(VI1_DATA3,           IP5_31_28)
 119 #define GPSR3_6         F_(VI1_DATA2,           IP5_27_24)
 120 #define GPSR3_5         F_(VI1_DATA1,           IP5_23_20)
 121 #define GPSR3_4         F_(VI1_DATA0,           IP5_19_16)
 122 #define GPSR3_3         F_(VI1_VSYNC_N,         IP5_15_12)
 123 #define GPSR3_2         F_(VI1_HSYNC_N,         IP5_11_8)
 124 #define GPSR3_1         F_(VI1_CLKENB,          IP5_7_4)
 125 #define GPSR3_0         F_(VI1_CLK,             IP5_3_0)
 126
 127 /* GPSR4 */
 128 #define GPSR4_5         F_(SDA2,                IP7_27_24)
 129 #define GPSR4_4         F_(SCL2,                IP7_23_20)
 130 #define GPSR4_3         F_(SDA1,                IP7_19_16)
 131 #define GPSR4_2         F_(SCL1,                IP7_15_12)
 132 #define GPSR4_1         F_(SDA0,                IP7_11_8)
 133 #define GPSR4_0         F_(SCL0,                IP7_7_4)
 134
 135 /* GPSR5 */
 136 #define GPSR5_14        FM(RPC_INT_N)
 137 #define GPSR5_13        FM(RPC_WP_N)
 138 #define GPSR5_12        FM(RPC_RESET_N)
 139 #define GPSR5_11        FM(QSPI1_SSL)
 140 #define GPSR5_10        FM(QSPI1_IO3)
 141 #define GPSR5_9         FM(QSPI1_IO2)
 142 #define GPSR5_8         FM(QSPI1_MISO_IO1)
 143 #define GPSR5_7         FM(QSPI1_MOSI_IO0)
 144 #define GPSR5_6         FM(QSPI1_SPCLK)
 145 #define GPSR5_5         FM(QSPI0_SSL)
 146 #define GPSR5_4         FM(QSPI0_IO3)
 147 #define GPSR5_3         FM(QSPI0_IO2)
 148 #define GPSR5_2         FM(QSPI0_MISO_IO1)
 149 #define GPSR5_1         FM(QSPI0_MOSI_IO0)
 150 #define GPSR5_0         FM(QSPI0_SPCLK)
 151
 152
 153 /* IPSRx */             /* 0 */                         /* 1 */                 /* 2 */         /* 3 */         /* 4 */                 /* 5 */         /* 6 - F */
 154 #define IP0_3_0         FM(DU_DR2)                      FM(HSCK0)               F_(0, 0)        FM(A0)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 155 #define IP0_7_4         FM(DU_DR3)                      FM(HRTS0_N)             F_(0, 0)        FM(A1)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 156 #define IP0_11_8        FM(DU_DR4)                      FM(HCTS0_N)             F_(0, 0)        FM(A2)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 157 #define IP0_15_12       FM(DU_DR5)                      FM(HTX0)                F_(0, 0)        FM(A3)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 158 #define IP0_19_16       FM(DU_DR6)                      FM(MSIOF3_RXD)          F_(0, 0)        FM(A4)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 159 #define IP0_23_20       FM(DU_DR7)                      FM(MSIOF3_TXD)          F_(0, 0)        FM(A5)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 160 #define IP0_27_24       FM(DU_DG2)                      FM(MSIOF3_SS1)          F_(0, 0)        FM(A6)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 161 #define IP0_31_28       FM(DU_DG3)                      FM(MSIOF3_SS2)          F_(0, 0)        FM(A7)          FM(PWMFSW0)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 162 #define IP1_3_0         FM(DU_DG4)                      F_(0, 0)                F_(0, 0)        FM(A8)          FM(FSO_CFE_0_N_A)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 163 #define IP1_7_4         FM(DU_DG5)                      F_(0, 0)                F_(0, 0)        FM(A9)          FM(FSO_CFE_1_N_A)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 164 #define IP1_11_8        FM(DU_DG6)                      F_(0, 0)                F_(0, 0)        FM(A10)         FM(FSO_TOE_N_A)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 165 #define IP1_15_12       FM(DU_DG7)                      F_(0, 0)                F_(0, 0)        FM(A11)         FM(IRQ1)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 166 #define IP1_19_16       FM(DU_DB2)                      F_(0, 0)                F_(0, 0)        FM(A12)         FM(IRQ2)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 167 #define IP1_23_20       FM(DU_DB3)                      F_(0, 0)                F_(0, 0)        FM(A13)         FM(FXR_CLKOUT1)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 168 #define IP1_27_24       FM(DU_DB4)                      F_(0, 0)                F_(0, 0)        FM(A14)         FM(FXR_CLKOUT2)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 169 #define IP1_31_28       FM(DU_DB5)                      F_(0, 0)                F_(0, 0)        FM(A15)         FM(FXR_TXENA_N)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 170 #define IP2_3_0         FM(DU_DB6)                      F_(0, 0)                F_(0, 0)        FM(A16)         FM(FXR_TXENB_N)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 171 #define IP2_7_4         FM(DU_DB7)                      F_(0, 0)                F_(0, 0)        FM(A17)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 172 #define IP2_11_8        FM(DU_DOTCLKOUT)                FM(SCIF_CLK_A)          F_(0, 0)        FM(A18)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 173 #define IP2_15_12       FM(DU_EXHSYNC_DU_HSYNC)         FM(HRX0)                F_(0, 0)        FM(A19)         FM(IRQ3)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 174 #define IP2_19_16       FM(DU_EXVSYNC_DU_VSYNC)         FM(MSIOF3_SCK)          F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 175 #define IP2_23_20       FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(MSIOF3_SYNC)         F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 176 #define IP2_27_24       FM(IRQ0)                        FM(CC5_OSCOUT)          F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 177 #define IP2_31_28       FM(VI0_CLK)                     FM(MSIOF2_SCK)          FM(SCK3)        F_(0, 0)        FM(HSCK3)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 178 #define IP3_3_0         FM(VI0_CLKENB)                  FM(MSIOF2_RXD)          FM(RX3)         FM(RD_WR_N)     FM(HCTS3_N)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 179 #define IP3_7_4         FM(VI0_HSYNC_N)                 FM(MSIOF2_TXD)          FM(TX3)         F_(0, 0)        FM(HRTS3_N)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 180 #define IP3_11_8        FM(VI0_VSYNC_N)                 FM(MSIOF2_SYNC)         FM(CTS3_N)      F_(0, 0)        FM(HTX3)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 181 #define IP3_15_12       FM(VI0_DATA0)                   FM(MSIOF2_SS1)          FM(RTS3_N_TANS) F_(0, 0)        FM(HRX3)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 182 #define IP3_19_16       FM(VI0_DATA1)                   FM(MSIOF2_SS2)          FM(SCK1)        F_(0, 0)        FM(SPEEDIN_A)           F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 183 #define IP3_23_20       FM(VI0_DATA2)                   FM(AVB0_AVTP_PPS)       FM(SDA3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 184 #define IP3_27_24       FM(VI0_DATA3)                   FM(HSCK1)               FM(SCL3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 185 #define IP3_31_28       FM(VI0_DATA4)                   FM(HRTS1_N)             FM(RX1_A)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 186 #define IP4_3_0         FM(VI0_DATA5)                   FM(HCTS1_N)             FM(TX1_A)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 187 #define IP4_7_4         FM(VI0_DATA6)                   FM(HTX1)                FM(CTS1_N)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 188 #define IP4_11_8        FM(VI0_DATA7)                   FM(HRX1)                FM(RTS1_N_TANS) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 189 #define IP4_15_12       FM(VI0_DATA8)                   FM(HSCK2)               FM(PWM0_A)      FM(A22)         F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 190 #define IP4_19_16       FM(VI0_DATA9)                   FM(HCTS2_N)             FM(PWM1_A)      FM(A23)         FM(FSO_CFE_0_N_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 191 #define IP4_23_20       FM(VI0_DATA10)                  FM(HRTS2_N)             FM(PWM2_A)      FM(A24)         FM(FSO_CFE_1_N_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 192 #define IP4_27_24       FM(VI0_DATA11)                  FM(HTX2)                FM(PWM3_A)      FM(A25)         FM(FSO_TOE_N_B)         F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 193 #define IP4_31_28       FM(VI0_FIELD)                   FM(HRX2)                FM(PWM4_A)      FM(CS1_N)       FM(FSCLKST2_N_A)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 194 #define IP5_3_0         FM(VI1_CLK)                     FM(MSIOF1_RXD)          F_(0, 0)        FM(CS0_N)       F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 195 #define IP5_7_4         FM(VI1_CLKENB)                  FM(MSIOF1_TXD)          F_(0, 0)        FM(D0)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 196 #define IP5_11_8        FM(VI1_HSYNC_N)                 FM(MSIOF1_SCK)          F_(0, 0)        FM(D1)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 197 #define IP5_15_12       FM(VI1_VSYNC_N)                 FM(MSIOF1_SYNC)         F_(0, 0)        FM(D2)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 198 #define IP5_19_16       FM(VI1_DATA0)                   FM(MSIOF1_SS1)          F_(0, 0)        FM(D3)          F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 199 #define IP5_23_20       FM(VI1_DATA1)                   FM(MSIOF1_SS2)          F_(0, 0)        FM(D4)          FM(MMC_CMD)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 200 #define IP5_27_24       FM(VI1_DATA2)                   FM(CANFD0_TX_B)         F_(0, 0)        FM(D5)          FM(MMC_D0)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 201 #define IP5_31_28       FM(VI1_DATA3)                   FM(CANFD0_RX_B)         F_(0, 0)        FM(D6)          FM(MMC_D1)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 202 #define IP6_3_0         FM(VI1_DATA4)                   FM(CANFD_CLK_B)         F_(0, 0)        FM(D7)          FM(MMC_D2)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 203 #define IP6_7_4         FM(VI1_DATA5)                   F_(0,0)                 FM(SCK4)        FM(D8)          FM(MMC_D3)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 204 #define IP6_11_8        FM(VI1_DATA6)                   F_(0,0)                 FM(RX4)         FM(D9)          FM(MMC_CLK)             F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 205 #define IP6_15_12       FM(VI1_DATA7)                   F_(0,0)                 FM(TX4)         FM(D10)         FM(MMC_D4)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 206 #define IP6_19_16       FM(VI1_DATA8)                   F_(0,0)                 FM(CTS4_N)      FM(D11)         FM(MMC_D5)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 207 #define IP6_23_20       FM(VI1_DATA9)                   F_(0,0)                 FM(RTS4_N_TANS) FM(D12)         FM(MMC_D6)              FM(SCL3_B)      F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 208 #define IP6_27_24       FM(VI1_DATA10)                  F_(0,0)                 F_(0, 0)        FM(D13)         FM(MMC_D7)              FM(SDA3_B)      F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 209 #define IP6_31_28       FM(VI1_DATA11)                  FM(SCL4)                FM(IRQ4)        FM(D14)         FM(MMC_WP)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 210 #define IP7_3_0         FM(VI1_FIELD)                   FM(SDA4)                FM(IRQ5)        FM(D15)         FM(MMC_CD)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 211 #define IP7_7_4         FM(SCL0)                        FM(DU_DR0)              FM(TPU0TO0)     FM(CLKOUT)      F_(0, 0)                FM(MSIOF0_RXD)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 212 #define IP7_11_8        FM(SDA0)                        FM(DU_DR1)              FM(TPU0TO1)     FM(BS_N)        FM(SCK0)                FM(MSIOF0_TXD)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 213 #define IP7_15_12       FM(SCL1)                        FM(DU_DG0)              FM(TPU0TO2)     FM(RD_N)        FM(CTS0_N)              FM(MSIOF0_SCK)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 214 #define IP7_19_16       FM(SDA1)                        FM(DU_DG1)              FM(TPU0TO3)     FM(WE0_N)       FM(RTS0_N_TANS)         FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 215 #define IP7_23_20       FM(SCL2)                        FM(DU_DB0)              FM(TCLK1_A)     FM(WE1_N)       FM(RX0)                 FM(MSIOF0_SS1)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 216 #define IP7_27_24       FM(SDA2)                        FM(DU_DB1)              FM(TCLK2_A)     FM(EX_WAIT0)    FM(TX0)                 FM(MSIOF0_SS2)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217 #define IP7_31_28       FM(AVB0_AVTP_CAPTURE)           F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(FSCLKST2_N_B)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218 #define IP8_3_0         FM(CANFD0_TX_A)                 FM(FXR_TXDA)            FM(PWM0_B)      FM(DU_DISP)     FM(FSCLKST2_N_C)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219 #define IP8_7_4         FM(CANFD0_RX_A)                 FM(RXDA_EXTFXR)         FM(PWM1_B)      FM(DU_CDE)      F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP8_11_8        FM(CANFD1_TX)                   FM(FXR_TXDB)            FM(PWM2_B)      FM(TCLK1_B)     FM(TX1_B)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP8_15_12       FM(CANFD1_RX)                   FM(RXDB_EXTFXR)         FM(PWM3_B)      FM(TCLK2_B)     FM(RX1_B)               F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP8_19_16       FM(CANFD_CLK_A)                 FM(CLK_EXTFXR)          FM(PWM4_B)      FM(SPEEDIN_B)   FM(SCIF_CLK_B)          F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP8_23_20       FM(DIGRF_CLKIN)                 FM(DIGRF_CLKEN_IN)      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP8_27_24       FM(DIGRF_CLKOUT)                FM(DIGRF_CLKEN_OUT)     F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP8_31_28       F_(0, 0)                        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)  F_(0, 0) F_(0, 0) F_(0, 0)
 226
 227 #define PINMUX_GPSR     \
 228 \
 229                 GPSR1_27 \
 230                 GPSR1_26 \
 231                 GPSR1_25 \
 232                 GPSR1_24 \
 233                 GPSR1_23 \
 234                 GPSR1_22 \
 235 GPSR0_21        GPSR1_21 \
 236 GPSR0_20        GPSR1_20 \
 237 GPSR0_19        GPSR1_19 \
 238 GPSR0_18        GPSR1_18 \
 239 GPSR0_17        GPSR1_17 \
 240 GPSR0_16        GPSR1_16        GPSR2_16        GPSR3_16 \
 241 GPSR0_15        GPSR1_15        GPSR2_15        GPSR3_15 \
 242 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14                        GPSR5_14 \
 243 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13                        GPSR5_13 \
 244 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12                        GPSR5_12 \
 245 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11                        GPSR5_11 \
 246 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10                        GPSR5_10 \
 247 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9                         GPSR5_9 \
 248 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8                         GPSR5_8 \
 249 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7                         GPSR5_7 \
 250 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6                         GPSR5_6 \
 251 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5 \
 252 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4 \
 253 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3 \
 254 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2 \
 255 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1 \
 256 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0
 257
 258 #define PINMUX_IPSR     \
 259 \
 260 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 261 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 262 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 263 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 264 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 265 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 266 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 267 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 268 \
 269 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 270 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 271 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 272 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
 273 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 274 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 275 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 276 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 277 \
 278 FM(IP8_3_0)     IP8_3_0 \
 279 FM(IP8_7_4)     IP8_7_4 \
 280 FM(IP8_11_8)    IP8_11_8 \
 281 FM(IP8_15_12)   IP8_15_12 \
 282 FM(IP8_19_16)   IP8_19_16 \
 283 FM(IP8_23_20)   IP8_23_20 \
 284 FM(IP8_27_24)   IP8_27_24 \
 285 FM(IP8_31_28)   IP8_31_28
 286
 287 /* MOD_SEL0 */          /* 0 */                 /* 1 */
 288 #define MOD_SEL0_11     FM(SEL_I2C3_0)          FM(SEL_I2C3_1)
 289 #define MOD_SEL0_10     FM(SEL_HSCIF0_0)        FM(SEL_HSCIF0_1)
 290 #define MOD_SEL0_9      FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 291 #define MOD_SEL0_8      FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 292 #define MOD_SEL0_7      FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 293 #define MOD_SEL0_6      FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 294 #define MOD_SEL0_5      FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 295 #define MOD_SEL0_4      FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 296 #define MOD_SEL0_3      FM(SEL_PWM0_0)          FM(SEL_PWM0_1)
 297 #define MOD_SEL0_2      FM(SEL_RFSO_0)          FM(SEL_RFSO_1)
 298 #define MOD_SEL0_1      FM(SEL_RSP_0)           FM(SEL_RSP_1)
 299 #define MOD_SEL0_0      FM(SEL_TMU_0)           FM(SEL_TMU_1)
 300
 301 #define PINMUX_MOD_SELS \
 302 \
 303 MOD_SEL0_11 \
 304 MOD_SEL0_10 \
 305 MOD_SEL0_9 \
 306 MOD_SEL0_8 \
 307 MOD_SEL0_7 \
 308 MOD_SEL0_6 \
 309 MOD_SEL0_5 \
 310 MOD_SEL0_4 \
 311 MOD_SEL0_3 \
 312 MOD_SEL0_2 \
 313 MOD_SEL0_1 \
 314 MOD_SEL0_0
 315
 316 enum {
 317         PINMUX_RESERVED = 0,
 318
 319         PINMUX_DATA_BEGIN,
 320         GP_ALL(DATA),
 321         PINMUX_DATA_END,
 322
 323 #define F_(x, y)
 324 #define FM(x)   FN_##x,
 325         PINMUX_FUNCTION_BEGIN,
 326         GP_ALL(FN),
 327         PINMUX_GPSR
 328         PINMUX_IPSR
 329         PINMUX_MOD_SELS
 330         PINMUX_FUNCTION_END,
 331 #undef F_
 332 #undef FM
 333
 334 #define F_(x, y)
 335 #define FM(x)   x##_MARK,
 336         PINMUX_MARK_BEGIN,
 337         PINMUX_GPSR
 338         PINMUX_IPSR
 339         PINMUX_MOD_SELS
 340         PINMUX_MARK_END,
 341 #undef F_
 342 #undef FM
 343 };
 344
 345 static const u16 pinmux_data[] = {
 346         PINMUX_DATA_GP_ALL(),
 347
 348         PINMUX_SINGLE(AVB0_RX_CTL),
 349         PINMUX_SINGLE(AVB0_RXC),
 350         PINMUX_SINGLE(AVB0_RD0),
 351         PINMUX_SINGLE(AVB0_RD1),
 352         PINMUX_SINGLE(AVB0_RD2),
 353         PINMUX_SINGLE(AVB0_RD3),
 354         PINMUX_SINGLE(AVB0_TX_CTL),
 355         PINMUX_SINGLE(AVB0_TXC),
 356         PINMUX_SINGLE(AVB0_TD0),
 357         PINMUX_SINGLE(AVB0_TD1),
 358         PINMUX_SINGLE(AVB0_TD2),
 359         PINMUX_SINGLE(AVB0_TD3),
 360         PINMUX_SINGLE(AVB0_TXCREFCLK),
 361         PINMUX_SINGLE(AVB0_MDIO),
 362         PINMUX_SINGLE(AVB0_MDC),
 363         PINMUX_SINGLE(AVB0_MAGIC),
 364         PINMUX_SINGLE(AVB0_PHY_INT),
 365         PINMUX_SINGLE(AVB0_LINK),
 366         PINMUX_SINGLE(AVB0_AVTP_MATCH),
 367
 368         PINMUX_SINGLE(QSPI0_SPCLK),
 369         PINMUX_SINGLE(QSPI0_MOSI_IO0),
 370         PINMUX_SINGLE(QSPI0_MISO_IO1),
 371         PINMUX_SINGLE(QSPI0_IO2),
 372         PINMUX_SINGLE(QSPI0_IO3),
 373         PINMUX_SINGLE(QSPI0_SSL),
 374         PINMUX_SINGLE(QSPI1_SPCLK),
 375         PINMUX_SINGLE(QSPI1_MOSI_IO0),
 376         PINMUX_SINGLE(QSPI1_MISO_IO1),
 377         PINMUX_SINGLE(QSPI1_IO2),
 378         PINMUX_SINGLE(QSPI1_IO3),
 379         PINMUX_SINGLE(QSPI1_SSL),
 380         PINMUX_SINGLE(RPC_RESET_N),
 381         PINMUX_SINGLE(RPC_WP_N),
 382         PINMUX_SINGLE(RPC_INT_N),
 383
 384         /* IPSR0 */
 385         PINMUX_IPSR_GPSR(IP0_3_0,       DU_DR2),
 386         PINMUX_IPSR_GPSR(IP0_3_0,       HSCK0),
 387         PINMUX_IPSR_GPSR(IP0_3_0,       A0),
 388
 389         PINMUX_IPSR_GPSR(IP0_7_4,       DU_DR3),
 390         PINMUX_IPSR_GPSR(IP0_7_4,       HRTS0_N),
 391         PINMUX_IPSR_GPSR(IP0_7_4,       A1),
 392
 393         PINMUX_IPSR_GPSR(IP0_11_8,      DU_DR4),
 394         PINMUX_IPSR_GPSR(IP0_11_8,      HCTS0_N),
 395         PINMUX_IPSR_GPSR(IP0_11_8,      A2),
 396
 397         PINMUX_IPSR_GPSR(IP0_15_12,     DU_DR5),
 398         PINMUX_IPSR_GPSR(IP0_15_12,     HTX0),
 399         PINMUX_IPSR_GPSR(IP0_15_12,     A3),
 400
 401         PINMUX_IPSR_GPSR(IP0_19_16,     DU_DR6),
 402         PINMUX_IPSR_GPSR(IP0_19_16,     MSIOF3_RXD),
 403         PINMUX_IPSR_GPSR(IP0_19_16,     A4),
 404
 405         PINMUX_IPSR_GPSR(IP0_23_20,     DU_DR7),
 406         PINMUX_IPSR_GPSR(IP0_23_20,     MSIOF3_TXD),
 407         PINMUX_IPSR_GPSR(IP0_23_20,     A5),
 408
 409         PINMUX_IPSR_GPSR(IP0_27_24,     DU_DG2),
 410         PINMUX_IPSR_GPSR(IP0_27_24,     MSIOF3_SS1),
 411         PINMUX_IPSR_GPSR(IP0_27_24,     A6),
 412
 413         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DG3),
 414         PINMUX_IPSR_GPSR(IP0_31_28,     MSIOF3_SS2),
 415         PINMUX_IPSR_GPSR(IP0_31_28,     A7),
 416         PINMUX_IPSR_GPSR(IP0_31_28,     PWMFSW0),
 417
 418         /* IPSR1 */
 419         PINMUX_IPSR_GPSR(IP1_3_0,       DU_DG4),
 420         PINMUX_IPSR_GPSR(IP1_3_0,       A8),
 421         PINMUX_IPSR_MSEL(IP1_3_0,       FSO_CFE_0_N_A,  SEL_RFSO_0),
 422
 423         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DG5),
 424         PINMUX_IPSR_GPSR(IP1_7_4,       A9),
 425         PINMUX_IPSR_MSEL(IP1_7_4,       FSO_CFE_1_N_A,  SEL_RFSO_0),
 426
 427         PINMUX_IPSR_GPSR(IP1_11_8,      DU_DG6),
 428         PINMUX_IPSR_GPSR(IP1_11_8,      A10),
 429         PINMUX_IPSR_MSEL(IP1_11_8,      FSO_TOE_N_A,    SEL_RFSO_0),
 430
 431         PINMUX_IPSR_GPSR(IP1_15_12,     DU_DG7),
 432         PINMUX_IPSR_GPSR(IP1_15_12,     A11),
 433         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ1),
 434
 435         PINMUX_IPSR_GPSR(IP1_19_16,     DU_DB2),
 436         PINMUX_IPSR_GPSR(IP1_19_16,     A12),
 437         PINMUX_IPSR_GPSR(IP1_19_16,     IRQ2),
 438
 439         PINMUX_IPSR_GPSR(IP1_23_20,     DU_DB3),
 440         PINMUX_IPSR_GPSR(IP1_23_20,     A13),
 441         PINMUX_IPSR_GPSR(IP1_23_20,     FXR_CLKOUT1),
 442
 443         PINMUX_IPSR_GPSR(IP1_27_24,     DU_DB4),
 444         PINMUX_IPSR_GPSR(IP1_27_24,     A14),
 445         PINMUX_IPSR_GPSR(IP1_27_24,     FXR_CLKOUT2),
 446
 447         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB5),
 448         PINMUX_IPSR_GPSR(IP1_31_28,     A15),
 449         PINMUX_IPSR_GPSR(IP1_31_28,     FXR_TXENA_N),
 450
 451         /* IPSR2 */
 452         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB6),
 453         PINMUX_IPSR_GPSR(IP2_3_0,       A16),
 454         PINMUX_IPSR_GPSR(IP2_3_0,       FXR_TXENB_N),
 455
 456         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB7),
 457         PINMUX_IPSR_GPSR(IP2_7_4,       A17),
 458
 459         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DOTCLKOUT),
 460         PINMUX_IPSR_MSEL(IP2_11_8,      SCIF_CLK_A,     SEL_HSCIF0_0),
 461         PINMUX_IPSR_GPSR(IP2_11_8,      A18),
 462
 463         PINMUX_IPSR_GPSR(IP2_15_12,     DU_EXHSYNC_DU_HSYNC),
 464         PINMUX_IPSR_GPSR(IP2_15_12,     HRX0),
 465         PINMUX_IPSR_GPSR(IP2_15_12,     A19),
 466         PINMUX_IPSR_GPSR(IP2_15_12,     IRQ3),
 467
 468         PINMUX_IPSR_GPSR(IP2_19_16,     DU_EXVSYNC_DU_VSYNC),
 469         PINMUX_IPSR_GPSR(IP2_19_16,     MSIOF3_SCK),
 470
 471         PINMUX_IPSR_GPSR(IP2_23_20,     DU_EXODDF_DU_ODDF_DISP_CDE),
 472         PINMUX_IPSR_GPSR(IP2_23_20,     MSIOF3_SYNC),
 473
 474         PINMUX_IPSR_GPSR(IP2_27_24,     IRQ0),
 475         PINMUX_IPSR_GPSR(IP2_27_24,     CC5_OSCOUT),
 476
 477         PINMUX_IPSR_GPSR(IP2_31_28,     VI0_CLK),
 478         PINMUX_IPSR_GPSR(IP2_31_28,     MSIOF2_SCK),
 479         PINMUX_IPSR_GPSR(IP2_31_28,     SCK3),
 480         PINMUX_IPSR_GPSR(IP2_31_28,     HSCK3),
 481
 482         /* IPSR3 */
 483         PINMUX_IPSR_GPSR(IP3_3_0,       VI0_CLKENB),
 484         PINMUX_IPSR_GPSR(IP3_3_0,       MSIOF2_RXD),
 485         PINMUX_IPSR_GPSR(IP3_3_0,       RX3),
 486         PINMUX_IPSR_GPSR(IP3_3_0,       RD_WR_N),
 487         PINMUX_IPSR_GPSR(IP3_3_0,       HCTS3_N),
 488
 489         PINMUX_IPSR_GPSR(IP3_7_4,       VI0_HSYNC_N),
 490         PINMUX_IPSR_GPSR(IP3_7_4,       MSIOF2_TXD),
 491         PINMUX_IPSR_GPSR(IP3_7_4,       TX3),
 492         PINMUX_IPSR_GPSR(IP3_7_4,       HRTS3_N),
 493
 494         PINMUX_IPSR_GPSR(IP3_11_8,      VI0_VSYNC_N),
 495         PINMUX_IPSR_GPSR(IP3_11_8,      MSIOF2_SYNC),
 496         PINMUX_IPSR_GPSR(IP3_11_8,      CTS3_N),
 497         PINMUX_IPSR_GPSR(IP3_11_8,      HTX3),
 498
 499         PINMUX_IPSR_GPSR(IP3_15_12,     VI0_DATA0),
 500         PINMUX_IPSR_GPSR(IP3_15_12,     MSIOF2_SS1),
 501         PINMUX_IPSR_GPSR(IP3_15_12,     RTS3_N_TANS),
 502         PINMUX_IPSR_GPSR(IP3_15_12,     HRX3),
 503
 504         PINMUX_IPSR_GPSR(IP3_19_16,     VI0_DATA1),
 505         PINMUX_IPSR_GPSR(IP3_19_16,     MSIOF2_SS2),
 506         PINMUX_IPSR_GPSR(IP3_19_16,     SCK1),
 507         PINMUX_IPSR_MSEL(IP3_19_16,     SPEEDIN_A,      SEL_RSP_0),
 508
 509         PINMUX_IPSR_GPSR(IP3_23_20,     VI0_DATA2),
 510         PINMUX_IPSR_GPSR(IP3_23_20,     AVB0_AVTP_PPS),
 511         PINMUX_IPSR_MSEL(IP3_23_20,     SDA3_A,         SEL_I2C3_0),
 512
 513         PINMUX_IPSR_GPSR(IP3_27_24,     VI0_DATA3),
 514         PINMUX_IPSR_GPSR(IP3_27_24,     HSCK1),
 515         PINMUX_IPSR_MSEL(IP3_27_24,     SCL3_A,         SEL_I2C3_0),
 516
 517         PINMUX_IPSR_GPSR(IP3_31_28,     VI0_DATA4),
 518         PINMUX_IPSR_GPSR(IP3_31_28,     HRTS1_N),
 519         PINMUX_IPSR_MSEL(IP3_31_28,     RX1_A,  SEL_SCIF1_0),
 520
 521         /* IPSR4 */
 522         PINMUX_IPSR_GPSR(IP4_3_0,       VI0_DATA5),
 523         PINMUX_IPSR_GPSR(IP4_3_0,       HCTS1_N),
 524         PINMUX_IPSR_MSEL(IP4_3_0,       TX1_A,  SEL_SCIF1_0),
 525
 526         PINMUX_IPSR_GPSR(IP4_7_4,       VI0_DATA6),
 527         PINMUX_IPSR_GPSR(IP4_7_4,       HTX1),
 528         PINMUX_IPSR_GPSR(IP4_7_4,       CTS1_N),
 529
 530         PINMUX_IPSR_GPSR(IP4_11_8,      VI0_DATA7),
 531         PINMUX_IPSR_GPSR(IP4_11_8,      HRX1),
 532         PINMUX_IPSR_GPSR(IP4_11_8,      RTS1_N_TANS),
 533
 534         PINMUX_IPSR_GPSR(IP4_15_12,     VI0_DATA8),
 535         PINMUX_IPSR_GPSR(IP4_15_12,     HSCK2),
 536         PINMUX_IPSR_MSEL(IP4_15_12,     PWM0_A, SEL_PWM0_0),
 537
 538         PINMUX_IPSR_GPSR(IP4_19_16,     VI0_DATA9),
 539         PINMUX_IPSR_GPSR(IP4_19_16,     HCTS2_N),
 540         PINMUX_IPSR_MSEL(IP4_19_16,     PWM1_A, SEL_PWM1_0),
 541         PINMUX_IPSR_MSEL(IP4_19_16,     FSO_CFE_0_N_B,  SEL_RFSO_1),
 542
 543         PINMUX_IPSR_GPSR(IP4_23_20,     VI0_DATA10),
 544         PINMUX_IPSR_GPSR(IP4_23_20,     HRTS2_N),
 545         PINMUX_IPSR_MSEL(IP4_23_20,     PWM2_A, SEL_PWM2_0),
 546         PINMUX_IPSR_MSEL(IP4_23_20,     FSO_CFE_1_N_B,  SEL_RFSO_1),
 547
 548         PINMUX_IPSR_GPSR(IP4_27_24,     VI0_DATA11),
 549         PINMUX_IPSR_GPSR(IP4_27_24,     HTX2),
 550         PINMUX_IPSR_MSEL(IP4_27_24,     PWM3_A, SEL_PWM3_0),
 551         PINMUX_IPSR_MSEL(IP4_27_24,     FSO_TOE_N_B,    SEL_RFSO_1),
 552
 553         PINMUX_IPSR_GPSR(IP4_31_28,     VI0_FIELD),
 554         PINMUX_IPSR_GPSR(IP4_31_28,     HRX2),
 555         PINMUX_IPSR_MSEL(IP4_31_28,     PWM4_A, SEL_PWM4_0),
 556         PINMUX_IPSR_GPSR(IP4_31_28,     CS1_N),
 557         PINMUX_IPSR_GPSR(IP4_31_28,     FSCLKST2_N_A),
 558
 559         /* IPSR5 */
 560         PINMUX_IPSR_GPSR(IP5_3_0,       VI1_CLK),
 561         PINMUX_IPSR_GPSR(IP5_3_0,       MSIOF1_RXD),
 562         PINMUX_IPSR_GPSR(IP5_3_0,       CS0_N),
 563
 564         PINMUX_IPSR_GPSR(IP5_7_4,       VI1_CLKENB),
 565         PINMUX_IPSR_GPSR(IP5_7_4,       MSIOF1_TXD),
 566         PINMUX_IPSR_GPSR(IP5_7_4,       D0),
 567
 568         PINMUX_IPSR_GPSR(IP5_11_8,      VI1_HSYNC_N),
 569         PINMUX_IPSR_GPSR(IP5_11_8,      MSIOF1_SCK),
 570         PINMUX_IPSR_GPSR(IP5_11_8,      D1),
 571
 572         PINMUX_IPSR_GPSR(IP5_15_12,     VI1_VSYNC_N),
 573         PINMUX_IPSR_GPSR(IP5_15_12,     MSIOF1_SYNC),
 574         PINMUX_IPSR_GPSR(IP5_15_12,     D2),
 575
 576         PINMUX_IPSR_GPSR(IP5_19_16,     VI1_DATA0),
 577         PINMUX_IPSR_GPSR(IP5_19_16,     MSIOF1_SS1),
 578         PINMUX_IPSR_GPSR(IP5_19_16,     D3),
 579
 580         PINMUX_IPSR_GPSR(IP5_23_20,     VI1_DATA1),
 581         PINMUX_IPSR_GPSR(IP5_23_20,     MSIOF1_SS2),
 582         PINMUX_IPSR_GPSR(IP5_23_20,     D4),
 583         PINMUX_IPSR_GPSR(IP5_23_20,     MMC_CMD),
 584
 585         PINMUX_IPSR_GPSR(IP5_27_24,     VI1_DATA2),
 586         PINMUX_IPSR_MSEL(IP5_27_24,     CANFD0_TX_B,    SEL_CANFD0_1),
 587         PINMUX_IPSR_GPSR(IP5_27_24,     D5),
 588         PINMUX_IPSR_GPSR(IP5_27_24,     MMC_D0),
 589
 590         PINMUX_IPSR_GPSR(IP5_31_28,     VI1_DATA3),
 591         PINMUX_IPSR_MSEL(IP5_31_28,     CANFD0_RX_B,    SEL_CANFD0_1),
 592         PINMUX_IPSR_GPSR(IP5_31_28,     D6),
 593         PINMUX_IPSR_GPSR(IP5_31_28,     MMC_D1),
 594
 595         /* IPSR6 */
 596         PINMUX_IPSR_GPSR(IP6_3_0,       VI1_DATA4),
 597         PINMUX_IPSR_MSEL(IP6_3_0,       CANFD_CLK_B,    SEL_CANFD0_1),
 598         PINMUX_IPSR_GPSR(IP6_3_0,       D7),
 599         PINMUX_IPSR_GPSR(IP6_3_0,       MMC_D2),
 600
 601         PINMUX_IPSR_GPSR(IP6_7_4,       VI1_DATA5),
 602         PINMUX_IPSR_GPSR(IP6_7_4,       SCK4),
 603         PINMUX_IPSR_GPSR(IP6_7_4,       D8),
 604         PINMUX_IPSR_GPSR(IP6_7_4,       MMC_D3),
 605
 606         PINMUX_IPSR_GPSR(IP6_11_8,      VI1_DATA6),
 607         PINMUX_IPSR_GPSR(IP6_11_8,      RX4),
 608         PINMUX_IPSR_GPSR(IP6_11_8,      D9),
 609         PINMUX_IPSR_GPSR(IP6_11_8,      MMC_CLK),
 610
 611         PINMUX_IPSR_GPSR(IP6_15_12,     VI1_DATA7),
 612         PINMUX_IPSR_GPSR(IP6_15_12,     TX4),
 613         PINMUX_IPSR_GPSR(IP6_15_12,     D10),
 614         PINMUX_IPSR_GPSR(IP6_15_12,     MMC_D4),
 615
 616         PINMUX_IPSR_GPSR(IP6_19_16,     VI1_DATA8),
 617         PINMUX_IPSR_GPSR(IP6_19_16,     CTS4_N),
 618         PINMUX_IPSR_GPSR(IP6_19_16,     D11),
 619         PINMUX_IPSR_GPSR(IP6_19_16,     MMC_D5),
 620
 621         PINMUX_IPSR_GPSR(IP6_23_20,     VI1_DATA9),
 622         PINMUX_IPSR_GPSR(IP6_23_20,     RTS4_N_TANS),
 623         PINMUX_IPSR_GPSR(IP6_23_20,     D12),
 624         PINMUX_IPSR_GPSR(IP6_23_20,     MMC_D6),
 625         PINMUX_IPSR_MSEL(IP6_23_20,     SCL3_B, SEL_I2C3_1),
 626
 627         PINMUX_IPSR_GPSR(IP6_27_24,     VI1_DATA10),
 628         PINMUX_IPSR_GPSR(IP6_27_24,     D13),
 629         PINMUX_IPSR_GPSR(IP6_27_24,     MMC_D7),
 630         PINMUX_IPSR_MSEL(IP6_27_24,     SDA3_B, SEL_I2C3_1),
 631
 632         PINMUX_IPSR_GPSR(IP6_31_28,     VI1_DATA11),
 633         PINMUX_IPSR_GPSR(IP6_31_28,     SCL4),
 634         PINMUX_IPSR_GPSR(IP6_31_28,     IRQ4),
 635         PINMUX_IPSR_GPSR(IP6_31_28,     D14),
 636         PINMUX_IPSR_GPSR(IP6_31_28,     MMC_WP),
 637
 638         /* IPSR7 */
 639         PINMUX_IPSR_GPSR(IP7_3_0,       VI1_FIELD),
 640         PINMUX_IPSR_GPSR(IP7_3_0,       SDA4),
 641         PINMUX_IPSR_GPSR(IP7_3_0,       IRQ5),
 642         PINMUX_IPSR_GPSR(IP7_3_0,       D15),
 643         PINMUX_IPSR_GPSR(IP7_3_0,       MMC_CD),
 644
 645         PINMUX_IPSR_GPSR(IP7_7_4,       SCL0),
 646         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR0),
 647         PINMUX_IPSR_GPSR(IP7_7_4,       TPU0TO0),
 648         PINMUX_IPSR_GPSR(IP7_7_4,       CLKOUT),
 649         PINMUX_IPSR_GPSR(IP7_7_4,       MSIOF0_RXD),
 650
 651         PINMUX_IPSR_GPSR(IP7_11_8,      SDA0),
 652         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR1),
 653         PINMUX_IPSR_GPSR(IP7_11_8,      TPU0TO1),
 654         PINMUX_IPSR_GPSR(IP7_11_8,      BS_N),
 655         PINMUX_IPSR_GPSR(IP7_11_8,      SCK0),
 656         PINMUX_IPSR_GPSR(IP7_11_8,      MSIOF0_TXD),
 657
 658         PINMUX_IPSR_GPSR(IP7_15_12,     SCL1),
 659         PINMUX_IPSR_GPSR(IP7_15_12,     DU_DG0),
 660         PINMUX_IPSR_GPSR(IP7_15_12,     TPU0TO2),
 661         PINMUX_IPSR_GPSR(IP7_15_12,     RD_N),
 662         PINMUX_IPSR_GPSR(IP7_15_12,     CTS0_N),
 663         PINMUX_IPSR_GPSR(IP7_15_12,     MSIOF0_SCK),
 664
 665         PINMUX_IPSR_GPSR(IP7_19_16,     SDA1),
 666         PINMUX_IPSR_GPSR(IP7_19_16,     DU_DG1),
 667         PINMUX_IPSR_GPSR(IP7_19_16,     TPU0TO3),
 668         PINMUX_IPSR_GPSR(IP7_19_16,     WE0_N),
 669         PINMUX_IPSR_GPSR(IP7_19_16,     RTS0_N_TANS),
 670         PINMUX_IPSR_GPSR(IP7_19_16,     MSIOF0_SYNC),
 671
 672         PINMUX_IPSR_GPSR(IP7_23_20,     SCL2),
 673         PINMUX_IPSR_GPSR(IP7_23_20,     DU_DB0),
 674         PINMUX_IPSR_MSEL(IP7_23_20,     TCLK1_A,        SEL_TMU_0),
 675         PINMUX_IPSR_GPSR(IP7_23_20,     WE1_N),
 676         PINMUX_IPSR_GPSR(IP7_23_20,     RX0),
 677         PINMUX_IPSR_GPSR(IP7_23_20,     MSIOF0_SS1),
 678
 679         PINMUX_IPSR_GPSR(IP7_27_24,     SDA2),
 680         PINMUX_IPSR_GPSR(IP7_27_24,     DU_DB1),
 681         PINMUX_IPSR_MSEL(IP7_27_24,     TCLK2_A,        SEL_TMU_0),
 682         PINMUX_IPSR_GPSR(IP7_27_24,     EX_WAIT0),
 683         PINMUX_IPSR_GPSR(IP7_27_24,     TX0),
 684         PINMUX_IPSR_GPSR(IP7_27_24,     MSIOF0_SS2),
 685
 686         PINMUX_IPSR_GPSR(IP7_31_28,     AVB0_AVTP_CAPTURE),
 687         PINMUX_IPSR_GPSR(IP7_31_28,     FSCLKST2_N_B),
 688
 689         /* IPSR8 */
 690         PINMUX_IPSR_MSEL(IP8_3_0,       CANFD0_TX_A,    SEL_CANFD0_0),
 691         PINMUX_IPSR_GPSR(IP8_3_0,       FXR_TXDA),
 692         PINMUX_IPSR_MSEL(IP8_3_0,       PWM0_B,         SEL_PWM0_1),
 693         PINMUX_IPSR_GPSR(IP8_3_0,       DU_DISP),
 694         PINMUX_IPSR_GPSR(IP8_3_0,       FSCLKST2_N_C),
 695
 696         PINMUX_IPSR_MSEL(IP8_7_4,       CANFD0_RX_A,    SEL_CANFD0_0),
 697         PINMUX_IPSR_GPSR(IP8_7_4,       RXDA_EXTFXR),
 698         PINMUX_IPSR_MSEL(IP8_7_4,       PWM1_B,         SEL_PWM1_1),
 699         PINMUX_IPSR_GPSR(IP8_7_4,       DU_CDE),
 700
 701         PINMUX_IPSR_GPSR(IP8_11_8,      CANFD1_TX),
 702         PINMUX_IPSR_GPSR(IP8_11_8,      FXR_TXDB),
 703         PINMUX_IPSR_MSEL(IP8_11_8,      PWM2_B,         SEL_PWM2_1),
 704         PINMUX_IPSR_MSEL(IP8_11_8,      TCLK1_B,        SEL_TMU_1),
 705         PINMUX_IPSR_MSEL(IP8_11_8,      TX1_B,          SEL_SCIF1_1),
 706
 707         PINMUX_IPSR_GPSR(IP8_15_12,     CANFD1_RX),
 708         PINMUX_IPSR_GPSR(IP8_15_12,     RXDB_EXTFXR),
 709         PINMUX_IPSR_MSEL(IP8_15_12,     PWM3_B,         SEL_PWM3_1),
 710         PINMUX_IPSR_MSEL(IP8_15_12,     TCLK2_B,        SEL_TMU_1),
 711         PINMUX_IPSR_MSEL(IP8_15_12,     RX1_B,          SEL_SCIF1_1),
 712
 713         PINMUX_IPSR_MSEL(IP8_19_16,     CANFD_CLK_A,    SEL_CANFD0_0),
 714         PINMUX_IPSR_GPSR(IP8_19_16,     CLK_EXTFXR),
 715         PINMUX_IPSR_MSEL(IP8_19_16,     PWM4_B,         SEL_PWM4_1),
 716         PINMUX_IPSR_MSEL(IP8_19_16,     SPEEDIN_B,      SEL_RSP_1),
 717         PINMUX_IPSR_MSEL(IP8_19_16,     SCIF_CLK_B,     SEL_HSCIF0_1),
 718
 719         PINMUX_IPSR_GPSR(IP8_23_20,     DIGRF_CLKIN),
 720         PINMUX_IPSR_GPSR(IP8_23_20,     DIGRF_CLKEN_IN),
 721
 722         PINMUX_IPSR_GPSR(IP8_27_24,     DIGRF_CLKOUT),
 723         PINMUX_IPSR_GPSR(IP8_27_24,     DIGRF_CLKEN_OUT),
 724 };
 725
 726 static const struct sh_pfc_pin pinmux_pins[] = {
 727         PINMUX_GPIO_GP_ALL(),
 728 };
 729
 730 /* - AVB0 ------------------------------------------------------------------- */
 731 static const unsigned int avb0_link_pins[] = {
 732         /* AVB0_LINK */
 733         RCAR_GP_PIN(1, 18),
 734 };
 735 static const unsigned int avb0_link_mux[] = {
 736         AVB0_LINK_MARK,
 737 };
 738 static const unsigned int avb0_magic_pins[] = {
 739         /* AVB0_MAGIC */
 740         RCAR_GP_PIN(1, 16),
 741 };
 742 static const unsigned int avb0_magic_mux[] = {
 743         AVB0_MAGIC_MARK,
 744 };
 745 static const unsigned int avb0_phy_int_pins[] = {
 746         /* AVB0_PHY_INT */
 747         RCAR_GP_PIN(1, 17),
 748 };
 749 static const unsigned int avb0_phy_int_mux[] = {
 750         AVB0_PHY_INT_MARK,
 751 };
 752 static const unsigned int avb0_mdio_pins[] = {
 753         /* AVB0_MDC, AVB0_MDIO */
 754         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
 755 };
 756 static const unsigned int avb0_mdio_mux[] = {
 757         AVB0_MDC_MARK, AVB0_MDIO_MARK,
 758 };
 759 static const unsigned int avb0_rgmii_pins[] = {
 760         /*
 761          * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
 762          * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
 763          */
 764         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
 765         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
 766         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
 767         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
 768         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
 769         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
 770 };
 771 static const unsigned int avb0_rgmii_mux[] = {
 772         AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
 773         AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
 774         AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
 775         AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
 776 };
 777 static const unsigned int avb0_txcrefclk_pins[] = {
 778         /* AVB0_TXCREFCLK */
 779         RCAR_GP_PIN(1, 13),
 780 };
 781 static const unsigned int avb0_txcrefclk_mux[] = {
 782         AVB0_TXCREFCLK_MARK,
 783 };
 784 static const unsigned int avb0_avtp_pps_pins[] = {
 785         /* AVB0_AVTP_PPS */
 786         RCAR_GP_PIN(2, 6),
 787 };
 788 static const unsigned int avb0_avtp_pps_mux[] = {
 789         AVB0_AVTP_PPS_MARK,
 790 };
 791 static const unsigned int avb0_avtp_capture_pins[] = {
 792         /* AVB0_AVTP_CAPTURE */
 793         RCAR_GP_PIN(1, 20),
 794 };
 795 static const unsigned int avb0_avtp_capture_mux[] = {
 796         AVB0_AVTP_CAPTURE_MARK,
 797 };
 798 static const unsigned int avb0_avtp_match_pins[] = {
 799         /* AVB0_AVTP_MATCH */
 800         RCAR_GP_PIN(1, 19),
 801 };
 802 static const unsigned int avb0_avtp_match_mux[] = {
 803         AVB0_AVTP_MATCH_MARK,
 804 };
 805
 806 /* - CANFD Clock ------------------------------------------------------------ */
 807 static const unsigned int canfd_clk_a_pins[] = {
 808         /* CANFD_CLK */
 809         RCAR_GP_PIN(1, 25),
 810 };
 811 static const unsigned int canfd_clk_a_mux[] = {
 812         CANFD_CLK_A_MARK,
 813 };
 814 static const unsigned int canfd_clk_b_pins[] = {
 815         /* CANFD_CLK */
 816         RCAR_GP_PIN(3, 8),
 817 };
 818 static const unsigned int canfd_clk_b_mux[] = {
 819         CANFD_CLK_B_MARK,
 820 };
 821
 822 /* - CANFD0 ----------------------------------------------------------------- */
 823 static const unsigned int canfd0_data_a_pins[] = {
 824         /* TX, RX */
 825         RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
 826 };
 827 static const unsigned int canfd0_data_a_mux[] = {
 828         CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
 829 };
 830 static const unsigned int canfd0_data_b_pins[] = {
 831         /* TX, RX */
 832         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 833 };
 834 static const unsigned int canfd0_data_b_mux[] = {
 835         CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
 836 };
 837
 838 /* - CANFD1 ----------------------------------------------------------------- */
 839 static const unsigned int canfd1_data_pins[] = {
 840         /* TX, RX */
 841         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
 842 };
 843 static const unsigned int canfd1_data_mux[] = {
 844         CANFD1_TX_MARK, CANFD1_RX_MARK,
 845 };
 846
 847 /* - DU --------------------------------------------------------------------- */
 848 static const unsigned int du_rgb666_pins[] = {
 849         /* R[7:2], G[7:2], B[7:2] */
 850         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
 851         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 852         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
 853         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
 854         RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
 855         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
 856 };
 857 static const unsigned int du_rgb666_mux[] = {
 858         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
 859         DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
 860         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
 861         DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
 862         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
 863         DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
 864 };
 865 static const unsigned int du_clk_out_pins[] = {
 866         /* DOTCLKOUT */
 867         RCAR_GP_PIN(0, 18),
 868 };
 869 static const unsigned int du_clk_out_mux[] = {
 870         DU_DOTCLKOUT_MARK,
 871 };
 872 static const unsigned int du_sync_pins[] = {
 873         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 874         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 875 };
 876 static const unsigned int du_sync_mux[] = {
 877         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
 878 };
 879 static const unsigned int du_oddf_pins[] = {
 880         /* EXODDF/ODDF/DISP/CDE */
 881         RCAR_GP_PIN(0, 21),
 882 };
 883 static const unsigned int du_oddf_mux[] = {
 884         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
 885 };
 886 static const unsigned int du_cde_pins[] = {
 887         /* CDE */
 888         RCAR_GP_PIN(1, 22),
 889 };
 890 static const unsigned int du_cde_mux[] = {
 891         DU_CDE_MARK,
 892 };
 893 static const unsigned int du_disp_pins[] = {
 894         /* DISP */
 895         RCAR_GP_PIN(1, 21),
 896 };
 897 static const unsigned int du_disp_mux[] = {
 898         DU_DISP_MARK,
 899 };
 900
 901 /* - HSCIF0 ----------------------------------------------------------------- */
 902 static const unsigned int hscif0_data_pins[] = {
 903         /* HRX, HTX */
 904         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
 905 };
 906 static const unsigned int hscif0_data_mux[] = {
 907         HRX0_MARK, HTX0_MARK,
 908 };
 909 static const unsigned int hscif0_clk_pins[] = {
 910         /* HSCK */
 911         RCAR_GP_PIN(0, 0),
 912 };
 913 static const unsigned int hscif0_clk_mux[] = {
 914         HSCK0_MARK,
 915 };
 916 static const unsigned int hscif0_ctrl_pins[] = {
 917         /* HRTS#, HCTS# */
 918         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
 919 };
 920 static const unsigned int hscif0_ctrl_mux[] = {
 921         HRTS0_N_MARK, HCTS0_N_MARK,
 922 };
 923
 924 /* - HSCIF1 ----------------------------------------------------------------- */
 925 static const unsigned int hscif1_data_pins[] = {
 926         /* HRX, HTX */
 927         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
 928 };
 929 static const unsigned int hscif1_data_mux[] = {
 930         HRX1_MARK, HTX1_MARK,
 931 };
 932 static const unsigned int hscif1_clk_pins[] = {
 933         /* HSCK */
 934         RCAR_GP_PIN(2, 7),
 935 };
 936 static const unsigned int hscif1_clk_mux[] = {
 937         HSCK1_MARK,
 938 };
 939 static const unsigned int hscif1_ctrl_pins[] = {
 940         /* HRTS#, HCTS# */
 941         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
 942 };
 943 static const unsigned int hscif1_ctrl_mux[] = {
 944         HRTS1_N_MARK, HCTS1_N_MARK,
 945 };
 946
 947 /* - HSCIF2 ----------------------------------------------------------------- */
 948 static const unsigned int hscif2_data_pins[] = {
 949         /* HRX, HTX */
 950         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
 951 };
 952 static const unsigned int hscif2_data_mux[] = {
 953         HRX2_MARK, HTX2_MARK,
 954 };
 955 static const unsigned int hscif2_clk_pins[] = {
 956         /* HSCK */
 957         RCAR_GP_PIN(2, 12),
 958 };
 959 static const unsigned int hscif2_clk_mux[] = {
 960         HSCK2_MARK,
 961 };
 962 static const unsigned int hscif2_ctrl_pins[] = {
 963         /* HRTS#, HCTS# */
 964         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
 965 };
 966 static const unsigned int hscif2_ctrl_mux[] = {
 967         HRTS2_N_MARK, HCTS2_N_MARK,
 968 };
 969
 970 /* - HSCIF3 ----------------------------------------------------------------- */
 971 static const unsigned int hscif3_data_pins[] = {
 972         /* HRX, HTX */
 973         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
 974 };
 975 static const unsigned int hscif3_data_mux[] = {
 976         HRX3_MARK, HTX3_MARK,
 977 };
 978 static const unsigned int hscif3_clk_pins[] = {
 979         /* HSCK */
 980         RCAR_GP_PIN(2, 0),
 981 };
 982 static const unsigned int hscif3_clk_mux[] = {
 983         HSCK3_MARK,
 984 };
 985 static const unsigned int hscif3_ctrl_pins[] = {
 986         /* HRTS#, HCTS# */
 987         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
 988 };
 989 static const unsigned int hscif3_ctrl_mux[] = {
 990         HRTS3_N_MARK, HCTS3_N_MARK,
 991 };
 992
 993 /* - I2C0 ------------------------------------------------------------------- */
 994 static const unsigned int i2c0_pins[] = {
 995         /* SDA, SCL */
 996         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
 997 };
 998 static const unsigned int i2c0_mux[] = {
 999         SDA0_MARK, SCL0_MARK,
1000 };
1001
1002 /* - I2C1 ------------------------------------------------------------------- */
1003 static const unsigned int i2c1_pins[] = {
1004         /* SDA, SCL */
1005         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1006 };
1007 static const unsigned int i2c1_mux[] = {
1008         SDA1_MARK, SCL1_MARK,
1009 };
1010
1011 /* - I2C2 ------------------------------------------------------------------- */
1012 static const unsigned int i2c2_pins[] = {
1013         /* SDA, SCL */
1014         RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1015 };
1016 static const unsigned int i2c2_mux[] = {
1017         SDA2_MARK, SCL2_MARK,
1018 };
1019
1020 /* - I2C3 ------------------------------------------------------------------- */
1021 static const unsigned int i2c3_a_pins[] = {
1022         /* SDA, SCL */
1023         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1024 };
1025 static const unsigned int i2c3_a_mux[] = {
1026         SDA3_A_MARK, SCL3_A_MARK,
1027 };
1028 static const unsigned int i2c3_b_pins[] = {
1029         /* SDA, SCL */
1030         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1031 };
1032 static const unsigned int i2c3_b_mux[] = {
1033         SDA3_B_MARK, SCL3_B_MARK,
1034 };
1035
1036 /* - I2C4 ------------------------------------------------------------------- */
1037 static const unsigned int i2c4_pins[] = {
1038         /* SDA, SCL */
1039         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1040 };
1041 static const unsigned int i2c4_mux[] = {
1042         SDA4_MARK, SCL4_MARK,
1043 };
1044
1045 /* - INTC-EX ---------------------------------------------------------------- */
1046 static const unsigned int intc_ex_irq0_pins[] = {
1047         /* IRQ0 */
1048         RCAR_GP_PIN(1, 0),
1049 };
1050 static const unsigned int intc_ex_irq0_mux[] = {
1051         IRQ0_MARK,
1052 };
1053 static const unsigned int intc_ex_irq1_pins[] = {
1054         /* IRQ1 */
1055         RCAR_GP_PIN(0, 11),
1056 };
1057 static const unsigned int intc_ex_irq1_mux[] = {
1058         IRQ1_MARK,
1059 };
1060 static const unsigned int intc_ex_irq2_pins[] = {
1061         /* IRQ2 */
1062         RCAR_GP_PIN(0, 12),
1063 };
1064 static const unsigned int intc_ex_irq2_mux[] = {
1065         IRQ2_MARK,
1066 };
1067 static const unsigned int intc_ex_irq3_pins[] = {
1068         /* IRQ3 */
1069         RCAR_GP_PIN(0, 19),
1070 };
1071 static const unsigned int intc_ex_irq3_mux[] = {
1072         IRQ3_MARK,
1073 };
1074 static const unsigned int intc_ex_irq4_pins[] = {
1075         /* IRQ4 */
1076         RCAR_GP_PIN(3, 15),
1077 };
1078 static const unsigned int intc_ex_irq4_mux[] = {
1079         IRQ4_MARK,
1080 };
1081 static const unsigned int intc_ex_irq5_pins[] = {
1082         /* IRQ5 */
1083         RCAR_GP_PIN(3, 16),
1084 };
1085 static const unsigned int intc_ex_irq5_mux[] = {
1086         IRQ5_MARK,
1087 };
1088
1089 /* - MMC -------------------------------------------------------------------- */
1090 static const unsigned int mmc_data1_pins[] = {
1091         /* D0 */
1092         RCAR_GP_PIN(3, 6),
1093 };
1094 static const unsigned int mmc_data1_mux[] = {
1095         MMC_D0_MARK,
1096 };
1097 static const unsigned int mmc_data4_pins[] = {
1098         /* D[0:3] */
1099         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1100         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1101 };
1102 static const unsigned int mmc_data4_mux[] = {
1103         MMC_D0_MARK, MMC_D1_MARK,
1104         MMC_D2_MARK, MMC_D3_MARK,
1105 };
1106 static const unsigned int mmc_data8_pins[] = {
1107         /* D[0:7] */
1108         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1109         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1110         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1111         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1112 };
1113 static const unsigned int mmc_data8_mux[] = {
1114         MMC_D0_MARK, MMC_D1_MARK,
1115         MMC_D2_MARK, MMC_D3_MARK,
1116         MMC_D4_MARK, MMC_D5_MARK,
1117         MMC_D6_MARK, MMC_D7_MARK,
1118 };
1119 static const unsigned int mmc_ctrl_pins[] = {
1120         /* CLK, CMD */
1121         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1122 };
1123 static const unsigned int mmc_ctrl_mux[] = {
1124         MMC_CLK_MARK, MMC_CMD_MARK,
1125 };
1126 static const unsigned int mmc_cd_pins[] = {
1127         /* CD */
1128         RCAR_GP_PIN(3, 16),
1129 };
1130 static const unsigned int mmc_cd_mux[] = {
1131         MMC_CD_MARK,
1132 };
1133 static const unsigned int mmc_wp_pins[] = {
1134         /* WP */
1135         RCAR_GP_PIN(3, 15),
1136 };
1137 static const unsigned int mmc_wp_mux[] = {
1138         MMC_WP_MARK,
1139 };
1140
1141 /* - MSIOF0 ----------------------------------------------------------------- */
1142 static const unsigned int msiof0_clk_pins[] = {
1143         /* SCK */
1144         RCAR_GP_PIN(4, 2),
1145 };
1146 static const unsigned int msiof0_clk_mux[] = {
1147         MSIOF0_SCK_MARK,
1148 };
1149 static const unsigned int msiof0_sync_pins[] = {
1150         /* SYNC */
1151         RCAR_GP_PIN(4, 3),
1152 };
1153 static const unsigned int msiof0_sync_mux[] = {
1154         MSIOF0_SYNC_MARK,
1155 };
1156 static const unsigned int msiof0_ss1_pins[] = {
1157         /* SS1 */
1158         RCAR_GP_PIN(4, 4),
1159 };
1160 static const unsigned int msiof0_ss1_mux[] = {
1161         MSIOF0_SS1_MARK,
1162 };
1163 static const unsigned int msiof0_ss2_pins[] = {
1164         /* SS2 */
1165         RCAR_GP_PIN(4, 5),
1166 };
1167 static const unsigned int msiof0_ss2_mux[] = {
1168         MSIOF0_SS2_MARK,
1169 };
1170 static const unsigned int msiof0_txd_pins[] = {
1171         /* TXD */
1172         RCAR_GP_PIN(4, 1),
1173 };
1174 static const unsigned int msiof0_txd_mux[] = {
1175         MSIOF0_TXD_MARK,
1176 };
1177 static const unsigned int msiof0_rxd_pins[] = {
1178         /* RXD */
1179         RCAR_GP_PIN(4, 0),
1180 };
1181 static const unsigned int msiof0_rxd_mux[] = {
1182         MSIOF0_RXD_MARK,
1183 };
1184
1185 /* - MSIOF1 ----------------------------------------------------------------- */
1186 static const unsigned int msiof1_clk_pins[] = {
1187         /* SCK */
1188         RCAR_GP_PIN(3, 2),
1189 };
1190 static const unsigned int msiof1_clk_mux[] = {
1191         MSIOF1_SCK_MARK,
1192 };
1193 static const unsigned int msiof1_sync_pins[] = {
1194         /* SYNC */
1195         RCAR_GP_PIN(3, 3),
1196 };
1197 static const unsigned int msiof1_sync_mux[] = {
1198         MSIOF1_SYNC_MARK,
1199 };
1200 static const unsigned int msiof1_ss1_pins[] = {
1201         /* SS1 */
1202         RCAR_GP_PIN(3, 4),
1203 };
1204 static const unsigned int msiof1_ss1_mux[] = {
1205         MSIOF1_SS1_MARK,
1206 };
1207 static const unsigned int msiof1_ss2_pins[] = {
1208         /* SS2 */
1209         RCAR_GP_PIN(3, 5),
1210 };
1211 static const unsigned int msiof1_ss2_mux[] = {
1212         MSIOF1_SS2_MARK,
1213 };
1214 static const unsigned int msiof1_txd_pins[] = {
1215         /* TXD */
1216         RCAR_GP_PIN(3, 1),
1217 };
1218 static const unsigned int msiof1_txd_mux[] = {
1219         MSIOF1_TXD_MARK,
1220 };
1221 static const unsigned int msiof1_rxd_pins[] = {
1222         /* RXD */
1223         RCAR_GP_PIN(3, 0),
1224 };
1225 static const unsigned int msiof1_rxd_mux[] = {
1226         MSIOF1_RXD_MARK,
1227 };
1228
1229 /* - MSIOF2 ----------------------------------------------------------------- */
1230 static const unsigned int msiof2_clk_pins[] = {
1231         /* SCK */
1232         RCAR_GP_PIN(2, 0),
1233 };
1234 static const unsigned int msiof2_clk_mux[] = {
1235         MSIOF2_SCK_MARK,
1236 };
1237 static const unsigned int msiof2_sync_pins[] = {
1238         /* SYNC */
1239         RCAR_GP_PIN(2, 3),
1240 };
1241 static const unsigned int msiof2_sync_mux[] = {
1242         MSIOF2_SYNC_MARK,
1243 };
1244 static const unsigned int msiof2_ss1_pins[] = {
1245         /* SS1 */
1246         RCAR_GP_PIN(2, 4),
1247 };
1248 static const unsigned int msiof2_ss1_mux[] = {
1249         MSIOF2_SS1_MARK,
1250 };
1251 static const unsigned int msiof2_ss2_pins[] = {
1252         /* SS2 */
1253         RCAR_GP_PIN(2, 5),
1254 };
1255 static const unsigned int msiof2_ss2_mux[] = {
1256         MSIOF2_SS2_MARK,
1257 };
1258 static const unsigned int msiof2_txd_pins[] = {
1259         /* TXD */
1260         RCAR_GP_PIN(2, 2),
1261 };
1262 static const unsigned int msiof2_txd_mux[] = {
1263         MSIOF2_TXD_MARK,
1264 };
1265 static const unsigned int msiof2_rxd_pins[] = {
1266         /* RXD */
1267         RCAR_GP_PIN(2, 1),
1268 };
1269 static const unsigned int msiof2_rxd_mux[] = {
1270         MSIOF2_RXD_MARK,
1271 };
1272
1273 /* - MSIOF3 ----------------------------------------------------------------- */
1274 static const unsigned int msiof3_clk_pins[] = {
1275         /* SCK */
1276         RCAR_GP_PIN(0, 20),
1277 };
1278 static const unsigned int msiof3_clk_mux[] = {
1279         MSIOF3_SCK_MARK,
1280 };
1281 static const unsigned int msiof3_sync_pins[] = {
1282         /* SYNC */
1283         RCAR_GP_PIN(0, 21),
1284 };
1285 static const unsigned int msiof3_sync_mux[] = {
1286         MSIOF3_SYNC_MARK,
1287 };
1288 static const unsigned int msiof3_ss1_pins[] = {
1289         /* SS1 */
1290         RCAR_GP_PIN(0, 6),
1291 };
1292 static const unsigned int msiof3_ss1_mux[] = {
1293         MSIOF3_SS1_MARK,
1294 };
1295 static const unsigned int msiof3_ss2_pins[] = {
1296         /* SS2 */
1297         RCAR_GP_PIN(0, 7),
1298 };
1299 static const unsigned int msiof3_ss2_mux[] = {
1300         MSIOF3_SS2_MARK,
1301 };
1302 static const unsigned int msiof3_txd_pins[] = {
1303         /* TXD */
1304         RCAR_GP_PIN(0, 5),
1305 };
1306 static const unsigned int msiof3_txd_mux[] = {
1307         MSIOF3_TXD_MARK,
1308 };
1309 static const unsigned int msiof3_rxd_pins[] = {
1310         /* RXD */
1311         RCAR_GP_PIN(0, 4),
1312 };
1313 static const unsigned int msiof3_rxd_mux[] = {
1314         MSIOF3_RXD_MARK,
1315 };
1316
1317 /* - PWM0 ------------------------------------------------------------------- */
1318 static const unsigned int pwm0_a_pins[] = {
1319         RCAR_GP_PIN(2, 12),
1320 };
1321 static const unsigned int pwm0_a_mux[] = {
1322         PWM0_A_MARK,
1323 };
1324 static const unsigned int pwm0_b_pins[] = {
1325         RCAR_GP_PIN(1, 21),
1326 };
1327 static const unsigned int pwm0_b_mux[] = {
1328         PWM0_B_MARK,
1329 };
1330
1331 /* - PWM1 ------------------------------------------------------------------- */
1332 static const unsigned int pwm1_a_pins[] = {
1333         RCAR_GP_PIN(2, 13),
1334 };
1335 static const unsigned int pwm1_a_mux[] = {
1336         PWM1_A_MARK,
1337 };
1338 static const unsigned int pwm1_b_pins[] = {
1339         RCAR_GP_PIN(1, 22),
1340 };
1341 static const unsigned int pwm1_b_mux[] = {
1342         PWM1_B_MARK,
1343 };
1344
1345 /* - PWM2 ------------------------------------------------------------------- */
1346 static const unsigned int pwm2_a_pins[] = {
1347         RCAR_GP_PIN(2, 14),
1348 };
1349 static const unsigned int pwm2_a_mux[] = {
1350         PWM2_A_MARK,
1351 };
1352 static const unsigned int pwm2_b_pins[] = {
1353         RCAR_GP_PIN(1, 23),
1354 };
1355 static const unsigned int pwm2_b_mux[] = {
1356         PWM2_B_MARK,
1357 };
1358
1359 /* - PWM3 ------------------------------------------------------------------- */
1360 static const unsigned int pwm3_a_pins[] = {
1361         RCAR_GP_PIN(2, 15),
1362 };
1363 static const unsigned int pwm3_a_mux[] = {
1364         PWM3_A_MARK,
1365 };
1366 static const unsigned int pwm3_b_pins[] = {
1367         RCAR_GP_PIN(1, 24),
1368 };
1369 static const unsigned int pwm3_b_mux[] = {
1370         PWM3_B_MARK,
1371 };
1372
1373 /* - PWM4 ------------------------------------------------------------------- */
1374 static const unsigned int pwm4_a_pins[] = {
1375         RCAR_GP_PIN(2, 16),
1376 };
1377 static const unsigned int pwm4_a_mux[] = {
1378         PWM4_A_MARK,
1379 };
1380 static const unsigned int pwm4_b_pins[] = {
1381         RCAR_GP_PIN(1, 25),
1382 };
1383 static const unsigned int pwm4_b_mux[] = {
1384         PWM4_B_MARK,
1385 };
1386
1387 /* - QSPI0 ------------------------------------------------------------------ */
1388 static const unsigned int qspi0_ctrl_pins[] = {
1389         /* SPCLK, SSL */
1390         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1391 };
1392 static const unsigned int qspi0_ctrl_mux[] = {
1393         QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1394 };
1395 static const unsigned int qspi0_data2_pins[] = {
1396         /* MOSI_IO0, MISO_IO1 */
1397         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1398 };
1399 static const unsigned int qspi0_data2_mux[] = {
1400         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1401 };
1402 static const unsigned int qspi0_data4_pins[] = {
1403         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1404         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1405         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1406 };
1407 static const unsigned int qspi0_data4_mux[] = {
1408         QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1409         QSPI0_IO2_MARK, QSPI0_IO3_MARK
1410 };
1411
1412 /* - QSPI1 ------------------------------------------------------------------ */
1413 static const unsigned int qspi1_ctrl_pins[] = {
1414         /* SPCLK, SSL */
1415         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1416 };
1417 static const unsigned int qspi1_ctrl_mux[] = {
1418         QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1419 };
1420 static const unsigned int qspi1_data2_pins[] = {
1421         /* MOSI_IO0, MISO_IO1 */
1422         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1423 };
1424 static const unsigned int qspi1_data2_mux[] = {
1425         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1426 };
1427 static const unsigned int qspi1_data4_pins[] = {
1428         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1429         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1430         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1431 };
1432 static const unsigned int qspi1_data4_mux[] = {
1433         QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1434         QSPI1_IO2_MARK, QSPI1_IO3_MARK
1435 };
1436
1437 /* - SCIF Clock ------------------------------------------------------------- */
1438 static const unsigned int scif_clk_a_pins[] = {
1439         /* SCIF_CLK */
1440         RCAR_GP_PIN(0, 18),
1441 };
1442 static const unsigned int scif_clk_a_mux[] = {
1443         SCIF_CLK_A_MARK,
1444 };
1445 static const unsigned int scif_clk_b_pins[] = {
1446         /* SCIF_CLK */
1447         RCAR_GP_PIN(1, 25),
1448 };
1449 static const unsigned int scif_clk_b_mux[] = {
1450         SCIF_CLK_B_MARK,
1451 };
1452
1453 /* - SCIF0 ------------------------------------------------------------------ */
1454 static const unsigned int scif0_data_pins[] = {
1455         /* RX, TX */
1456         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1457 };
1458 static const unsigned int scif0_data_mux[] = {
1459         RX0_MARK, TX0_MARK,
1460 };
1461 static const unsigned int scif0_clk_pins[] = {
1462         /* SCK */
1463         RCAR_GP_PIN(4, 1),
1464 };
1465 static const unsigned int scif0_clk_mux[] = {
1466         SCK0_MARK,
1467 };
1468 static const unsigned int scif0_ctrl_pins[] = {
1469         /* RTS#, CTS# */
1470         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1471 };
1472 static const unsigned int scif0_ctrl_mux[] = {
1473         RTS0_N_TANS_MARK, CTS0_N_MARK,
1474 };
1475
1476 /* - SCIF1 ------------------------------------------------------------------ */
1477 static const unsigned int scif1_data_a_pins[] = {
1478         /* RX, TX */
1479         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1480 };
1481 static const unsigned int scif1_data_a_mux[] = {
1482         RX1_A_MARK, TX1_A_MARK,
1483 };
1484 static const unsigned int scif1_clk_pins[] = {
1485         /* SCK */
1486         RCAR_GP_PIN(2, 5),
1487 };
1488 static const unsigned int scif1_clk_mux[] = {
1489         SCK1_MARK,
1490 };
1491 static const unsigned int scif1_ctrl_pins[] = {
1492         /* RTS#, CTS# */
1493         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1494 };
1495 static const unsigned int scif1_ctrl_mux[] = {
1496         RTS1_N_TANS_MARK, CTS1_N_MARK,
1497 };
1498 static const unsigned int scif1_data_b_pins[] = {
1499         /* RX, TX */
1500         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1501 };
1502 static const unsigned int scif1_data_b_mux[] = {
1503         RX1_B_MARK, TX1_B_MARK,
1504 };
1505
1506 /* - SCIF3 ------------------------------------------------------------------ */
1507 static const unsigned int scif3_data_pins[] = {
1508         /* RX, TX */
1509         RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1510 };
1511 static const unsigned int scif3_data_mux[] = {
1512         RX3_MARK, TX3_MARK,
1513 };
1514 static const unsigned int scif3_clk_pins[] = {
1515         /* SCK */
1516         RCAR_GP_PIN(2, 0),
1517 };
1518 static const unsigned int scif3_clk_mux[] = {
1519         SCK3_MARK,
1520 };
1521 static const unsigned int scif3_ctrl_pins[] = {
1522         /* RTS#, CTS# */
1523         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1524 };
1525 static const unsigned int scif3_ctrl_mux[] = {
1526         RTS3_N_TANS_MARK, CTS3_N_MARK,
1527 };
1528
1529 /* - SCIF4 ------------------------------------------------------------------ */
1530 static const unsigned int scif4_data_pins[] = {
1531         /* RX, TX */
1532         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1533 };
1534 static const unsigned int scif4_data_mux[] = {
1535         RX4_MARK, TX4_MARK,
1536 };
1537 static const unsigned int scif4_clk_pins[] = {
1538         /* SCK */
1539         RCAR_GP_PIN(3, 9),
1540 };
1541 static const unsigned int scif4_clk_mux[] = {
1542         SCK4_MARK,
1543 };
1544 static const unsigned int scif4_ctrl_pins[] = {
1545         /* RTS#, CTS# */
1546         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1547 };
1548 static const unsigned int scif4_ctrl_mux[] = {
1549         RTS4_N_TANS_MARK, CTS4_N_MARK,
1550 };
1551
1552 /* - TMU -------------------------------------------------------------------- */
1553 static const unsigned int tmu_tclk1_a_pins[] = {
1554         /* TCLK1 */
1555         RCAR_GP_PIN(4, 4),
1556 };
1557 static const unsigned int tmu_tclk1_a_mux[] = {
1558         TCLK1_A_MARK,
1559 };
1560 static const unsigned int tmu_tclk1_b_pins[] = {
1561         /* TCLK1 */
1562         RCAR_GP_PIN(1, 23),
1563 };
1564 static const unsigned int tmu_tclk1_b_mux[] = {
1565         TCLK1_B_MARK,
1566 };
1567 static const unsigned int tmu_tclk2_a_pins[] = {
1568         /* TCLK2 */
1569         RCAR_GP_PIN(4, 5),
1570 };
1571 static const unsigned int tmu_tclk2_a_mux[] = {
1572         TCLK2_A_MARK,
1573 };
1574 static const unsigned int tmu_tclk2_b_pins[] = {
1575         /* TCLK2 */
1576         RCAR_GP_PIN(1, 24),
1577 };
1578 static const unsigned int tmu_tclk2_b_mux[] = {
1579         TCLK2_B_MARK,
1580 };
1581
1582 /* - VIN0 ------------------------------------------------------------------- */
1583 static const union vin_data12 vin0_data_pins = {
1584         .data12 = {
1585                 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1586                 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1587                 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1588                 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1589                 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1590                 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1591         },
1592 };
1593 static const union vin_data12 vin0_data_mux = {
1594         .data12 = {
1595                 VI0_DATA0_MARK, VI0_DATA1_MARK,
1596                 VI0_DATA2_MARK, VI0_DATA3_MARK,
1597                 VI0_DATA4_MARK, VI0_DATA5_MARK,
1598                 VI0_DATA6_MARK, VI0_DATA7_MARK,
1599                 VI0_DATA8_MARK,  VI0_DATA9_MARK,
1600                 VI0_DATA10_MARK, VI0_DATA11_MARK,
1601         },
1602 };
1603 static const unsigned int vin0_sync_pins[] = {
1604         /* HSYNC#, VSYNC# */
1605         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1606 };
1607 static const unsigned int vin0_sync_mux[] = {
1608         VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1609 };
1610 static const unsigned int vin0_field_pins[] = {
1611         /* FIELD */
1612         RCAR_GP_PIN(2, 16),
1613 };
1614 static const unsigned int vin0_field_mux[] = {
1615         VI0_FIELD_MARK,
1616 };
1617 static const unsigned int vin0_clkenb_pins[] = {
1618         /* CLKENB */
1619         RCAR_GP_PIN(2, 1),
1620 };
1621 static const unsigned int vin0_clkenb_mux[] = {
1622         VI0_CLKENB_MARK,
1623 };
1624 static const unsigned int vin0_clk_pins[] = {
1625         /* CLK */
1626         RCAR_GP_PIN(2, 0),
1627 };
1628 static const unsigned int vin0_clk_mux[] = {
1629         VI0_CLK_MARK,
1630 };
1631
1632 /* - VIN1 ------------------------------------------------------------------- */
1633 static const union vin_data12 vin1_data_pins = {
1634         .data12 = {
1635                 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1636                 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1637                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1638                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1639                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1640                 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1641         },
1642 };
1643 static const union vin_data12 vin1_data_mux = {
1644         .data12 = {
1645                 VI1_DATA0_MARK, VI1_DATA1_MARK,
1646                 VI1_DATA2_MARK, VI1_DATA3_MARK,
1647                 VI1_DATA4_MARK, VI1_DATA5_MARK,
1648                 VI1_DATA6_MARK, VI1_DATA7_MARK,
1649                 VI1_DATA8_MARK,  VI1_DATA9_MARK,
1650                 VI1_DATA10_MARK, VI1_DATA11_MARK,
1651         },
1652 };
1653 static const unsigned int vin1_sync_pins[] = {
1654         /* HSYNC#, VSYNC# */
1655         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1656 };
1657 static const unsigned int vin1_sync_mux[] = {
1658         VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1659 };
1660 static const unsigned int vin1_field_pins[] = {
1661         RCAR_GP_PIN(3, 16),
1662 };
1663 static const unsigned int vin1_field_mux[] = {
1664         /* FIELD */
1665         VI1_FIELD_MARK,
1666 };
1667 static const unsigned int vin1_clkenb_pins[] = {
1668         RCAR_GP_PIN(3, 1),
1669 };
1670 static const unsigned int vin1_clkenb_mux[] = {
1671         /* CLKENB */
1672         VI1_CLKENB_MARK,
1673 };
1674 static const unsigned int vin1_clk_pins[] = {
1675         RCAR_GP_PIN(3, 0),
1676 };
1677 static const unsigned int vin1_clk_mux[] = {
1678         /* CLK */
1679         VI1_CLK_MARK,
1680 };
1681
1682 static const struct sh_pfc_pin_group pinmux_groups[] = {
1683         SH_PFC_PIN_GROUP(avb0_link),
1684         SH_PFC_PIN_GROUP(avb0_magic),
1685         SH_PFC_PIN_GROUP(avb0_phy_int),
1686         SH_PFC_PIN_GROUP(avb0_mdio),
1687         SH_PFC_PIN_GROUP(avb0_rgmii),
1688         SH_PFC_PIN_GROUP(avb0_txcrefclk),
1689         SH_PFC_PIN_GROUP(avb0_avtp_pps),
1690         SH_PFC_PIN_GROUP(avb0_avtp_capture),
1691         SH_PFC_PIN_GROUP(avb0_avtp_match),
1692         SH_PFC_PIN_GROUP(canfd_clk_a),
1693         SH_PFC_PIN_GROUP(canfd_clk_b),
1694         SH_PFC_PIN_GROUP(canfd0_data_a),
1695         SH_PFC_PIN_GROUP(canfd0_data_b),
1696         SH_PFC_PIN_GROUP(canfd1_data),
1697         SH_PFC_PIN_GROUP(du_rgb666),
1698         SH_PFC_PIN_GROUP(du_clk_out),
1699         SH_PFC_PIN_GROUP(du_sync),
1700         SH_PFC_PIN_GROUP(du_oddf),
1701         SH_PFC_PIN_GROUP(du_cde),
1702         SH_PFC_PIN_GROUP(du_disp),
1703         SH_PFC_PIN_GROUP(hscif0_data),
1704         SH_PFC_PIN_GROUP(hscif0_clk),
1705         SH_PFC_PIN_GROUP(hscif0_ctrl),
1706         SH_PFC_PIN_GROUP(hscif1_data),
1707         SH_PFC_PIN_GROUP(hscif1_clk),
1708         SH_PFC_PIN_GROUP(hscif1_ctrl),
1709         SH_PFC_PIN_GROUP(hscif2_data),
1710         SH_PFC_PIN_GROUP(hscif2_clk),
1711         SH_PFC_PIN_GROUP(hscif2_ctrl),
1712         SH_PFC_PIN_GROUP(hscif3_data),
1713         SH_PFC_PIN_GROUP(hscif3_clk),
1714         SH_PFC_PIN_GROUP(hscif3_ctrl),
1715         SH_PFC_PIN_GROUP(i2c0),
1716         SH_PFC_PIN_GROUP(i2c1),
1717         SH_PFC_PIN_GROUP(i2c2),
1718         SH_PFC_PIN_GROUP(i2c3_a),
1719         SH_PFC_PIN_GROUP(i2c3_b),
1720         SH_PFC_PIN_GROUP(i2c4),
1721         SH_PFC_PIN_GROUP(intc_ex_irq0),
1722         SH_PFC_PIN_GROUP(intc_ex_irq1),
1723         SH_PFC_PIN_GROUP(intc_ex_irq2),
1724         SH_PFC_PIN_GROUP(intc_ex_irq3),
1725         SH_PFC_PIN_GROUP(intc_ex_irq4),
1726         SH_PFC_PIN_GROUP(intc_ex_irq5),
1727         SH_PFC_PIN_GROUP(mmc_data1),
1728         SH_PFC_PIN_GROUP(mmc_data4),
1729         SH_PFC_PIN_GROUP(mmc_data8),
1730         SH_PFC_PIN_GROUP(mmc_ctrl),
1731         SH_PFC_PIN_GROUP(mmc_cd),
1732         SH_PFC_PIN_GROUP(mmc_wp),
1733         SH_PFC_PIN_GROUP(msiof0_clk),
1734         SH_PFC_PIN_GROUP(msiof0_sync),
1735         SH_PFC_PIN_GROUP(msiof0_ss1),
1736         SH_PFC_PIN_GROUP(msiof0_ss2),
1737         SH_PFC_PIN_GROUP(msiof0_txd),
1738         SH_PFC_PIN_GROUP(msiof0_rxd),
1739         SH_PFC_PIN_GROUP(msiof1_clk),
1740         SH_PFC_PIN_GROUP(msiof1_sync),
1741         SH_PFC_PIN_GROUP(msiof1_ss1),
1742         SH_PFC_PIN_GROUP(msiof1_ss2),
1743         SH_PFC_PIN_GROUP(msiof1_txd),
1744         SH_PFC_PIN_GROUP(msiof1_rxd),
1745         SH_PFC_PIN_GROUP(msiof2_clk),
1746         SH_PFC_PIN_GROUP(msiof2_sync),
1747         SH_PFC_PIN_GROUP(msiof2_ss1),
1748         SH_PFC_PIN_GROUP(msiof2_ss2),
1749         SH_PFC_PIN_GROUP(msiof2_txd),
1750         SH_PFC_PIN_GROUP(msiof2_rxd),
1751         SH_PFC_PIN_GROUP(msiof3_clk),
1752         SH_PFC_PIN_GROUP(msiof3_sync),
1753         SH_PFC_PIN_GROUP(msiof3_ss1),
1754         SH_PFC_PIN_GROUP(msiof3_ss2),
1755         SH_PFC_PIN_GROUP(msiof3_txd),
1756         SH_PFC_PIN_GROUP(msiof3_rxd),
1757         SH_PFC_PIN_GROUP(pwm0_a),
1758         SH_PFC_PIN_GROUP(pwm0_b),
1759         SH_PFC_PIN_GROUP(pwm1_a),
1760         SH_PFC_PIN_GROUP(pwm1_b),
1761         SH_PFC_PIN_GROUP(pwm2_a),
1762         SH_PFC_PIN_GROUP(pwm2_b),
1763         SH_PFC_PIN_GROUP(pwm3_a),
1764         SH_PFC_PIN_GROUP(pwm3_b),
1765         SH_PFC_PIN_GROUP(pwm4_a),
1766         SH_PFC_PIN_GROUP(pwm4_b),
1767         SH_PFC_PIN_GROUP(qspi0_ctrl),
1768         SH_PFC_PIN_GROUP(qspi0_data2),
1769         SH_PFC_PIN_GROUP(qspi0_data4),
1770         SH_PFC_PIN_GROUP(qspi1_ctrl),
1771         SH_PFC_PIN_GROUP(qspi1_data2),
1772         SH_PFC_PIN_GROUP(qspi1_data4),
1773         SH_PFC_PIN_GROUP(scif_clk_a),
1774         SH_PFC_PIN_GROUP(scif_clk_b),
1775         SH_PFC_PIN_GROUP(scif0_data),
1776         SH_PFC_PIN_GROUP(scif0_clk),
1777         SH_PFC_PIN_GROUP(scif0_ctrl),
1778         SH_PFC_PIN_GROUP(scif1_data_a),
1779         SH_PFC_PIN_GROUP(scif1_clk),
1780         SH_PFC_PIN_GROUP(scif1_ctrl),
1781         SH_PFC_PIN_GROUP(scif1_data_b),
1782         SH_PFC_PIN_GROUP(scif3_data),
1783         SH_PFC_PIN_GROUP(scif3_clk),
1784         SH_PFC_PIN_GROUP(scif3_ctrl),
1785         SH_PFC_PIN_GROUP(scif4_data),
1786         SH_PFC_PIN_GROUP(scif4_clk),
1787         SH_PFC_PIN_GROUP(scif4_ctrl),
1788         SH_PFC_PIN_GROUP(tmu_tclk1_a),
1789         SH_PFC_PIN_GROUP(tmu_tclk1_b),
1790         SH_PFC_PIN_GROUP(tmu_tclk2_a),
1791         SH_PFC_PIN_GROUP(tmu_tclk2_b),
1792         VIN_DATA_PIN_GROUP(vin0_data, 8),
1793         VIN_DATA_PIN_GROUP(vin0_data, 10),
1794         VIN_DATA_PIN_GROUP(vin0_data, 12),
1795         SH_PFC_PIN_GROUP(vin0_sync),
1796         SH_PFC_PIN_GROUP(vin0_field),
1797         SH_PFC_PIN_GROUP(vin0_clkenb),
1798         SH_PFC_PIN_GROUP(vin0_clk),
1799         VIN_DATA_PIN_GROUP(vin1_data, 8),
1800         VIN_DATA_PIN_GROUP(vin1_data, 10),
1801         VIN_DATA_PIN_GROUP(vin1_data, 12),
1802         SH_PFC_PIN_GROUP(vin1_sync),
1803         SH_PFC_PIN_GROUP(vin1_field),
1804         SH_PFC_PIN_GROUP(vin1_clkenb),
1805         SH_PFC_PIN_GROUP(vin1_clk),
1806 };
1807
1808 static const char * const avb0_groups[] = {
1809         "avb0_link",
1810         "avb0_magic",
1811         "avb0_phy_int",
1812         "avb0_mdio",
1813         "avb0_rgmii",
1814         "avb0_txcrefclk",
1815         "avb0_avtp_pps",
1816         "avb0_avtp_capture",
1817         "avb0_avtp_match",
1818 };
1819
1820 static const char * const canfd_clk_groups[] = {
1821         "canfd_clk_a",
1822         "canfd_clk_b",
1823 };
1824
1825 static const char * const canfd0_groups[] = {
1826         "canfd0_data_a",
1827         "canfd0_data_b",
1828 };
1829
1830 static const char * const canfd1_groups[] = {
1831         "canfd1_data",
1832 };
1833
1834 static const char * const du_groups[] = {
1835         "du_rgb666",
1836         "du_clk_out",
1837         "du_sync",
1838         "du_oddf",
1839         "du_cde",
1840         "du_disp",
1841 };
1842
1843 static const char * const hscif0_groups[] = {
1844         "hscif0_data",
1845         "hscif0_clk",
1846         "hscif0_ctrl",
1847 };
1848
1849 static const char * const hscif1_groups[] = {
1850         "hscif1_data",
1851         "hscif1_clk",
1852         "hscif1_ctrl",
1853 };
1854
1855 static const char * const hscif2_groups[] = {
1856         "hscif2_data",
1857         "hscif2_clk",
1858         "hscif2_ctrl",
1859 };
1860
1861 static const char * const hscif3_groups[] = {
1862         "hscif3_data",
1863         "hscif3_clk",
1864         "hscif3_ctrl",
1865 };
1866
1867 static const char * const i2c0_groups[] = {
1868         "i2c0",
1869 };
1870
1871 static const char * const i2c1_groups[] = {
1872         "i2c1",
1873 };
1874
1875 static const char * const i2c2_groups[] = {
1876         "i2c2",
1877 };
1878
1879 static const char * const i2c3_groups[] = {
1880         "i2c3_a",
1881         "i2c3_b",
1882 };
1883
1884 static const char * const i2c4_groups[] = {
1885         "i2c4",
1886 };
1887
1888 static const char * const intc_ex_groups[] = {
1889         "intc_ex_irq0",
1890         "intc_ex_irq1",
1891         "intc_ex_irq2",
1892         "intc_ex_irq3",
1893         "intc_ex_irq4",
1894         "intc_ex_irq5",
1895 };
1896
1897 static const char * const mmc_groups[] = {
1898         "mmc_data1",
1899         "mmc_data4",
1900         "mmc_data8",
1901         "mmc_ctrl",
1902         "mmc_cd",
1903         "mmc_wp",
1904 };
1905
1906 static const char * const msiof0_groups[] = {
1907         "msiof0_clk",
1908         "msiof0_sync",
1909         "msiof0_ss1",
1910         "msiof0_ss2",
1911         "msiof0_txd",
1912         "msiof0_rxd",
1913 };
1914
1915 static const char * const msiof1_groups[] = {
1916         "msiof1_clk",
1917         "msiof1_sync",
1918         "msiof1_ss1",
1919         "msiof1_ss2",
1920         "msiof1_txd",
1921         "msiof1_rxd",
1922 };
1923
1924 static const char * const msiof2_groups[] = {
1925         "msiof2_clk",
1926         "msiof2_sync",
1927         "msiof2_ss1",
1928         "msiof2_ss2",
1929         "msiof2_txd",
1930         "msiof2_rxd",
1931 };
1932
1933 static const char * const msiof3_groups[] = {
1934         "msiof3_clk",
1935         "msiof3_sync",
1936         "msiof3_ss1",
1937         "msiof3_ss2",
1938         "msiof3_txd",
1939         "msiof3_rxd",
1940 };
1941
1942 static const char * const pwm0_groups[] = {
1943         "pwm0_a",
1944         "pwm0_b",
1945 };
1946
1947 static const char * const pwm1_groups[] = {
1948         "pwm1_a",
1949         "pwm1_b",
1950 };
1951
1952 static const char * const pwm2_groups[] = {
1953         "pwm2_a",
1954         "pwm2_b",
1955 };
1956
1957 static const char * const pwm3_groups[] = {
1958         "pwm3_a",
1959         "pwm3_b",
1960 };
1961
1962 static const char * const pwm4_groups[] = {
1963         "pwm4_a",
1964         "pwm4_b",
1965 };
1966
1967 static const char * const qspi0_groups[] = {
1968         "qspi0_ctrl",
1969         "qspi0_data2",
1970         "qspi0_data4",
1971 };
1972
1973 static const char * const qspi1_groups[] = {
1974         "qspi1_ctrl",
1975         "qspi1_data2",
1976         "qspi1_data4",
1977 };
1978
1979 static const char * const scif_clk_groups[] = {
1980         "scif_clk_a",
1981         "scif_clk_b",
1982 };
1983
1984 static const char * const scif0_groups[] = {
1985         "scif0_data",
1986         "scif0_clk",
1987         "scif0_ctrl",
1988 };
1989
1990 static const char * const scif1_groups[] = {
1991         "scif1_data_a",
1992         "scif1_clk",
1993         "scif1_ctrl",
1994         "scif1_data_b",
1995 };
1996
1997 static const char * const scif3_groups[] = {
1998         "scif3_data",
1999         "scif3_clk",
2000         "scif3_ctrl",
2001 };
2002
2003 static const char * const scif4_groups[] = {
2004         "scif4_data",
2005         "scif4_clk",
2006         "scif4_ctrl",
2007 };
2008
2009 static const char * const tmu_groups[] = {
2010         "tmu_tclk1_a",
2011         "tmu_tclk1_b",
2012         "tmu_tclk2_a",
2013         "tmu_tclk2_b",
2014 };
2015
2016 static const char * const vin0_groups[] = {
2017         "vin0_data8",
2018         "vin0_data10",
2019         "vin0_data12",
2020         "vin0_sync",
2021         "vin0_field",
2022         "vin0_clkenb",
2023         "vin0_clk",
2024 };
2025
2026 static const char * const vin1_groups[] = {
2027         "vin1_data8",
2028         "vin1_data10",
2029         "vin1_data12",
2030         "vin1_sync",
2031         "vin1_field",
2032         "vin1_clkenb",
2033         "vin1_clk",
2034 };
2035
2036 static const struct sh_pfc_function pinmux_functions[] = {
2037         SH_PFC_FUNCTION(avb0),
2038         SH_PFC_FUNCTION(canfd_clk),
2039         SH_PFC_FUNCTION(canfd0),
2040         SH_PFC_FUNCTION(canfd1),
2041         SH_PFC_FUNCTION(du),
2042         SH_PFC_FUNCTION(hscif0),
2043         SH_PFC_FUNCTION(hscif1),
2044         SH_PFC_FUNCTION(hscif2),
2045         SH_PFC_FUNCTION(hscif3),
2046         SH_PFC_FUNCTION(i2c0),
2047         SH_PFC_FUNCTION(i2c1),
2048         SH_PFC_FUNCTION(i2c2),
2049         SH_PFC_FUNCTION(i2c3),
2050         SH_PFC_FUNCTION(i2c4),
2051         SH_PFC_FUNCTION(intc_ex),
2052         SH_PFC_FUNCTION(mmc),
2053         SH_PFC_FUNCTION(msiof0),
2054         SH_PFC_FUNCTION(msiof1),
2055         SH_PFC_FUNCTION(msiof2),
2056         SH_PFC_FUNCTION(msiof3),
2057         SH_PFC_FUNCTION(pwm0),
2058         SH_PFC_FUNCTION(pwm1),
2059         SH_PFC_FUNCTION(pwm2),
2060         SH_PFC_FUNCTION(pwm3),
2061         SH_PFC_FUNCTION(pwm4),
2062         SH_PFC_FUNCTION(qspi0),
2063         SH_PFC_FUNCTION(qspi1),
2064         SH_PFC_FUNCTION(scif_clk),
2065         SH_PFC_FUNCTION(scif0),
2066         SH_PFC_FUNCTION(scif1),
2067         SH_PFC_FUNCTION(scif3),
2068         SH_PFC_FUNCTION(scif4),
2069         SH_PFC_FUNCTION(tmu),
2070         SH_PFC_FUNCTION(vin0),
2071         SH_PFC_FUNCTION(vin1),
2072 };
2073
2074 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2075 #define F_(x, y)        FN_##y
2076 #define FM(x)           FN_##x
2077         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2078                 0, 0,
2079                 0, 0,
2080                 0, 0,
2081                 0, 0,
2082                 0, 0,
2083                 0, 0,
2084                 0, 0,
2085                 0, 0,
2086                 0, 0,
2087                 0, 0,
2088                 GP_0_21_FN,     GPSR0_21,
2089                 GP_0_20_FN,     GPSR0_20,
2090                 GP_0_19_FN,     GPSR0_19,
2091                 GP_0_18_FN,     GPSR0_18,
2092                 GP_0_17_FN,     GPSR0_17,
2093                 GP_0_16_FN,     GPSR0_16,
2094                 GP_0_15_FN,     GPSR0_15,
2095                 GP_0_14_FN,     GPSR0_14,
2096                 GP_0_13_FN,     GPSR0_13,
2097                 GP_0_12_FN,     GPSR0_12,
2098                 GP_0_11_FN,     GPSR0_11,
2099                 GP_0_10_FN,     GPSR0_10,
2100                 GP_0_9_FN,      GPSR0_9,
2101                 GP_0_8_FN,      GPSR0_8,
2102                 GP_0_7_FN,      GPSR0_7,
2103                 GP_0_6_FN,      GPSR0_6,
2104                 GP_0_5_FN,      GPSR0_5,
2105                 GP_0_4_FN,      GPSR0_4,
2106                 GP_0_3_FN,      GPSR0_3,
2107                 GP_0_2_FN,      GPSR0_2,
2108                 GP_0_1_FN,      GPSR0_1,
2109                 GP_0_0_FN,      GPSR0_0, }
2110         },
2111         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2112                 0, 0,
2113                 0, 0,
2114                 0, 0,
2115                 0, 0,
2116                 GP_1_27_FN,     GPSR1_27,
2117                 GP_1_26_FN,     GPSR1_26,
2118                 GP_1_25_FN,     GPSR1_25,
2119                 GP_1_24_FN,     GPSR1_24,
2120                 GP_1_23_FN,     GPSR1_23,
2121                 GP_1_22_FN,     GPSR1_22,
2122                 GP_1_21_FN,     GPSR1_21,
2123                 GP_1_20_FN,     GPSR1_20,
2124                 GP_1_19_FN,     GPSR1_19,
2125                 GP_1_18_FN,     GPSR1_18,
2126                 GP_1_17_FN,     GPSR1_17,
2127                 GP_1_16_FN,     GPSR1_16,
2128                 GP_1_15_FN,     GPSR1_15,
2129                 GP_1_14_FN,     GPSR1_14,
2130                 GP_1_13_FN,     GPSR1_13,
2131                 GP_1_12_FN,     GPSR1_12,
2132                 GP_1_11_FN,     GPSR1_11,
2133                 GP_1_10_FN,     GPSR1_10,
2134                 GP_1_9_FN,      GPSR1_9,
2135                 GP_1_8_FN,      GPSR1_8,
2136                 GP_1_7_FN,      GPSR1_7,
2137                 GP_1_6_FN,      GPSR1_6,
2138                 GP_1_5_FN,      GPSR1_5,
2139                 GP_1_4_FN,      GPSR1_4,
2140                 GP_1_3_FN,      GPSR1_3,
2141                 GP_1_2_FN,      GPSR1_2,
2142                 GP_1_1_FN,      GPSR1_1,
2143                 GP_1_0_FN,      GPSR1_0, }
2144         },
2145         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2146                 0, 0,
2147                 0, 0,
2148                 0, 0,
2149                 0, 0,
2150                 0, 0,
2151                 0, 0,
2152                 0, 0,
2153                 0, 0,
2154                 0, 0,
2155                 0, 0,
2156                 0, 0,
2157                 0, 0,
2158                 0, 0,
2159                 0, 0,
2160                 0, 0,
2161                 GP_2_16_FN,     GPSR2_16,
2162                 GP_2_15_FN,     GPSR2_15,
2163                 GP_2_14_FN,     GPSR2_14,
2164                 GP_2_13_FN,     GPSR2_13,
2165                 GP_2_12_FN,     GPSR2_12,
2166                 GP_2_11_FN,     GPSR2_11,
2167                 GP_2_10_FN,     GPSR2_10,
2168                 GP_2_9_FN,      GPSR2_9,
2169                 GP_2_8_FN,      GPSR2_8,
2170                 GP_2_7_FN,      GPSR2_7,
2171                 GP_2_6_FN,      GPSR2_6,
2172                 GP_2_5_FN,      GPSR2_5,
2173                 GP_2_4_FN,      GPSR2_4,
2174                 GP_2_3_FN,      GPSR2_3,
2175                 GP_2_2_FN,      GPSR2_2,
2176                 GP_2_1_FN,      GPSR2_1,
2177                 GP_2_0_FN,      GPSR2_0, }
2178         },
2179         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2180                 0, 0,
2181                 0, 0,
2182                 0, 0,
2183                 0, 0,
2184                 0, 0,
2185                 0, 0,
2186                 0, 0,
2187                 0, 0,
2188                 0, 0,
2189                 0, 0,
2190                 0, 0,
2191                 0, 0,
2192                 0, 0,
2193                 0, 0,
2194                 0, 0,
2195                 GP_3_16_FN,     GPSR3_16,
2196                 GP_3_15_FN,     GPSR3_15,
2197                 GP_3_14_FN,     GPSR3_14,
2198                 GP_3_13_FN,     GPSR3_13,
2199                 GP_3_12_FN,     GPSR3_12,
2200                 GP_3_11_FN,     GPSR3_11,
2201                 GP_3_10_FN,     GPSR3_10,
2202                 GP_3_9_FN,      GPSR3_9,
2203                 GP_3_8_FN,      GPSR3_8,
2204                 GP_3_7_FN,      GPSR3_7,
2205                 GP_3_6_FN,      GPSR3_6,
2206                 GP_3_5_FN,      GPSR3_5,
2207                 GP_3_4_FN,      GPSR3_4,
2208                 GP_3_3_FN,      GPSR3_3,
2209                 GP_3_2_FN,      GPSR3_2,
2210                 GP_3_1_FN,      GPSR3_1,
2211                 GP_3_0_FN,      GPSR3_0, }
2212         },
2213         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2214                 0, 0,
2215                 0, 0,
2216                 0, 0,
2217                 0, 0,
2218                 0, 0,
2219                 0, 0,
2220                 0, 0,
2221                 0, 0,
2222                 0, 0,
2223                 0, 0,
2224                 0, 0,
2225                 0, 0,
2226                 0, 0,
2227                 0, 0,
2228                 0, 0,
2229                 0, 0,
2230                 0, 0,
2231                 0, 0,
2232                 0, 0,
2233                 0, 0,
2234                 0, 0,
2235                 0, 0,
2236                 0, 0,
2237                 0, 0,
2238                 0, 0,
2239                 0, 0,
2240                 GP_4_5_FN,      GPSR4_5,
2241                 GP_4_4_FN,      GPSR4_4,
2242                 GP_4_3_FN,      GPSR4_3,
2243                 GP_4_2_FN,      GPSR4_2,
2244                 GP_4_1_FN,      GPSR4_1,
2245                 GP_4_0_FN,      GPSR4_0, }
2246         },
2247         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2248                 0, 0,
2249                 0, 0,
2250                 0, 0,
2251                 0, 0,
2252                 0, 0,
2253                 0, 0,
2254                 0, 0,
2255                 0, 0,
2256                 0, 0,
2257                 0, 0,
2258                 0, 0,
2259                 0, 0,
2260                 0, 0,
2261                 0, 0,
2262                 0, 0,
2263                 0, 0,
2264                 0, 0,
2265                 GP_5_14_FN,     GPSR5_14,
2266                 GP_5_13_FN,     GPSR5_13,
2267                 GP_5_12_FN,     GPSR5_12,
2268                 GP_5_11_FN,     GPSR5_11,
2269                 GP_5_10_FN,     GPSR5_10,
2270                 GP_5_9_FN,      GPSR5_9,
2271                 GP_5_8_FN,      GPSR5_8,
2272                 GP_5_7_FN,      GPSR5_7,
2273                 GP_5_6_FN,      GPSR5_6,
2274                 GP_5_5_FN,      GPSR5_5,
2275                 GP_5_4_FN,      GPSR5_4,
2276                 GP_5_3_FN,      GPSR5_3,
2277                 GP_5_2_FN,      GPSR5_2,
2278                 GP_5_1_FN,      GPSR5_1,
2279                 GP_5_0_FN,      GPSR5_0, }
2280         },
2281 #undef F_
2282 #undef FM
2283
2284 #define F_(x, y)        x,
2285 #define FM(x)           FN_##x,
2286         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2287                 IP0_31_28
2288                 IP0_27_24
2289                 IP0_23_20
2290                 IP0_19_16
2291                 IP0_15_12
2292                 IP0_11_8
2293                 IP0_7_4
2294                 IP0_3_0 }
2295         },
2296         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2297                 IP1_31_28
2298                 IP1_27_24
2299                 IP1_23_20
2300                 IP1_19_16
2301                 IP1_15_12
2302                 IP1_11_8
2303                 IP1_7_4
2304                 IP1_3_0 }
2305         },
2306         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2307                 IP2_31_28
2308                 IP2_27_24
2309                 IP2_23_20
2310                 IP2_19_16
2311                 IP2_15_12
2312                 IP2_11_8
2313                 IP2_7_4
2314                 IP2_3_0 }
2315         },
2316         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2317                 IP3_31_28
2318                 IP3_27_24
2319                 IP3_23_20
2320                 IP3_19_16
2321                 IP3_15_12
2322                 IP3_11_8
2323                 IP3_7_4
2324                 IP3_3_0 }
2325         },
2326         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2327                 IP4_31_28
2328                 IP4_27_24
2329                 IP4_23_20
2330                 IP4_19_16
2331                 IP4_15_12
2332                 IP4_11_8
2333                 IP4_7_4
2334                 IP4_3_0 }
2335         },
2336         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2337                 IP5_31_28
2338                 IP5_27_24
2339                 IP5_23_20
2340                 IP5_19_16
2341                 IP5_15_12
2342                 IP5_11_8
2343                 IP5_7_4
2344                 IP5_3_0 }
2345         },
2346         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2347                 IP6_31_28
2348                 IP6_27_24
2349                 IP6_23_20
2350                 IP6_19_16
2351                 IP6_15_12
2352                 IP6_11_8
2353                 IP6_7_4
2354                 IP6_3_0 }
2355         },
2356         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2357                 IP7_31_28
2358                 IP7_27_24
2359                 IP7_23_20
2360                 IP7_19_16
2361                 IP7_15_12
2362                 IP7_11_8
2363                 IP7_7_4
2364                 IP7_3_0 }
2365         },
2366         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2367                 IP8_31_28
2368                 IP8_27_24
2369                 IP8_23_20
2370                 IP8_19_16
2371                 IP8_15_12
2372                 IP8_11_8
2373                 IP8_7_4
2374                 IP8_3_0 }
2375         },
2376 #undef F_
2377 #undef FM
2378
2379 #define F_(x, y)        x,
2380 #define FM(x)           FN_##x,
2381         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2382                              4, 4, 4, 4, 4,
2383                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
2384                 /* RESERVED 31, 30, 29, 28 */
2385                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2386                 /* RESERVED 27, 26, 25, 24 */
2387                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2388                 /* RESERVED 23, 22, 21, 20 */
2389                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2390                 /* RESERVED 19, 18, 17, 16 */
2391                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2392                 /* RESERVED 15, 14, 13, 12 */
2393                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2394                 MOD_SEL0_11
2395                 MOD_SEL0_10
2396                 MOD_SEL0_9
2397                 MOD_SEL0_8
2398                 MOD_SEL0_7
2399                 MOD_SEL0_6
2400                 MOD_SEL0_5
2401                 MOD_SEL0_4
2402                 MOD_SEL0_3
2403                 MOD_SEL0_2
2404                 MOD_SEL0_1
2405                 MOD_SEL0_0 }
2406         },
2407         { },
2408 };
2409
2410 enum ioctrl_regs {
2411         IOCTRL30,
2412         IOCTRL31,
2413         IOCTRL32,
2414 };
2415
2416 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2417         [IOCTRL30] = { 0xe6060380 },
2418         [IOCTRL31] = { 0xe6060384 },
2419         [IOCTRL32] = { 0xe6060388 },
2420         { /* sentinel */ },
2421 };
2422
2423 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2424                                    u32 *pocctrl)
2425 {
2426         int bit = pin & 0x1f;
2427
2428         *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
2429         if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2430                 return bit;
2431         if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2432                 return bit + 22;
2433
2434         *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
2435         if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2436                 return bit - 10;
2437         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2438                 return bit + 7;
2439
2440         return -EINVAL;
2441 }
2442
2443 static const struct sh_pfc_soc_operations pinmux_ops = {
2444         .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2445 };
2446
2447 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2448         .name = "r8a77970_pfc",
2449         .ops = &pinmux_ops,
2450         .unlock_reg = 0xe6060000, /* PMMR */
2451
2452         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2453
2454         .pins = pinmux_pins,
2455         .nr_pins = ARRAY_SIZE(pinmux_pins),
2456         .groups = pinmux_groups,
2457         .nr_groups = ARRAY_SIZE(pinmux_groups),
2458         .functions = pinmux_functions,
2459         .nr_functions = ARRAY_SIZE(pinmux_functions),
2460
2461         .cfg_regs = pinmux_config_regs,
2462         .ioctrl_regs = pinmux_ioctrl_regs,
2463
2464         .pinmux_data = pinmux_data,
2465         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2466 };