drivers/pinctrl/renesas/pfc-r8a77965.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A77965 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
   6  * Copyright (C) 2016 Renesas Electronics Corp.
   7  *
   8  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
   9  *
  10  * R-Car Gen3 processor support - PFC hardware block.
  11  *
  12  * Copyright (C) 2015  Renesas Electronics Corporation
  13  */
  14
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/kernel.h>
  20
  21 #include "sh_pfc.h"
  22
  23 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
  24                    SH_PFC_PIN_CFG_PULL_UP | \
  25                    SH_PFC_PIN_CFG_PULL_DOWN)
  26
  27 #define CPU_ALL_PORT(fn, sfx)                                           \
  28         PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
  29         PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
  30         PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
  31         PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  32         PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),       \
  33         PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),       \
  34         PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),       \
  35         PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),       \
  36         PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),      \
  37         PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
  38         PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
  39         PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  40 /*
  41  * F_() : just information
  42  * FM() : macro for FN_xxx / xxx_MARK
  43  */
  44
  45 /* GPSR0 */
  46 #define GPSR0_15        F_(D15,                 IP7_11_8)
  47 #define GPSR0_14        F_(D14,                 IP7_7_4)
  48 #define GPSR0_13        F_(D13,                 IP7_3_0)
  49 #define GPSR0_12        F_(D12,                 IP6_31_28)
  50 #define GPSR0_11        F_(D11,                 IP6_27_24)
  51 #define GPSR0_10        F_(D10,                 IP6_23_20)
  52 #define GPSR0_9         F_(D9,                  IP6_19_16)
  53 #define GPSR0_8         F_(D8,                  IP6_15_12)
  54 #define GPSR0_7         F_(D7,                  IP6_11_8)
  55 #define GPSR0_6         F_(D6,                  IP6_7_4)
  56 #define GPSR0_5         F_(D5,                  IP6_3_0)
  57 #define GPSR0_4         F_(D4,                  IP5_31_28)
  58 #define GPSR0_3         F_(D3,                  IP5_27_24)
  59 #define GPSR0_2         F_(D2,                  IP5_23_20)
  60 #define GPSR0_1         F_(D1,                  IP5_19_16)
  61 #define GPSR0_0         F_(D0,                  IP5_15_12)
  62
  63 /* GPSR1 */
  64 #define GPSR1_28        FM(CLKOUT)
  65 #define GPSR1_27        F_(EX_WAIT0_A,          IP5_11_8)
  66 #define GPSR1_26        F_(WE1_N,               IP5_7_4)
  67 #define GPSR1_25        F_(WE0_N,               IP5_3_0)
  68 #define GPSR1_24        F_(RD_WR_N,             IP4_31_28)
  69 #define GPSR1_23        F_(RD_N,                IP4_27_24)
  70 #define GPSR1_22        F_(BS_N,                IP4_23_20)
  71 #define GPSR1_21        F_(CS1_N,               IP4_19_16)
  72 #define GPSR1_20        F_(CS0_N,               IP4_15_12)
  73 #define GPSR1_19        F_(A19,                 IP4_11_8)
  74 #define GPSR1_18        F_(A18,                 IP4_7_4)
  75 #define GPSR1_17        F_(A17,                 IP4_3_0)
  76 #define GPSR1_16        F_(A16,                 IP3_31_28)
  77 #define GPSR1_15        F_(A15,                 IP3_27_24)
  78 #define GPSR1_14        F_(A14,                 IP3_23_20)
  79 #define GPSR1_13        F_(A13,                 IP3_19_16)
  80 #define GPSR1_12        F_(A12,                 IP3_15_12)
  81 #define GPSR1_11        F_(A11,                 IP3_11_8)
  82 #define GPSR1_10        F_(A10,                 IP3_7_4)
  83 #define GPSR1_9         F_(A9,                  IP3_3_0)
  84 #define GPSR1_8         F_(A8,                  IP2_31_28)
  85 #define GPSR1_7         F_(A7,                  IP2_27_24)
  86 #define GPSR1_6         F_(A6,                  IP2_23_20)
  87 #define GPSR1_5         F_(A5,                  IP2_19_16)
  88 #define GPSR1_4         F_(A4,                  IP2_15_12)
  89 #define GPSR1_3         F_(A3,                  IP2_11_8)
  90 #define GPSR1_2         F_(A2,                  IP2_7_4)
  91 #define GPSR1_1         F_(A1,                  IP2_3_0)
  92 #define GPSR1_0         F_(A0,                  IP1_31_28)
  93
  94 /* GPSR2 */
  95 #define GPSR2_14        F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
  96 #define GPSR2_13        F_(AVB_AVTP_MATCH_A,    IP0_19_16)
  97 #define GPSR2_12        F_(AVB_LINK,            IP0_15_12)
  98 #define GPSR2_11        F_(AVB_PHY_INT,         IP0_11_8)
  99 #define GPSR2_10        F_(AVB_MAGIC,           IP0_7_4)
 100 #define GPSR2_9         F_(AVB_MDC,             IP0_3_0)
 101 #define GPSR2_8         F_(PWM2_A,              IP1_27_24)
 102 #define GPSR2_7         F_(PWM1_A,              IP1_23_20)
 103 #define GPSR2_6         F_(PWM0,                IP1_19_16)
 104 #define GPSR2_5         F_(IRQ5,                IP1_15_12)
 105 #define GPSR2_4         F_(IRQ4,                IP1_11_8)
 106 #define GPSR2_3         F_(IRQ3,                IP1_7_4)
 107 #define GPSR2_2         F_(IRQ2,                IP1_3_0)
 108 #define GPSR2_1         F_(IRQ1,                IP0_31_28)
 109 #define GPSR2_0         F_(IRQ0,                IP0_27_24)
 110
 111 /* GPSR3 */
 112 #define GPSR3_15        F_(SD1_WP,              IP11_23_20)
 113 #define GPSR3_14        F_(SD1_CD,              IP11_19_16)
 114 #define GPSR3_13        F_(SD0_WP,              IP11_15_12)
 115 #define GPSR3_12        F_(SD0_CD,              IP11_11_8)
 116 #define GPSR3_11        F_(SD1_DAT3,            IP8_31_28)
 117 #define GPSR3_10        F_(SD1_DAT2,            IP8_27_24)
 118 #define GPSR3_9         F_(SD1_DAT1,            IP8_23_20)
 119 #define GPSR3_8         F_(SD1_DAT0,            IP8_19_16)
 120 #define GPSR3_7         F_(SD1_CMD,             IP8_15_12)
 121 #define GPSR3_6         F_(SD1_CLK,             IP8_11_8)
 122 #define GPSR3_5         F_(SD0_DAT3,            IP8_7_4)
 123 #define GPSR3_4         F_(SD0_DAT2,            IP8_3_0)
 124 #define GPSR3_3         F_(SD0_DAT1,            IP7_31_28)
 125 #define GPSR3_2         F_(SD0_DAT0,            IP7_27_24)
 126 #define GPSR3_1         F_(SD0_CMD,             IP7_23_20)
 127 #define GPSR3_0         F_(SD0_CLK,             IP7_19_16)
 128
 129 /* GPSR4 */
 130 #define GPSR4_17        F_(SD3_DS,              IP11_7_4)
 131 #define GPSR4_16        F_(SD3_DAT7,            IP11_3_0)
 132 #define GPSR4_15        F_(SD3_DAT6,            IP10_31_28)
 133 #define GPSR4_14        F_(SD3_DAT5,            IP10_27_24)
 134 #define GPSR4_13        F_(SD3_DAT4,            IP10_23_20)
 135 #define GPSR4_12        F_(SD3_DAT3,            IP10_19_16)
 136 #define GPSR4_11        F_(SD3_DAT2,            IP10_15_12)
 137 #define GPSR4_10        F_(SD3_DAT1,            IP10_11_8)
 138 #define GPSR4_9         F_(SD3_DAT0,            IP10_7_4)
 139 #define GPSR4_8         F_(SD3_CMD,             IP10_3_0)
 140 #define GPSR4_7         F_(SD3_CLK,             IP9_31_28)
 141 #define GPSR4_6         F_(SD2_DS,              IP9_27_24)
 142 #define GPSR4_5         F_(SD2_DAT3,            IP9_23_20)
 143 #define GPSR4_4         F_(SD2_DAT2,            IP9_19_16)
 144 #define GPSR4_3         F_(SD2_DAT1,            IP9_15_12)
 145 #define GPSR4_2         F_(SD2_DAT0,            IP9_11_8)
 146 #define GPSR4_1         F_(SD2_CMD,             IP9_7_4)
 147 #define GPSR4_0         F_(SD2_CLK,             IP9_3_0)
 148
 149 /* GPSR5 */
 150 #define GPSR5_25        F_(MLB_DAT,             IP14_19_16)
 151 #define GPSR5_24        F_(MLB_SIG,             IP14_15_12)
 152 #define GPSR5_23        F_(MLB_CLK,             IP14_11_8)
 153 #define GPSR5_22        FM(MSIOF0_RXD)
 154 #define GPSR5_21        F_(MSIOF0_SS2,          IP14_7_4)
 155 #define GPSR5_20        FM(MSIOF0_TXD)
 156 #define GPSR5_19        F_(MSIOF0_SS1,          IP14_3_0)
 157 #define GPSR5_18        F_(MSIOF0_SYNC,         IP13_31_28)
 158 #define GPSR5_17        FM(MSIOF0_SCK)
 159 #define GPSR5_16        F_(HRTS0_N,             IP13_27_24)
 160 #define GPSR5_15        F_(HCTS0_N,             IP13_23_20)
 161 #define GPSR5_14        F_(HTX0,                IP13_19_16)
 162 #define GPSR5_13        F_(HRX0,                IP13_15_12)
 163 #define GPSR5_12        F_(HSCK0,               IP13_11_8)
 164 #define GPSR5_11        F_(RX2_A,               IP13_7_4)
 165 #define GPSR5_10        F_(TX2_A,               IP13_3_0)
 166 #define GPSR5_9         F_(SCK2,                IP12_31_28)
 167 #define GPSR5_8         F_(RTS1_N,              IP12_27_24)
 168 #define GPSR5_7         F_(CTS1_N,              IP12_23_20)
 169 #define GPSR5_6         F_(TX1_A,               IP12_19_16)
 170 #define GPSR5_5         F_(RX1_A,               IP12_15_12)
 171 #define GPSR5_4         F_(RTS0_N,              IP12_11_8)
 172 #define GPSR5_3         F_(CTS0_N,              IP12_7_4)
 173 #define GPSR5_2         F_(TX0,                 IP12_3_0)
 174 #define GPSR5_1         F_(RX0,                 IP11_31_28)
 175 #define GPSR5_0         F_(SCK0,                IP11_27_24)
 176
 177 /* GPSR6 */
 178 #define GPSR6_31        F_(GP6_31,              IP18_7_4)
 179 #define GPSR6_30        F_(GP6_30,              IP18_3_0)
 180 #define GPSR6_29        F_(USB30_OVC,           IP17_31_28)
 181 #define GPSR6_28        F_(USB30_PWEN,          IP17_27_24)
 182 #define GPSR6_27        F_(USB1_OVC,            IP17_23_20)
 183 #define GPSR6_26        F_(USB1_PWEN,           IP17_19_16)
 184 #define GPSR6_25        F_(USB0_OVC,            IP17_15_12)
 185 #define GPSR6_24        F_(USB0_PWEN,           IP17_11_8)
 186 #define GPSR6_23        F_(AUDIO_CLKB_B,        IP17_7_4)
 187 #define GPSR6_22        F_(AUDIO_CLKA_A,        IP17_3_0)
 188 #define GPSR6_21        F_(SSI_SDATA9_A,        IP16_31_28)
 189 #define GPSR6_20        F_(SSI_SDATA8,          IP16_27_24)
 190 #define GPSR6_19        F_(SSI_SDATA7,          IP16_23_20)
 191 #define GPSR6_18        F_(SSI_WS78,            IP16_19_16)
 192 #define GPSR6_17        F_(SSI_SCK78,           IP16_15_12)
 193 #define GPSR6_16        F_(SSI_SDATA6,          IP16_11_8)
 194 #define GPSR6_15        F_(SSI_WS6,             IP16_7_4)
 195 #define GPSR6_14        F_(SSI_SCK6,            IP16_3_0)
 196 #define GPSR6_13        FM(SSI_SDATA5)
 197 #define GPSR6_12        FM(SSI_WS5)
 198 #define GPSR6_11        FM(SSI_SCK5)
 199 #define GPSR6_10        F_(SSI_SDATA4,          IP15_31_28)
 200 #define GPSR6_9         F_(SSI_WS4,             IP15_27_24)
 201 #define GPSR6_8         F_(SSI_SCK4,            IP15_23_20)
 202 #define GPSR6_7         F_(SSI_SDATA3,          IP15_19_16)
 203 #define GPSR6_6         F_(SSI_WS349,           IP15_15_12)
 204 #define GPSR6_5         F_(SSI_SCK349,          IP15_11_8)
 205 #define GPSR6_4         F_(SSI_SDATA2_A,        IP15_7_4)
 206 #define GPSR6_3         F_(SSI_SDATA1_A,        IP15_3_0)
 207 #define GPSR6_2         F_(SSI_SDATA0,          IP14_31_28)
 208 #define GPSR6_1         F_(SSI_WS01239,         IP14_27_24)
 209 #define GPSR6_0         F_(SSI_SCK01239,        IP14_23_20)
 210
 211 /* GPSR7 */
 212 #define GPSR7_3         FM(GP7_03)
 213 #define GPSR7_2         FM(HDMI0_CEC)
 214 #define GPSR7_1         FM(AVS2)
 215 #define GPSR7_0         FM(AVS1)
 216
 217
 218 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 219 #define IP0_3_0         FM(AVB_MDC)             F_(0, 0)        FM(MSIOF2_SS2_C)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220 #define IP0_7_4         FM(AVB_MAGIC)           F_(0, 0)        FM(MSIOF2_SS1_C)        FM(SCK4_A)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221 #define IP0_11_8        FM(AVB_PHY_INT)         F_(0, 0)        FM(MSIOF2_SYNC_C)       FM(RX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222 #define IP0_15_12       FM(AVB_LINK)            F_(0, 0)        FM(MSIOF2_SCK_C)        FM(TX4_A)                       F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223 #define IP0_19_16       FM(AVB_AVTP_MATCH_A)    F_(0, 0)        FM(MSIOF2_RXD_C)        FM(CTS4_N_A)                    F_(0, 0)        FM(FSCLKST2_N_A) F_(0, 0)               F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224 #define IP0_23_20       FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)        FM(MSIOF2_TXD_C)        FM(RTS4_N_A)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225 #define IP0_27_24       FM(IRQ0)                FM(QPOLB)       F_(0, 0)                FM(DU_CDE)                      FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)         FM(MSIOF3_SS2_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226 #define IP0_31_28       FM(IRQ1)                FM(QPOLA)       F_(0, 0)                FM(DU_DISP)                     FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)         FM(MSIOF3_SS1_E) F_(0, 0)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227 #define IP1_3_0         FM(IRQ2)                FM(QCPV_QDE)    F_(0, 0)                FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SYNC_E) F_(0, 0)              FM(PWM3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228 #define IP1_7_4         FM(IRQ3)                FM(QSTVB_QVE)   F_(0, 0)                FM(DU_DOTCLKOUT1)               FM(VI4_DATA3_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_SCK_E) F_(0, 0)               FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229 #define IP1_11_8        FM(IRQ4)                FM(QSTH_QHS)    F_(0, 0)                FM(DU_EXHSYNC_DU_HSYNC)         FM(VI4_DATA4_B) F_(0, 0)        F_(0, 0)                FM(MSIOF3_RXD_E) F_(0, 0)               FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230 #define IP1_15_12       FM(IRQ5)                FM(QSTB_QHE)    F_(0, 0)                FM(DU_EXVSYNC_DU_VSYNC)         FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)               FM(MSIOF3_TXD_E) F_(0, 0)               FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231 #define IP1_19_16       FM(PWM0)                FM(AVB_AVTP_PPS)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA6_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IECLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232 #define IP1_23_20       FM(PWM1_A)              F_(0, 0)        F_(0, 0)                FM(HRX3_D)                      FM(VI4_DATA7_B) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IERX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233 #define IP1_27_24       FM(PWM2_A)              F_(0, 0)        F_(0, 0)                FM(HTX3_D)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                FM(IETX_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234 #define IP1_31_28       FM(A0)                  FM(LCDOUT16)    FM(MSIOF3_SYNC_B)       F_(0, 0)                        FM(VI4_DATA8)   F_(0, 0)        FM(DU_DB0)              F_(0, 0)        F_(0, 0)                FM(PWM3_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235 #define IP2_3_0         FM(A1)                  FM(LCDOUT17)    FM(MSIOF3_TXD_B)        F_(0, 0)                        FM(VI4_DATA9)   F_(0, 0)        FM(DU_DB1)              F_(0, 0)        F_(0, 0)                FM(PWM4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236 #define IP2_7_4         FM(A2)                  FM(LCDOUT18)    FM(MSIOF3_SCK_B)        F_(0, 0)                        FM(VI4_DATA10)  F_(0, 0)        FM(DU_DB2)              F_(0, 0)        F_(0, 0)                FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237 #define IP2_11_8        FM(A3)                  FM(LCDOUT19)    FM(MSIOF3_RXD_B)        F_(0, 0)                        FM(VI4_DATA11)  F_(0, 0)        FM(DU_DB3)              F_(0, 0)        F_(0, 0)                FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238 #define IP2_15_12       FM(A4)                  FM(LCDOUT20)    FM(MSIOF3_SS1_B)        F_(0, 0)                        FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239 #define IP2_19_16       FM(A5)                  FM(LCDOUT21)    FM(MSIOF3_SS2_B)        FM(SCK4_B)                      FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240 #define IP2_23_20       FM(A6)                  FM(LCDOUT22)    FM(MSIOF2_SS1_A)        FM(RX4_B)                       FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241 #define IP2_27_24       FM(A7)                  FM(LCDOUT23)    FM(MSIOF2_SS2_A)        FM(TX4_B)                       FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242 #define IP2_31_28       FM(A8)                  FM(RX3_B)       FM(MSIOF2_SYNC_A)       FM(HRX4_B)                      F_(0, 0)        F_(0, 0)        F_(0, 0)                FM(SDA6_A)      FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243 #define IP3_3_0         FM(A9)                  F_(0, 0)        FM(MSIOF2_SCK_A)        FM(CTS4_N_B)                    F_(0, 0)        FM(VI5_VSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244 #define IP3_7_4         FM(A10)                 F_(0, 0)        FM(MSIOF2_RXD_A)        FM(RTS4_N_B)                    F_(0, 0)        FM(VI5_HSYNC_N) F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245 #define IP3_11_8        FM(A11)                 FM(TX3_B)       FM(MSIOF2_TXD_A)        FM(HTX4_B)                      FM(HSCK4)       FM(VI5_FIELD)   F_(0, 0)                FM(SCL6_A)      FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 246
 247 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 248 #define IP3_15_12       FM(A12)                 FM(LCDOUT12)    FM(MSIOF3_SCK_C)        F_(0, 0)                        FM(HRX4_A)      FM(VI5_DATA8)   FM(DU_DG4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249 #define IP3_19_16       FM(A13)                 FM(LCDOUT13)    FM(MSIOF3_SYNC_C)       F_(0, 0)                        FM(HTX4_A)      FM(VI5_DATA9)   FM(DU_DG5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250 #define IP3_23_20       FM(A14)                 FM(LCDOUT14)    FM(MSIOF3_RXD_C)        F_(0, 0)                        FM(HCTS4_N)     FM(VI5_DATA10)  FM(DU_DG6)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251 #define IP3_27_24       FM(A15)                 FM(LCDOUT15)    FM(MSIOF3_TXD_C)        F_(0, 0)                        FM(HRTS4_N)     FM(VI5_DATA11)  FM(DU_DG7)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252 #define IP3_31_28       FM(A16)                 FM(LCDOUT8)     F_(0, 0)                F_(0, 0)                        FM(VI4_FIELD)   F_(0, 0)        FM(DU_DG0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253 #define IP4_3_0         FM(A17)                 FM(LCDOUT9)     F_(0, 0)                F_(0, 0)                        FM(VI4_VSYNC_N) F_(0, 0)        FM(DU_DG1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254 #define IP4_7_4         FM(A18)                 FM(LCDOUT10)    F_(0, 0)                F_(0, 0)                        FM(VI4_HSYNC_N) F_(0, 0)        FM(DU_DG2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255 #define IP4_11_8        FM(A19)                 FM(LCDOUT11)    F_(0, 0)                F_(0, 0)                        FM(VI4_CLKENB)  F_(0, 0)        FM(DU_DG3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256 #define IP4_15_12       FM(CS0_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLKENB)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257 #define IP4_19_16       FM(CS1_N)               F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(VI5_CLK)     F_(0, 0)                FM(EX_WAIT0_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258 #define IP4_23_20       FM(BS_N)                FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)        FM(SCK3)                        FM(HSCK3)       F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN1_TX)             FM(CANFD1_TX)   FM(IETX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259 #define IP4_27_24       FM(RD_N)                F_(0, 0)        FM(MSIOF3_SYNC_D)       FM(RX3_A)                       FM(HRX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_TX_A)           FM(CANFD0_TX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260 #define IP4_31_28       FM(RD_WR_N)             F_(0, 0)        FM(MSIOF3_RXD_D)        FM(TX3_A)                       FM(HTX3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(CAN0_RX_A)           FM(CANFD0_RX_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261 #define IP5_3_0         FM(WE0_N)               F_(0, 0)        FM(MSIOF3_TXD_D)        FM(CTS3_N)                      FM(HCTS3_N)     F_(0, 0)        F_(0, 0)                FM(SCL6_B)      FM(CAN_CLK)             F_(0, 0)        FM(IECLK_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262 #define IP5_7_4         FM(WE1_N)               F_(0, 0)        FM(MSIOF3_SS1_D)        FM(RTS3_N)                      FM(HRTS3_N)     F_(0, 0)        F_(0, 0)                FM(SDA6_B)      FM(CAN1_RX)             FM(CANFD1_RX)   FM(IERX_A)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263 #define IP5_11_8        FM(EX_WAIT0_A)          FM(QCLK)        F_(0, 0)                F_(0, 0)                        FM(VI4_CLK)     F_(0, 0)        FM(DU_DOTCLKOUT0)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264 #define IP5_15_12       FM(D0)                  FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)        F_(0, 0)                        FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265 #define IP5_19_16       FM(D1)                  FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)       F_(0, 0)                        FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266 #define IP5_23_20       FM(D2)                  F_(0, 0)        FM(MSIOF3_RXD_A)        F_(0, 0)                        FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267 #define IP5_27_24       FM(D3)                  F_(0, 0)        FM(MSIOF3_TXD_A)        F_(0, 0)                        FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268 #define IP5_31_28       FM(D4)                  FM(MSIOF2_SCK_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269 #define IP6_3_0         FM(D5)                  FM(MSIOF2_SYNC_B)F_(0, 0)               F_(0, 0)                        FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270 #define IP6_7_4         FM(D6)                  FM(MSIOF2_RXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271 #define IP6_11_8        FM(D7)                  FM(MSIOF2_TXD_B)F_(0, 0)                F_(0, 0)                        FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272 #define IP6_15_12       FM(D8)                  FM(LCDOUT0)     FM(MSIOF2_SCK_D)        FM(SCK4_C)                      FM(VI4_DATA0_A) F_(0, 0)        FM(DU_DR0)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273 #define IP6_19_16       FM(D9)                  FM(LCDOUT1)     FM(MSIOF2_SYNC_D)       F_(0, 0)                        FM(VI4_DATA1_A) F_(0, 0)        FM(DU_DR1)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274 #define IP6_23_20       FM(D10)                 FM(LCDOUT2)     FM(MSIOF2_RXD_D)        FM(HRX3_B)                      FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275 #define IP6_27_24       FM(D11)                 FM(LCDOUT3)     FM(MSIOF2_TXD_D)        FM(HTX3_B)                      FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276 #define IP6_31_28       FM(D12)                 FM(LCDOUT4)     FM(MSIOF2_SS1_D)        FM(RX4_C)                       FM(VI4_DATA4_A) F_(0, 0)        FM(DU_DR4)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277
 278 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 279 #define IP7_3_0         FM(D13)                 FM(LCDOUT5)     FM(MSIOF2_SS2_D)        FM(TX4_C)                       FM(VI4_DATA5_A) F_(0, 0)        FM(DU_DR5)              F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280 #define IP7_7_4         FM(D14)                 FM(LCDOUT6)     FM(MSIOF3_SS1_A)        FM(HRX3_C)                      FM(VI4_DATA6_A) F_(0, 0)        FM(DU_DR6)              FM(SCL6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281 #define IP7_11_8        FM(D15)                 FM(LCDOUT7)     FM(MSIOF3_SS2_A)        FM(HTX3_C)                      FM(VI4_DATA7_A) F_(0, 0)        FM(DU_DR7)              FM(SDA6_C)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282 #define IP7_19_16       FM(SD0_CLK)             F_(0, 0)        FM(MSIOF1_SCK_E)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283 #define IP7_23_20       FM(SD0_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_E)       F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284 #define IP7_27_24       FM(SD0_DAT0)            F_(0, 0)        FM(MSIOF1_RXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285 #define IP7_31_28       FM(SD0_DAT1)            F_(0, 0)        FM(MSIOF1_TXD_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286 #define IP8_3_0         FM(SD0_DAT2)            F_(0, 0)        FM(MSIOF1_SS1_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_B)  FM(STP_ISD_0_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 287 #define IP8_7_4         FM(SD0_DAT3)            F_(0, 0)        FM(MSIOF1_SS2_E)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288 #define IP8_11_8        FM(SD1_CLK)             F_(0, 0)        FM(MSIOF1_SCK_G)        F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289 #define IP8_15_12       FM(SD1_CMD)             F_(0, 0)        FM(MSIOF1_SYNC_G)       FM(NFCE_N_B)                    F_(0, 0)        FM(SIM0_D_A)    FM(STP_IVCXO27_1_B)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290 #define IP8_19_16       FM(SD1_DAT0)            FM(SD2_DAT4)    FM(MSIOF1_RXD_G)        FM(NFWP_N_B)                    F_(0, 0)        FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291 #define IP8_23_20       FM(SD1_DAT1)            FM(SD2_DAT5)    FM(MSIOF1_TXD_G)        FM(NFDATA14_B)                  F_(0, 0)        FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292 #define IP8_27_24       FM(SD1_DAT2)            FM(SD2_DAT6)    FM(MSIOF1_SS1_G)        FM(NFDATA15_B)                  F_(0, 0)        FM(TS_SDAT1_B)  FM(STP_ISD_1_B)         F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293 #define IP8_31_28       FM(SD1_DAT3)            FM(SD2_DAT7)    FM(MSIOF1_SS2_G)        FM(NFRB_N_B)                    F_(0, 0)        FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294 #define IP9_3_0         FM(SD2_CLK)             F_(0, 0)        FM(NFDATA8)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295 #define IP9_7_4         FM(SD2_CMD)             F_(0, 0)        FM(NFDATA9)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296 #define IP9_11_8        FM(SD2_DAT0)            F_(0, 0)        FM(NFDATA10)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297 #define IP9_15_12       FM(SD2_DAT1)            F_(0, 0)        FM(NFDATA11)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298 #define IP9_19_16       FM(SD2_DAT2)            F_(0, 0)        FM(NFDATA12)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299 #define IP9_23_20       FM(SD2_DAT3)            F_(0, 0)        FM(NFDATA13)            F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300 #define IP9_27_24       FM(SD2_DS)              F_(0, 0)        FM(NFALE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301 #define IP9_31_28       FM(SD3_CLK)             F_(0, 0)        FM(NFWE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302 #define IP10_3_0        FM(SD3_CMD)             F_(0, 0)        FM(NFRE_N)              F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303 #define IP10_7_4        FM(SD3_DAT0)            F_(0, 0)        FM(NFDATA0)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304 #define IP10_11_8       FM(SD3_DAT1)            F_(0, 0)        FM(NFDATA1)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305 #define IP10_15_12      FM(SD3_DAT2)            F_(0, 0)        FM(NFDATA2)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306 #define IP10_19_16      FM(SD3_DAT3)            F_(0, 0)        FM(NFDATA3)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307 #define IP10_23_20      FM(SD3_DAT4)            FM(SD2_CD_A)    FM(NFDATA4)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308 #define IP10_27_24      FM(SD3_DAT5)            FM(SD2_WP_A)    FM(NFDATA5)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309 #define IP10_31_28      FM(SD3_DAT6)            FM(SD3_CD)      FM(NFDATA6)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310 #define IP11_3_0        FM(SD3_DAT7)            FM(SD3_WP)      FM(NFDATA7)             F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311 #define IP11_7_4        FM(SD3_DS)              F_(0, 0)        FM(NFCLE)               F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312 #define IP11_11_8       FM(SD0_CD)              F_(0, 0)        FM(NFDATA14_A)          F_(0, 0)                        FM(SCL2_B)      FM(SIM0_RST_A)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313
 314 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 315 #define IP11_15_12      FM(SD0_WP)              F_(0, 0)        FM(NFDATA15_A)          F_(0, 0)                        FM(SDA2_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316 #define IP11_19_16      FM(SD1_CD)              F_(0, 0)        FM(NFRB_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317 #define IP11_23_20      FM(SD1_WP)              F_(0, 0)        FM(NFCE_N_A)            F_(0, 0)                        F_(0, 0)        FM(SIM0_D_B)    F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318 #define IP11_27_24      FM(SCK0)                FM(HSCK1_B)     FM(MSIOF1_SS2_B)        FM(AUDIO_CLKC_B)                FM(SDA2_A)      FM(SIM0_RST_B)  FM(STP_OPWM_0_C)        FM(RIF0_CLK_B)  F_(0, 0)                FM(ADICHS2)     FM(SCK5_B)      F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319 #define IP11_31_28      FM(RX0)                 FM(HRX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)       FM(RIF0_D0_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320 #define IP12_3_0        FM(TX0)                 FM(HTX1_B)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)      FM(RIF0_D1_B)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321 #define IP12_7_4        FM(CTS0_N)              FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)       F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)      FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)      FM(ADICS_SAMP)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322 #define IP12_11_8       FM(RTS0_N)              FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)        FM(AUDIO_CLKA_B)                FM(SCL2_A)      F_(0, 0)        FM(STP_IVCXO27_1_C)     FM(RIF0_SYNC_B) F_(0, 0)                FM(ADICHS1)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323 #define IP12_15_12      FM(RX1_A)               FM(HRX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_C)  FM(STP_ISD_0_C)         FM(RIF1_CLK_C)  F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324 #define IP12_19_16      FM(TX1_A)               FM(HTX1_A)      F_(0, 0)                F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)        FM(RIF1_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325 #define IP12_23_20      FM(CTS1_N)              FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)        FM(RIF1_D0_B)   F_(0, 0)                FM(ADIDATA)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326 #define IP12_27_24      FM(RTS1_N)              FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_C)  FM(STP_ISD_1_C)         FM(RIF1_D1_B)   F_(0, 0)                FM(ADICHS0)     F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327 #define IP12_31_28      FM(SCK2)                FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)       FM(RIF1_CLK_B)  F_(0, 0)                FM(ADICLK)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328 #define IP13_3_0        FM(TX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_CD_B)                    FM(SCL1_A)      F_(0, 0)        FM(FMCLK_A)             FM(RIF1_D1_C)   F_(0, 0)                FM(FSO_CFE_0_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329 #define IP13_7_4        FM(RX2_A)               F_(0, 0)        F_(0, 0)                FM(SD2_WP_B)                    FM(SDA1_A)      F_(0, 0)        FM(FMIN_A)              FM(RIF1_SYNC_C) F_(0, 0)                FM(FSO_CFE_1_N) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330 #define IP13_11_8       FM(HSCK0)               F_(0, 0)        FM(MSIOF1_SCK_D)        FM(AUDIO_CLKB_A)                FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)       FM(RIF0_CLK_C)  F_(0, 0)                F_(0, 0)        FM(RX5_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331 #define IP13_15_12      FM(HRX0)                F_(0, 0)        FM(MSIOF1_RXD_D)        F_(0, 0)                        FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)        FM(RIF0_D0_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332 #define IP13_19_16      FM(HTX0)                F_(0, 0)        FM(MSIOF1_TXD_D)        F_(0, 0)                        FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)         FM(RIF0_D1_C)   F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333 #define IP13_23_20      FM(HCTS0_N)             FM(RX2_B)       FM(MSIOF1_SYNC_D)       F_(0, 0)                        FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)      FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334 #define IP13_27_24      FM(HRTS0_N)             FM(TX2_B)       FM(MSIOF1_SS1_D)        F_(0, 0)                        FM(SSI_WS9_A)   F_(0, 0)        FM(STP_IVCXO27_0_D)     FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335 #define IP13_31_28      FM(MSIOF0_SYNC)         F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(AUDIO_CLKOUT_A)      F_(0, 0)        FM(TX5_B)       F_(0, 0)        F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 336 #define IP14_3_0        FM(MSIOF0_SS1)          FM(RX5_A)       FM(NFWP_N_A)            FM(AUDIO_CLKA_C)                FM(SSI_SCK2_A)  F_(0, 0)        FM(STP_IVCXO27_0_C)     F_(0, 0)        FM(AUDIO_CLKOUT3_A)     F_(0, 0)        FM(TCLK1_B)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337 #define IP14_7_4        FM(MSIOF0_SS2)          FM(TX5_A)       FM(MSIOF1_SS2_D)        FM(AUDIO_CLKC_A)                FM(SSI_WS2_A)   F_(0, 0)        FM(STP_OPWM_0_D)        F_(0, 0)        FM(AUDIO_CLKOUT_D)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338 #define IP14_11_8       FM(MLB_CLK)             F_(0, 0)        FM(MSIOF1_SCK_F)        F_(0, 0)                        FM(SCL1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339 #define IP14_15_12      FM(MLB_SIG)             FM(RX1_B)       FM(MSIOF1_SYNC_F)       F_(0, 0)                        FM(SDA1_B)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340 #define IP14_19_16      FM(MLB_DAT)             FM(TX1_B)       FM(MSIOF1_RXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341 #define IP14_23_20      FM(SSI_SCK01239)        F_(0, 0)        FM(MSIOF1_TXD_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342 #define IP14_27_24      FM(SSI_WS01239)         F_(0, 0)        FM(MSIOF1_SS1_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343
 344 /* IPSRx */             /* 0 */                 /* 1 */         /* 2 */                 /* 3 */                         /* 4 */         /* 5 */         /* 6 */                 /* 7 */         /* 8 */                 /* 9 */         /* A */         /* B */         /* C - F */
 345 #define IP14_31_28      FM(SSI_SDATA0)          F_(0, 0)        FM(MSIOF1_SS2_F)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346 #define IP15_3_0        FM(SSI_SDATA1_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347 #define IP15_7_4        FM(SSI_SDATA2_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        FM(SSI_SCK1_B)  F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348 #define IP15_11_8       FM(SSI_SCK349)          F_(0, 0)        FM(MSIOF1_SS1_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_OPWM_0_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349 #define IP15_15_12      FM(SSI_WS349)           FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)        F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_0_A)     F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350 #define IP15_19_16      FM(SSI_SDATA3)          FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)       FM(RIF0_D1_A)   FM(RIF2_D0_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351 #define IP15_23_20      FM(SSI_SCK4)            FM(HRX2_A)      FM(MSIOF1_SCK_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SDAT0_A)  FM(STP_ISD_0_A)         FM(RIF0_CLK_A)  FM(RIF2_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352 #define IP15_27_24      FM(SSI_WS4)             FM(HTX2_A)      FM(MSIOF1_SYNC_A)       F_(0, 0)                        F_(0, 0)        FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)        FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353 #define IP15_31_28      FM(SSI_SDATA4)          FM(HSCK2_A)     FM(MSIOF1_RXD_A)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)      FM(RIF0_D0_A)   FM(RIF2_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354 #define IP16_3_0        FM(SSI_SCK6)            F_(0, 0)        F_(0, 0)                FM(SIM0_RST_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355 #define IP16_7_4        FM(SSI_WS6)             F_(0, 0)        F_(0, 0)                FM(SIM0_D_D)                    F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356 #define IP16_11_8       FM(SSI_SDATA6)          F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_D)                  F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        FM(SATA_DEVSLP_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357 #define IP16_15_12      FM(SSI_SCK78)           FM(HRX2_B)      FM(MSIOF1_SCK_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)       FM(RIF1_CLK_A)  FM(RIF3_CLK_A)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358 #define IP16_19_16      FM(SSI_WS78)            FM(HTX2_B)      FM(MSIOF1_SYNC_C)       F_(0, 0)                        F_(0, 0)        FM(TS_SDAT1_A)  FM(STP_ISD_1_A)         FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359 #define IP16_23_20      FM(SSI_SDATA7)          FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)        FM(RIF1_D0_A)   FM(RIF3_D0_A)           F_(0, 0)        FM(TCLK2_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360 #define IP16_27_24      FM(SSI_SDATA8)          FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)        F_(0, 0)                        F_(0, 0)        FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)      FM(RIF1_D1_A)   FM(RIF3_D1_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361 #define IP16_31_28      FM(SSI_SDATA9_A)        FM(HSCK2_B)     FM(MSIOF1_SS1_C)        FM(HSCK1_A)                     FM(SSI_WS1_B)   FM(SCK1)        FM(STP_IVCXO27_1_A)     FM(SCK5_A)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 362 #define IP17_3_0        FM(AUDIO_CLKA_A)        F_(0, 0)        F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(CC5_OSCOUT)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363 #define IP17_7_4        FM(AUDIO_CLKB_B)        FM(SCIF_CLK_A)  F_(0, 0)                F_(0, 0)                        F_(0, 0)        F_(0, 0)        FM(STP_IVCXO27_1_D)     FM(REMOCON_A)   F_(0, 0)                F_(0, 0)        FM(TCLK1_A)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 364 #define IP17_11_8       FM(USB0_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_RST_C)                  F_(0, 0)        FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)       FM(BPFCLK_B)    FM(RIF3_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 365 #define IP17_15_12      FM(USB0_OVC)            F_(0, 0)        F_(0, 0)                FM(SIM0_D_C)                    F_(0, 0)        FM(TS_SDAT1_D)  FM(STP_ISD_1_D)         F_(0, 0)        FM(RIF3_SYNC_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 366 #define IP17_19_16      FM(USB1_PWEN)           F_(0, 0)        F_(0, 0)                FM(SIM0_CLK_C)                  FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)       FM(FMCLK_B)     FM(RIF2_CLK_B)          F_(0, 0)        FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 367 #define IP17_23_20      FM(USB1_OVC)            F_(0, 0)        FM(MSIOF1_SS2_C)        F_(0, 0)                        FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)         FM(FMIN_B)      FM(RIF2_SYNC_B)         F_(0, 0)        FM(REMOCON_B)   F_(0, 0)        F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 368 #define IP17_27_24      FM(USB30_PWEN)          F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT_B)              FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)        FM(STP_OPWM_0_E)FM(RIF3_D0_B)           F_(0, 0)        FM(TCLK2_B)     FM(TPU0TO0)     FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 369 #define IP17_31_28      FM(USB30_OVC)           F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT1_B)             FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)      FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)        F_(0, 0)        FM(FSO_TOE_N)   FM(TPU0TO1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 370 #define IP18_3_0        FM(GP6_30)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT2_B)             FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)        F_(0, 0)        FM(RIF2_D0_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO2)     FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 371 #define IP18_7_4        FM(GP6_31)              F_(0, 0)        F_(0, 0)                FM(AUDIO_CLKOUT3_B)             FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)      F_(0, 0)        FM(RIF2_D1_B)           F_(0, 0)        F_(0, 0)        FM(TPU0TO3)     FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 372
 373 #define PINMUX_GPSR     \
 374 \
 375                                                                                                 GPSR6_31 \
 376                                                                                                 GPSR6_30 \
 377                                                                                                 GPSR6_29 \
 378                 GPSR1_28                                                                        GPSR6_28 \
 379                 GPSR1_27                                                                        GPSR6_27 \
 380                 GPSR1_26                                                                        GPSR6_26 \
 381                 GPSR1_25                                                        GPSR5_25        GPSR6_25 \
 382                 GPSR1_24                                                        GPSR5_24        GPSR6_24 \
 383                 GPSR1_23                                                        GPSR5_23        GPSR6_23 \
 384                 GPSR1_22                                                        GPSR5_22        GPSR6_22 \
 385                 GPSR1_21                                                        GPSR5_21        GPSR6_21 \
 386                 GPSR1_20                                                        GPSR5_20        GPSR6_20 \
 387                 GPSR1_19                                                        GPSR5_19        GPSR6_19 \
 388                 GPSR1_18                                                        GPSR5_18        GPSR6_18 \
 389                 GPSR1_17                                        GPSR4_17        GPSR5_17        GPSR6_17 \
 390                 GPSR1_16                                        GPSR4_16        GPSR5_16        GPSR6_16 \
 391 GPSR0_15        GPSR1_15                        GPSR3_15        GPSR4_15        GPSR5_15        GPSR6_15 \
 392 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14        GPSR4_14        GPSR5_14        GPSR6_14 \
 393 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13        GPSR4_13        GPSR5_13        GPSR6_13 \
 394 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12        GPSR4_12        GPSR5_12        GPSR6_12 \
 395 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11        GPSR4_11        GPSR5_11        GPSR6_11 \
 396 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
 397 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
 398 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
 399 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
 400 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
 401 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
 402 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
 403 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3         GPSR7_3 \
 404 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2         GPSR7_2 \
 405 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1         GPSR7_1 \
 406 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0         GPSR7_0
 407
 408 #define PINMUX_IPSR                             \
 409 \
 410 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 411 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 412 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 413 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 414 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 415 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 416 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 417 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 418 \
 419 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 420 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 421 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 422 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12 \
 423 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 424 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 425 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 426 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 427 \
 428 FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
 429 FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
 430 FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
 431 FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
 432 FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
 433 FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
 434 FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
 435 FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
 436 \
 437 FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
 438 FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
 439 FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
 440 FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
 441 FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
 442 FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
 443 FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
 444 FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28 \
 445 \
 446 FM(IP16_3_0)    IP16_3_0        FM(IP17_3_0)    IP17_3_0        FM(IP18_3_0)    IP18_3_0 \
 447 FM(IP16_7_4)    IP16_7_4        FM(IP17_7_4)    IP17_7_4        FM(IP18_7_4)    IP18_7_4 \
 448 FM(IP16_11_8)   IP16_11_8       FM(IP17_11_8)   IP17_11_8 \
 449 FM(IP16_15_12)  IP16_15_12      FM(IP17_15_12)  IP17_15_12 \
 450 FM(IP16_19_16)  IP16_19_16      FM(IP17_19_16)  IP17_19_16 \
 451 FM(IP16_23_20)  IP16_23_20      FM(IP17_23_20)  IP17_23_20 \
 452 FM(IP16_27_24)  IP16_27_24      FM(IP17_27_24)  IP17_27_24 \
 453 FM(IP16_31_28)  IP16_31_28      FM(IP17_31_28)  IP17_31_28
 454
 455 /* MOD_SEL0 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 456 #define MOD_SEL0_31_30_29       FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)        FM(SEL_MSIOF3_2)        FM(SEL_MSIOF3_3)        FM(SEL_MSIOF3_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 457 #define MOD_SEL0_28_27          FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)        FM(SEL_MSIOF2_2)        FM(SEL_MSIOF2_3)
 458 #define MOD_SEL0_26_25_24       FM(SEL_MSIOF1_0)        FM(SEL_MSIOF1_1)        FM(SEL_MSIOF1_2)        FM(SEL_MSIOF1_3)        FM(SEL_MSIOF1_4)        FM(SEL_MSIOF1_5)        FM(SEL_MSIOF1_6)        F_(0, 0)
 459 #define MOD_SEL0_23             FM(SEL_LBSC_0)          FM(SEL_LBSC_1)
 460 #define MOD_SEL0_22             FM(SEL_IEBUS_0)         FM(SEL_IEBUS_1)
 461 #define MOD_SEL0_21             FM(SEL_I2C2_0)          FM(SEL_I2C2_1)
 462 #define MOD_SEL0_20             FM(SEL_I2C1_0)          FM(SEL_I2C1_1)
 463 #define MOD_SEL0_19             FM(SEL_HSCIF4_0)        FM(SEL_HSCIF4_1)
 464 #define MOD_SEL0_18_17          FM(SEL_HSCIF3_0)        FM(SEL_HSCIF3_1)        FM(SEL_HSCIF3_2)        FM(SEL_HSCIF3_3)
 465 #define MOD_SEL0_16             FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
 466 #define MOD_SEL0_14_13          FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)        FM(SEL_HSCIF2_2)        F_(0, 0)
 467 #define MOD_SEL0_12             FM(SEL_ETHERAVB_0)      FM(SEL_ETHERAVB_1)
 468 #define MOD_SEL0_11             FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
 469 #define MOD_SEL0_10             FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
 470 #define MOD_SEL0_9_8            FM(SEL_DRIF1_0)         FM(SEL_DRIF1_1)         FM(SEL_DRIF1_2)         F_(0, 0)
 471 #define MOD_SEL0_7_6            FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)         FM(SEL_DRIF0_2)         F_(0, 0)
 472 #define MOD_SEL0_5              FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 473 #define MOD_SEL0_4_3            FM(SEL_ADG_A_0)         FM(SEL_ADG_A_1)         FM(SEL_ADG_A_2)         FM(SEL_ADG_A_3)
 474
 475 /* MOD_SEL1 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 476 #define MOD_SEL1_31_30          FM(SEL_TSIF1_0)         FM(SEL_TSIF1_1)         FM(SEL_TSIF1_2)         FM(SEL_TSIF1_3)
 477 #define MOD_SEL1_29_28_27       FM(SEL_TSIF0_0)         FM(SEL_TSIF0_1)         FM(SEL_TSIF0_2)         FM(SEL_TSIF0_3)         FM(SEL_TSIF0_4)         F_(0, 0)                F_(0, 0)                F_(0, 0)
 478 #define MOD_SEL1_26             FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
 479 #define MOD_SEL1_25_24          FM(SEL_SSP1_1_0)        FM(SEL_SSP1_1_1)        FM(SEL_SSP1_1_2)        FM(SEL_SSP1_1_3)
 480 #define MOD_SEL1_23_22_21       FM(SEL_SSP1_0_0)        FM(SEL_SSP1_0_1)        FM(SEL_SSP1_0_2)        FM(SEL_SSP1_0_3)        FM(SEL_SSP1_0_4)        F_(0, 0)                F_(0, 0)                F_(0, 0)
 481 #define MOD_SEL1_20             FM(SEL_SSI1_0)          FM(SEL_SSI1_1)
 482 #define MOD_SEL1_19             FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 483 #define MOD_SEL1_18_17          FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)       FM(SEL_SIMCARD_2)       FM(SEL_SIMCARD_3)
 484 #define MOD_SEL1_16             FM(SEL_SDHI2_0)         FM(SEL_SDHI2_1)
 485 #define MOD_SEL1_15_14          FM(SEL_SCIF4_0)         FM(SEL_SCIF4_1)         FM(SEL_SCIF4_2)         F_(0, 0)
 486 #define MOD_SEL1_13             FM(SEL_SCIF3_0)         FM(SEL_SCIF3_1)
 487 #define MOD_SEL1_12             FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
 488 #define MOD_SEL1_11             FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 489 #define MOD_SEL1_10             FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
 490 #define MOD_SEL1_9              FM(SEL_REMOCON_0)       FM(SEL_REMOCON_1)
 491 #define MOD_SEL1_6              FM(SEL_RCAN0_0)         FM(SEL_RCAN0_1)
 492 #define MOD_SEL1_5              FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
 493 #define MOD_SEL1_4              FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
 494 #define MOD_SEL1_3              FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 495 #define MOD_SEL1_2              FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 496 #define MOD_SEL1_1              FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 497 #define MOD_SEL1_0              FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 498
 499 /* MOD_SEL2 */                  /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */                 /* 6 */                 /* 7 */
 500 #define MOD_SEL2_31             FM(I2C_SEL_5_0)         FM(I2C_SEL_5_1)
 501 #define MOD_SEL2_30             FM(I2C_SEL_3_0)         FM(I2C_SEL_3_1)
 502 #define MOD_SEL2_29             FM(I2C_SEL_0_0)         FM(I2C_SEL_0_1)
 503 #define MOD_SEL2_28_27          FM(SEL_FM_0)            FM(SEL_FM_1)            FM(SEL_FM_2)            FM(SEL_FM_3)
 504 #define MOD_SEL2_26             FM(SEL_SCIF5_0)         FM(SEL_SCIF5_1)
 505 #define MOD_SEL2_25_24_23       FM(SEL_I2C6_0)          FM(SEL_I2C6_1)          FM(SEL_I2C6_2)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)
 506 #define MOD_SEL2_22             FM(SEL_NDFC_0)          FM(SEL_NDFC_1)
 507 #define MOD_SEL2_21             FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
 508 #define MOD_SEL2_20             FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
 509 #define MOD_SEL2_19             FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
 510 #define MOD_SEL2_18             FM(SEL_ADG_B_0)         FM(SEL_ADG_B_1)
 511 #define MOD_SEL2_17             FM(SEL_ADG_C_0)         FM(SEL_ADG_C_1)
 512 #define MOD_SEL2_0              FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
 513
 514 #define PINMUX_MOD_SELS \
 515 \
 516 MOD_SEL0_31_30_29       MOD_SEL1_31_30          MOD_SEL2_31 \
 517                                                 MOD_SEL2_30 \
 518                         MOD_SEL1_29_28_27       MOD_SEL2_29 \
 519 MOD_SEL0_28_27                                  MOD_SEL2_28_27 \
 520 MOD_SEL0_26_25_24       MOD_SEL1_26             MOD_SEL2_26 \
 521                         MOD_SEL1_25_24          MOD_SEL2_25_24_23 \
 522 MOD_SEL0_23             MOD_SEL1_23_22_21 \
 523 MOD_SEL0_22                                     MOD_SEL2_22 \
 524 MOD_SEL0_21                                     MOD_SEL2_21 \
 525 MOD_SEL0_20             MOD_SEL1_20             MOD_SEL2_20 \
 526 MOD_SEL0_19             MOD_SEL1_19             MOD_SEL2_19 \
 527 MOD_SEL0_18_17          MOD_SEL1_18_17          MOD_SEL2_18 \
 528                                                 MOD_SEL2_17 \
 529 MOD_SEL0_16             MOD_SEL1_16 \
 530                         MOD_SEL1_15_14 \
 531 MOD_SEL0_14_13 \
 532                         MOD_SEL1_13 \
 533 MOD_SEL0_12             MOD_SEL1_12 \
 534 MOD_SEL0_11             MOD_SEL1_11 \
 535 MOD_SEL0_10             MOD_SEL1_10 \
 536 MOD_SEL0_9_8            MOD_SEL1_9 \
 537 MOD_SEL0_7_6 \
 538                         MOD_SEL1_6 \
 539 MOD_SEL0_5              MOD_SEL1_5 \
 540 MOD_SEL0_4_3            MOD_SEL1_4 \
 541                         MOD_SEL1_3 \
 542                         MOD_SEL1_2 \
 543                         MOD_SEL1_1 \
 544                         MOD_SEL1_0              MOD_SEL2_0
 545
 546 /*
 547  * These pins are not able to be muxed but have other properties
 548  * that can be set, such as drive-strength or pull-up/pull-down enable.
 549  */
 550 #define PINMUX_STATIC \
 551         FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 552         FM(QSPI0_IO2) FM(QSPI0_IO3) \
 553         FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 554         FM(QSPI1_IO2) FM(QSPI1_IO3) \
 555         FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 556         FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 557         FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 558         FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 559         FM(PRESETOUT) \
 560         FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
 561         FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 562
 563 enum {
 564         PINMUX_RESERVED = 0,
 565
 566         PINMUX_DATA_BEGIN,
 567         GP_ALL(DATA),
 568         PINMUX_DATA_END,
 569
 570 #define F_(x, y)
 571 #define FM(x)   FN_##x,
 572         PINMUX_FUNCTION_BEGIN,
 573         GP_ALL(FN),
 574         PINMUX_GPSR
 575         PINMUX_IPSR
 576         PINMUX_MOD_SELS
 577         PINMUX_FUNCTION_END,
 578 #undef F_
 579 #undef FM
 580
 581 #define F_(x, y)
 582 #define FM(x)   x##_MARK,
 583         PINMUX_MARK_BEGIN,
 584         PINMUX_GPSR
 585         PINMUX_IPSR
 586         PINMUX_MOD_SELS
 587         PINMUX_STATIC
 588         PINMUX_MARK_END,
 589 #undef F_
 590 #undef FM
 591 };
 592
 593 static const u16 pinmux_data[] = {
 594         PINMUX_DATA_GP_ALL(),
 595
 596         PINMUX_SINGLE(AVS1),
 597         PINMUX_SINGLE(AVS2),
 598         PINMUX_SINGLE(CLKOUT),
 599         PINMUX_SINGLE(GP7_03),
 600         PINMUX_SINGLE(HDMI0_CEC),
 601         PINMUX_SINGLE(MSIOF0_RXD),
 602         PINMUX_SINGLE(MSIOF0_SCK),
 603         PINMUX_SINGLE(MSIOF0_TXD),
 604         PINMUX_SINGLE(SSI_SCK5),
 605         PINMUX_SINGLE(SSI_SDATA5),
 606         PINMUX_SINGLE(SSI_WS5),
 607
 608         /* IPSR0 */
 609         PINMUX_IPSR_GPSR(IP0_3_0,       AVB_MDC),
 610         PINMUX_IPSR_MSEL(IP0_3_0,       MSIOF2_SS2_C,           SEL_MSIOF2_2),
 611
 612         PINMUX_IPSR_GPSR(IP0_7_4,       AVB_MAGIC),
 613         PINMUX_IPSR_MSEL(IP0_7_4,       MSIOF2_SS1_C,           SEL_MSIOF2_2),
 614         PINMUX_IPSR_MSEL(IP0_7_4,       SCK4_A,                 SEL_SCIF4_0),
 615
 616         PINMUX_IPSR_GPSR(IP0_11_8,      AVB_PHY_INT),
 617         PINMUX_IPSR_MSEL(IP0_11_8,      MSIOF2_SYNC_C,          SEL_MSIOF2_2),
 618         PINMUX_IPSR_MSEL(IP0_11_8,      RX4_A,                  SEL_SCIF4_0),
 619
 620         PINMUX_IPSR_GPSR(IP0_15_12,     AVB_LINK),
 621         PINMUX_IPSR_MSEL(IP0_15_12,     MSIOF2_SCK_C,           SEL_MSIOF2_2),
 622         PINMUX_IPSR_MSEL(IP0_15_12,     TX4_A,                  SEL_SCIF4_0),
 623         PINMUX_IPSR_GPSR(IP0_19_16,     FSCLKST2_N_A),
 624
 625         PINMUX_IPSR_MSEL(IP0_19_16,     AVB_AVTP_MATCH_A,       SEL_ETHERAVB_0),
 626         PINMUX_IPSR_MSEL(IP0_19_16,     MSIOF2_RXD_C,           SEL_MSIOF2_2),
 627         PINMUX_IPSR_MSEL(IP0_19_16,     CTS4_N_A,               SEL_SCIF4_0),
 628
 629         PINMUX_IPSR_MSEL(IP0_23_20,     AVB_AVTP_CAPTURE_A,     SEL_ETHERAVB_0),
 630         PINMUX_IPSR_MSEL(IP0_23_20,     MSIOF2_TXD_C,           SEL_MSIOF2_2),
 631         PINMUX_IPSR_MSEL(IP0_23_20,     RTS4_N_A,               SEL_SCIF4_0),
 632
 633         PINMUX_IPSR_GPSR(IP0_27_24,     IRQ0),
 634         PINMUX_IPSR_GPSR(IP0_27_24,     QPOLB),
 635         PINMUX_IPSR_GPSR(IP0_27_24,     DU_CDE),
 636         PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA0_B,            SEL_VIN4_1),
 637         PINMUX_IPSR_MSEL(IP0_27_24,     CAN0_TX_B,              SEL_RCAN0_1),
 638         PINMUX_IPSR_MSEL(IP0_27_24,     CANFD0_TX_B,            SEL_CANFD0_1),
 639         PINMUX_IPSR_MSEL(IP0_27_24,     MSIOF3_SS2_E,           SEL_MSIOF3_4),
 640
 641         PINMUX_IPSR_GPSR(IP0_31_28,     IRQ1),
 642         PINMUX_IPSR_GPSR(IP0_31_28,     QPOLA),
 643         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DISP),
 644         PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA1_B,            SEL_VIN4_1),
 645         PINMUX_IPSR_MSEL(IP0_31_28,     CAN0_RX_B,              SEL_RCAN0_1),
 646         PINMUX_IPSR_MSEL(IP0_31_28,     CANFD0_RX_B,            SEL_CANFD0_1),
 647         PINMUX_IPSR_MSEL(IP0_31_28,     MSIOF3_SS1_E,           SEL_MSIOF3_4),
 648
 649         /* IPSR1 */
 650         PINMUX_IPSR_GPSR(IP1_3_0,       IRQ2),
 651         PINMUX_IPSR_GPSR(IP1_3_0,       QCPV_QDE),
 652         PINMUX_IPSR_GPSR(IP1_3_0,       DU_EXODDF_DU_ODDF_DISP_CDE),
 653         PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA2_B,            SEL_VIN4_1),
 654         PINMUX_IPSR_MSEL(IP1_3_0,       PWM3_B,                 SEL_PWM3_1),
 655         PINMUX_IPSR_MSEL(IP1_3_0,       MSIOF3_SYNC_E,          SEL_MSIOF3_4),
 656
 657         PINMUX_IPSR_GPSR(IP1_7_4,       IRQ3),
 658         PINMUX_IPSR_GPSR(IP1_7_4,       QSTVB_QVE),
 659         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DOTCLKOUT1),
 660         PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA3_B,            SEL_VIN4_1),
 661         PINMUX_IPSR_MSEL(IP1_7_4,       PWM4_B,                 SEL_PWM4_1),
 662         PINMUX_IPSR_MSEL(IP1_7_4,       MSIOF3_SCK_E,           SEL_MSIOF3_4),
 663
 664         PINMUX_IPSR_GPSR(IP1_11_8,      IRQ4),
 665         PINMUX_IPSR_GPSR(IP1_11_8,      QSTH_QHS),
 666         PINMUX_IPSR_GPSR(IP1_11_8,      DU_EXHSYNC_DU_HSYNC),
 667         PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA4_B,            SEL_VIN4_1),
 668         PINMUX_IPSR_MSEL(IP1_11_8,      PWM5_B,                 SEL_PWM5_1),
 669         PINMUX_IPSR_MSEL(IP1_11_8,      MSIOF3_RXD_E,           SEL_MSIOF3_4),
 670
 671         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ5),
 672         PINMUX_IPSR_GPSR(IP1_15_12,     QSTB_QHE),
 673         PINMUX_IPSR_GPSR(IP1_15_12,     DU_EXVSYNC_DU_VSYNC),
 674         PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA5_B,            SEL_VIN4_1),
 675         PINMUX_IPSR_MSEL(IP1_15_12,     PWM6_B,                 SEL_PWM6_1),
 676         PINMUX_IPSR_GPSR(IP1_15_12,     FSCLKST2_N_B),
 677         PINMUX_IPSR_MSEL(IP1_15_12,     MSIOF3_TXD_E,           SEL_MSIOF3_4),
 678
 679         PINMUX_IPSR_GPSR(IP1_19_16,     PWM0),
 680         PINMUX_IPSR_GPSR(IP1_19_16,     AVB_AVTP_PPS),
 681         PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA6_B,            SEL_VIN4_1),
 682         PINMUX_IPSR_MSEL(IP1_19_16,     IECLK_B,                SEL_IEBUS_1),
 683
 684         PINMUX_IPSR_MSEL(IP1_23_20,     PWM1_A,                 SEL_PWM1_0),
 685         PINMUX_IPSR_MSEL(IP1_23_20,     HRX3_D,                 SEL_HSCIF3_3),
 686         PINMUX_IPSR_MSEL(IP1_23_20,     VI4_DATA7_B,            SEL_VIN4_1),
 687         PINMUX_IPSR_MSEL(IP1_23_20,     IERX_B,                 SEL_IEBUS_1),
 688
 689         PINMUX_IPSR_MSEL(IP1_27_24,     PWM2_A,                 SEL_PWM2_0),
 690         PINMUX_IPSR_MSEL(IP1_27_24,     HTX3_D,                 SEL_HSCIF3_3),
 691         PINMUX_IPSR_MSEL(IP1_27_24,     IETX_B,                 SEL_IEBUS_1),
 692
 693         PINMUX_IPSR_GPSR(IP1_31_28,     A0),
 694         PINMUX_IPSR_GPSR(IP1_31_28,     LCDOUT16),
 695         PINMUX_IPSR_MSEL(IP1_31_28,     MSIOF3_SYNC_B,          SEL_MSIOF3_1),
 696         PINMUX_IPSR_GPSR(IP1_31_28,     VI4_DATA8),
 697         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB0),
 698         PINMUX_IPSR_MSEL(IP1_31_28,     PWM3_A,                 SEL_PWM3_0),
 699
 700         /* IPSR2 */
 701         PINMUX_IPSR_GPSR(IP2_3_0,       A1),
 702         PINMUX_IPSR_GPSR(IP2_3_0,       LCDOUT17),
 703         PINMUX_IPSR_MSEL(IP2_3_0,       MSIOF3_TXD_B,           SEL_MSIOF3_1),
 704         PINMUX_IPSR_GPSR(IP2_3_0,       VI4_DATA9),
 705         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB1),
 706         PINMUX_IPSR_MSEL(IP2_3_0,       PWM4_A,                 SEL_PWM4_0),
 707
 708         PINMUX_IPSR_GPSR(IP2_7_4,       A2),
 709         PINMUX_IPSR_GPSR(IP2_7_4,       LCDOUT18),
 710         PINMUX_IPSR_MSEL(IP2_7_4,       MSIOF3_SCK_B,           SEL_MSIOF3_1),
 711         PINMUX_IPSR_GPSR(IP2_7_4,       VI4_DATA10),
 712         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB2),
 713         PINMUX_IPSR_MSEL(IP2_7_4,       PWM5_A,                 SEL_PWM5_0),
 714
 715         PINMUX_IPSR_GPSR(IP2_11_8,      A3),
 716         PINMUX_IPSR_GPSR(IP2_11_8,      LCDOUT19),
 717         PINMUX_IPSR_MSEL(IP2_11_8,      MSIOF3_RXD_B,           SEL_MSIOF3_1),
 718         PINMUX_IPSR_GPSR(IP2_11_8,      VI4_DATA11),
 719         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DB3),
 720         PINMUX_IPSR_MSEL(IP2_11_8,      PWM6_A,                 SEL_PWM6_0),
 721
 722         PINMUX_IPSR_GPSR(IP2_15_12,     A4),
 723         PINMUX_IPSR_GPSR(IP2_15_12,     LCDOUT20),
 724         PINMUX_IPSR_MSEL(IP2_15_12,     MSIOF3_SS1_B,           SEL_MSIOF3_1),
 725         PINMUX_IPSR_GPSR(IP2_15_12,     VI4_DATA12),
 726         PINMUX_IPSR_GPSR(IP2_15_12,     VI5_DATA12),
 727         PINMUX_IPSR_GPSR(IP2_15_12,     DU_DB4),
 728
 729         PINMUX_IPSR_GPSR(IP2_19_16,     A5),
 730         PINMUX_IPSR_GPSR(IP2_19_16,     LCDOUT21),
 731         PINMUX_IPSR_MSEL(IP2_19_16,     MSIOF3_SS2_B,           SEL_MSIOF3_1),
 732         PINMUX_IPSR_MSEL(IP2_19_16,     SCK4_B,                 SEL_SCIF4_1),
 733         PINMUX_IPSR_GPSR(IP2_19_16,     VI4_DATA13),
 734         PINMUX_IPSR_GPSR(IP2_19_16,     VI5_DATA13),
 735         PINMUX_IPSR_GPSR(IP2_19_16,     DU_DB5),
 736
 737         PINMUX_IPSR_GPSR(IP2_23_20,     A6),
 738         PINMUX_IPSR_GPSR(IP2_23_20,     LCDOUT22),
 739         PINMUX_IPSR_MSEL(IP2_23_20,     MSIOF2_SS1_A,           SEL_MSIOF2_0),
 740         PINMUX_IPSR_MSEL(IP2_23_20,     RX4_B,                  SEL_SCIF4_1),
 741         PINMUX_IPSR_GPSR(IP2_23_20,     VI4_DATA14),
 742         PINMUX_IPSR_GPSR(IP2_23_20,     VI5_DATA14),
 743         PINMUX_IPSR_GPSR(IP2_23_20,     DU_DB6),
 744
 745         PINMUX_IPSR_GPSR(IP2_27_24,     A7),
 746         PINMUX_IPSR_GPSR(IP2_27_24,     LCDOUT23),
 747         PINMUX_IPSR_MSEL(IP2_27_24,     MSIOF2_SS2_A,           SEL_MSIOF2_0),
 748         PINMUX_IPSR_MSEL(IP2_27_24,     TX4_B,                  SEL_SCIF4_1),
 749         PINMUX_IPSR_GPSR(IP2_27_24,     VI4_DATA15),
 750         PINMUX_IPSR_GPSR(IP2_27_24,     VI5_DATA15),
 751         PINMUX_IPSR_GPSR(IP2_27_24,     DU_DB7),
 752
 753         PINMUX_IPSR_GPSR(IP2_31_28,     A8),
 754         PINMUX_IPSR_MSEL(IP2_31_28,     RX3_B,                  SEL_SCIF3_1),
 755         PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF2_SYNC_A,          SEL_MSIOF2_0),
 756         PINMUX_IPSR_MSEL(IP2_31_28,     HRX4_B,                 SEL_HSCIF4_1),
 757         PINMUX_IPSR_MSEL(IP2_31_28,     SDA6_A,                 SEL_I2C6_0),
 758         PINMUX_IPSR_MSEL(IP2_31_28,     AVB_AVTP_MATCH_B,       SEL_ETHERAVB_1),
 759         PINMUX_IPSR_MSEL(IP2_31_28,     PWM1_B,                 SEL_PWM1_1),
 760
 761         /* IPSR3 */
 762         PINMUX_IPSR_GPSR(IP3_3_0,       A9),
 763         PINMUX_IPSR_MSEL(IP3_3_0,       MSIOF2_SCK_A,           SEL_MSIOF2_0),
 764         PINMUX_IPSR_MSEL(IP3_3_0,       CTS4_N_B,               SEL_SCIF4_1),
 765         PINMUX_IPSR_GPSR(IP3_3_0,       VI5_VSYNC_N),
 766
 767         PINMUX_IPSR_GPSR(IP3_7_4,       A10),
 768         PINMUX_IPSR_MSEL(IP3_7_4,       MSIOF2_RXD_A,           SEL_MSIOF2_0),
 769         PINMUX_IPSR_MSEL(IP3_7_4,       RTS4_N_B,               SEL_SCIF4_1),
 770         PINMUX_IPSR_GPSR(IP3_7_4,       VI5_HSYNC_N),
 771
 772         PINMUX_IPSR_GPSR(IP3_11_8,      A11),
 773         PINMUX_IPSR_MSEL(IP3_11_8,      TX3_B,                  SEL_SCIF3_1),
 774         PINMUX_IPSR_MSEL(IP3_11_8,      MSIOF2_TXD_A,           SEL_MSIOF2_0),
 775         PINMUX_IPSR_MSEL(IP3_11_8,      HTX4_B,                 SEL_HSCIF4_1),
 776         PINMUX_IPSR_GPSR(IP3_11_8,      HSCK4),
 777         PINMUX_IPSR_GPSR(IP3_11_8,      VI5_FIELD),
 778         PINMUX_IPSR_MSEL(IP3_11_8,      SCL6_A,                 SEL_I2C6_0),
 779         PINMUX_IPSR_MSEL(IP3_11_8,      AVB_AVTP_CAPTURE_B,     SEL_ETHERAVB_1),
 780         PINMUX_IPSR_MSEL(IP3_11_8,      PWM2_B,                 SEL_PWM2_1),
 781
 782         PINMUX_IPSR_GPSR(IP3_15_12,     A12),
 783         PINMUX_IPSR_GPSR(IP3_15_12,     LCDOUT12),
 784         PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SCK_C,           SEL_MSIOF3_2),
 785         PINMUX_IPSR_MSEL(IP3_15_12,     HRX4_A,                 SEL_HSCIF4_0),
 786         PINMUX_IPSR_GPSR(IP3_15_12,     VI5_DATA8),
 787         PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
 788
 789         PINMUX_IPSR_GPSR(IP3_19_16,     A13),
 790         PINMUX_IPSR_GPSR(IP3_19_16,     LCDOUT13),
 791         PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SYNC_C,          SEL_MSIOF3_2),
 792         PINMUX_IPSR_MSEL(IP3_19_16,     HTX4_A,                 SEL_HSCIF4_0),
 793         PINMUX_IPSR_GPSR(IP3_19_16,     VI5_DATA9),
 794         PINMUX_IPSR_GPSR(IP3_19_16,     DU_DG5),
 795
 796         PINMUX_IPSR_GPSR(IP3_23_20,     A14),
 797         PINMUX_IPSR_GPSR(IP3_23_20,     LCDOUT14),
 798         PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_C,           SEL_MSIOF3_2),
 799         PINMUX_IPSR_GPSR(IP3_23_20,     HCTS4_N),
 800         PINMUX_IPSR_GPSR(IP3_23_20,     VI5_DATA10),
 801         PINMUX_IPSR_GPSR(IP3_23_20,     DU_DG6),
 802
 803         PINMUX_IPSR_GPSR(IP3_27_24,     A15),
 804         PINMUX_IPSR_GPSR(IP3_27_24,     LCDOUT15),
 805         PINMUX_IPSR_MSEL(IP3_27_24,     MSIOF3_TXD_C,           SEL_MSIOF3_2),
 806         PINMUX_IPSR_GPSR(IP3_27_24,     HRTS4_N),
 807         PINMUX_IPSR_GPSR(IP3_27_24,     VI5_DATA11),
 808         PINMUX_IPSR_GPSR(IP3_27_24,     DU_DG7),
 809
 810         PINMUX_IPSR_GPSR(IP3_31_28,     A16),
 811         PINMUX_IPSR_GPSR(IP3_31_28,     LCDOUT8),
 812         PINMUX_IPSR_GPSR(IP3_31_28,     VI4_FIELD),
 813         PINMUX_IPSR_GPSR(IP3_31_28,     DU_DG0),
 814
 815         /* IPSR4 */
 816         PINMUX_IPSR_GPSR(IP4_3_0,       A17),
 817         PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT9),
 818         PINMUX_IPSR_GPSR(IP4_3_0,       VI4_VSYNC_N),
 819         PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG1),
 820
 821         PINMUX_IPSR_GPSR(IP4_7_4,       A18),
 822         PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT10),
 823         PINMUX_IPSR_GPSR(IP4_7_4,       VI4_HSYNC_N),
 824         PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG2),
 825
 826         PINMUX_IPSR_GPSR(IP4_11_8,      A19),
 827         PINMUX_IPSR_GPSR(IP4_11_8,      LCDOUT11),
 828         PINMUX_IPSR_GPSR(IP4_11_8,      VI4_CLKENB),
 829         PINMUX_IPSR_GPSR(IP4_11_8,      DU_DG3),
 830
 831         PINMUX_IPSR_GPSR(IP4_15_12,     CS0_N),
 832         PINMUX_IPSR_GPSR(IP4_15_12,     VI5_CLKENB),
 833
 834         PINMUX_IPSR_GPSR(IP4_19_16,     CS1_N),
 835         PINMUX_IPSR_GPSR(IP4_19_16,     VI5_CLK),
 836         PINMUX_IPSR_MSEL(IP4_19_16,     EX_WAIT0_B,             SEL_LBSC_1),
 837
 838         PINMUX_IPSR_GPSR(IP4_23_20,     BS_N),
 839         PINMUX_IPSR_GPSR(IP4_23_20,     QSTVA_QVS),
 840         PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF3_SCK_D,           SEL_MSIOF3_3),
 841         PINMUX_IPSR_GPSR(IP4_23_20,     SCK3),
 842         PINMUX_IPSR_GPSR(IP4_23_20,     HSCK3),
 843         PINMUX_IPSR_GPSR(IP4_23_20,     CAN1_TX),
 844         PINMUX_IPSR_GPSR(IP4_23_20,     CANFD1_TX),
 845         PINMUX_IPSR_MSEL(IP4_23_20,     IETX_A,                 SEL_IEBUS_0),
 846
 847         PINMUX_IPSR_GPSR(IP4_27_24,     RD_N),
 848         PINMUX_IPSR_MSEL(IP4_27_24,     MSIOF3_SYNC_D,          SEL_MSIOF3_3),
 849         PINMUX_IPSR_MSEL(IP4_27_24,     RX3_A,                  SEL_SCIF3_0),
 850         PINMUX_IPSR_MSEL(IP4_27_24,     HRX3_A,                 SEL_HSCIF3_0),
 851         PINMUX_IPSR_MSEL(IP4_27_24,     CAN0_TX_A,              SEL_RCAN0_0),
 852         PINMUX_IPSR_MSEL(IP4_27_24,     CANFD0_TX_A,            SEL_CANFD0_0),
 853
 854         PINMUX_IPSR_GPSR(IP4_31_28,     RD_WR_N),
 855         PINMUX_IPSR_MSEL(IP4_31_28,     MSIOF3_RXD_D,           SEL_MSIOF3_3),
 856         PINMUX_IPSR_MSEL(IP4_31_28,     TX3_A,                  SEL_SCIF3_0),
 857         PINMUX_IPSR_MSEL(IP4_31_28,     HTX3_A,                 SEL_HSCIF3_0),
 858         PINMUX_IPSR_MSEL(IP4_31_28,     CAN0_RX_A,              SEL_RCAN0_0),
 859         PINMUX_IPSR_MSEL(IP4_31_28,     CANFD0_RX_A,            SEL_CANFD0_0),
 860
 861         /* IPSR5 */
 862         PINMUX_IPSR_GPSR(IP5_3_0,       WE0_N),
 863         PINMUX_IPSR_MSEL(IP5_3_0,       MSIOF3_TXD_D,           SEL_MSIOF3_3),
 864         PINMUX_IPSR_GPSR(IP5_3_0,       CTS3_N),
 865         PINMUX_IPSR_GPSR(IP5_3_0,       HCTS3_N),
 866         PINMUX_IPSR_MSEL(IP5_3_0,       SCL6_B,                 SEL_I2C6_1),
 867         PINMUX_IPSR_GPSR(IP5_3_0,       CAN_CLK),
 868         PINMUX_IPSR_MSEL(IP5_3_0,       IECLK_A,                SEL_IEBUS_0),
 869
 870         PINMUX_IPSR_GPSR(IP5_7_4,       WE1_N),
 871         PINMUX_IPSR_MSEL(IP5_7_4,       MSIOF3_SS1_D,           SEL_MSIOF3_3),
 872         PINMUX_IPSR_GPSR(IP5_7_4,       RTS3_N),
 873         PINMUX_IPSR_GPSR(IP5_7_4,       HRTS3_N),
 874         PINMUX_IPSR_MSEL(IP5_7_4,       SDA6_B,                 SEL_I2C6_1),
 875         PINMUX_IPSR_GPSR(IP5_7_4,       CAN1_RX),
 876         PINMUX_IPSR_GPSR(IP5_7_4,       CANFD1_RX),
 877         PINMUX_IPSR_MSEL(IP5_7_4,       IERX_A,                 SEL_IEBUS_0),
 878
 879         PINMUX_IPSR_MSEL(IP5_11_8,      EX_WAIT0_A,             SEL_LBSC_0),
 880         PINMUX_IPSR_GPSR(IP5_11_8,      QCLK),
 881         PINMUX_IPSR_GPSR(IP5_11_8,      VI4_CLK),
 882         PINMUX_IPSR_GPSR(IP5_11_8,      DU_DOTCLKOUT0),
 883
 884         PINMUX_IPSR_GPSR(IP5_15_12,     D0),
 885         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF2_SS1_B,           SEL_MSIOF2_1),
 886         PINMUX_IPSR_MSEL(IP5_15_12,     MSIOF3_SCK_A,           SEL_MSIOF3_0),
 887         PINMUX_IPSR_GPSR(IP5_15_12,     VI4_DATA16),
 888         PINMUX_IPSR_GPSR(IP5_15_12,     VI5_DATA0),
 889
 890         PINMUX_IPSR_GPSR(IP5_19_16,     D1),
 891         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF2_SS2_B,           SEL_MSIOF2_1),
 892         PINMUX_IPSR_MSEL(IP5_19_16,     MSIOF3_SYNC_A,          SEL_MSIOF3_0),
 893         PINMUX_IPSR_GPSR(IP5_19_16,     VI4_DATA17),
 894         PINMUX_IPSR_GPSR(IP5_19_16,     VI5_DATA1),
 895
 896         PINMUX_IPSR_GPSR(IP5_23_20,     D2),
 897         PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_RXD_A,           SEL_MSIOF3_0),
 898         PINMUX_IPSR_GPSR(IP5_23_20,     VI4_DATA18),
 899         PINMUX_IPSR_GPSR(IP5_23_20,     VI5_DATA2),
 900
 901         PINMUX_IPSR_GPSR(IP5_27_24,     D3),
 902         PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_TXD_A,           SEL_MSIOF3_0),
 903         PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA19),
 904         PINMUX_IPSR_GPSR(IP5_27_24,     VI5_DATA3),
 905
 906         PINMUX_IPSR_GPSR(IP5_31_28,     D4),
 907         PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF2_SCK_B,           SEL_MSIOF2_1),
 908         PINMUX_IPSR_GPSR(IP5_31_28,     VI4_DATA20),
 909         PINMUX_IPSR_GPSR(IP5_31_28,     VI5_DATA4),
 910
 911         /* IPSR6 */
 912         PINMUX_IPSR_GPSR(IP6_3_0,       D5),
 913         PINMUX_IPSR_MSEL(IP6_3_0,       MSIOF2_SYNC_B,          SEL_MSIOF2_1),
 914         PINMUX_IPSR_GPSR(IP6_3_0,       VI4_DATA21),
 915         PINMUX_IPSR_GPSR(IP6_3_0,       VI5_DATA5),
 916
 917         PINMUX_IPSR_GPSR(IP6_7_4,       D6),
 918         PINMUX_IPSR_MSEL(IP6_7_4,       MSIOF2_RXD_B,           SEL_MSIOF2_1),
 919         PINMUX_IPSR_GPSR(IP6_7_4,       VI4_DATA22),
 920         PINMUX_IPSR_GPSR(IP6_7_4,       VI5_DATA6),
 921
 922         PINMUX_IPSR_GPSR(IP6_11_8,      D7),
 923         PINMUX_IPSR_MSEL(IP6_11_8,      MSIOF2_TXD_B,           SEL_MSIOF2_1),
 924         PINMUX_IPSR_GPSR(IP6_11_8,      VI4_DATA23),
 925         PINMUX_IPSR_GPSR(IP6_11_8,      VI5_DATA7),
 926
 927         PINMUX_IPSR_GPSR(IP6_15_12,     D8),
 928         PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT0),
 929         PINMUX_IPSR_MSEL(IP6_15_12,     MSIOF2_SCK_D,           SEL_MSIOF2_3),
 930         PINMUX_IPSR_MSEL(IP6_15_12,     SCK4_C,                 SEL_SCIF4_2),
 931         PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA0_A,            SEL_VIN4_0),
 932         PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR0),
 933
 934         PINMUX_IPSR_GPSR(IP6_19_16,     D9),
 935         PINMUX_IPSR_GPSR(IP6_19_16,     LCDOUT1),
 936         PINMUX_IPSR_MSEL(IP6_19_16,     MSIOF2_SYNC_D,          SEL_MSIOF2_3),
 937         PINMUX_IPSR_MSEL(IP6_19_16,     VI4_DATA1_A,            SEL_VIN4_0),
 938         PINMUX_IPSR_GPSR(IP6_19_16,     DU_DR1),
 939
 940         PINMUX_IPSR_GPSR(IP6_23_20,     D10),
 941         PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT2),
 942         PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_RXD_D,           SEL_MSIOF2_3),
 943         PINMUX_IPSR_MSEL(IP6_23_20,     HRX3_B,                 SEL_HSCIF3_1),
 944         PINMUX_IPSR_MSEL(IP6_23_20,     VI4_DATA2_A,            SEL_VIN4_0),
 945         PINMUX_IPSR_MSEL(IP6_23_20,     CTS4_N_C,               SEL_SCIF4_2),
 946         PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR2),
 947
 948         PINMUX_IPSR_GPSR(IP6_27_24,     D11),
 949         PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT3),
 950         PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_TXD_D,           SEL_MSIOF2_3),
 951         PINMUX_IPSR_MSEL(IP6_27_24,     HTX3_B,                 SEL_HSCIF3_1),
 952         PINMUX_IPSR_MSEL(IP6_27_24,     VI4_DATA3_A,            SEL_VIN4_0),
 953         PINMUX_IPSR_MSEL(IP6_27_24,     RTS4_N_C,               SEL_SCIF4_2),
 954         PINMUX_IPSR_GPSR(IP6_27_24,     DU_DR3),
 955
 956         PINMUX_IPSR_GPSR(IP6_31_28,     D12),
 957         PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT4),
 958         PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_SS1_D,           SEL_MSIOF2_3),
 959         PINMUX_IPSR_MSEL(IP6_31_28,     RX4_C,                  SEL_SCIF4_2),
 960         PINMUX_IPSR_MSEL(IP6_31_28,     VI4_DATA4_A,            SEL_VIN4_0),
 961         PINMUX_IPSR_GPSR(IP6_31_28,     DU_DR4),
 962
 963         /* IPSR7 */
 964         PINMUX_IPSR_GPSR(IP7_3_0,       D13),
 965         PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT5),
 966         PINMUX_IPSR_MSEL(IP7_3_0,       MSIOF2_SS2_D,           SEL_MSIOF2_3),
 967         PINMUX_IPSR_MSEL(IP7_3_0,       TX4_C,                  SEL_SCIF4_2),
 968         PINMUX_IPSR_MSEL(IP7_3_0,       VI4_DATA5_A,            SEL_VIN4_0),
 969         PINMUX_IPSR_GPSR(IP7_3_0,       DU_DR5),
 970
 971         PINMUX_IPSR_GPSR(IP7_7_4,       D14),
 972         PINMUX_IPSR_GPSR(IP7_7_4,       LCDOUT6),
 973         PINMUX_IPSR_MSEL(IP7_7_4,       MSIOF3_SS1_A,           SEL_MSIOF3_0),
 974         PINMUX_IPSR_MSEL(IP7_7_4,       HRX3_C,                 SEL_HSCIF3_2),
 975         PINMUX_IPSR_MSEL(IP7_7_4,       VI4_DATA6_A,            SEL_VIN4_0),
 976         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR6),
 977         PINMUX_IPSR_MSEL(IP7_7_4,       SCL6_C,                 SEL_I2C6_2),
 978
 979         PINMUX_IPSR_GPSR(IP7_11_8,      D15),
 980         PINMUX_IPSR_GPSR(IP7_11_8,      LCDOUT7),
 981         PINMUX_IPSR_MSEL(IP7_11_8,      MSIOF3_SS2_A,           SEL_MSIOF3_0),
 982         PINMUX_IPSR_MSEL(IP7_11_8,      HTX3_C,                 SEL_HSCIF3_2),
 983         PINMUX_IPSR_MSEL(IP7_11_8,      VI4_DATA7_A,            SEL_VIN4_0),
 984         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR7),
 985         PINMUX_IPSR_MSEL(IP7_11_8,      SDA6_C,                 SEL_I2C6_2),
 986
 987         PINMUX_IPSR_GPSR(IP7_19_16,     SD0_CLK),
 988         PINMUX_IPSR_MSEL(IP7_19_16,     MSIOF1_SCK_E,           SEL_MSIOF1_4),
 989         PINMUX_IPSR_MSEL(IP7_19_16,     STP_OPWM_0_B,           SEL_SSP1_0_1),
 990
 991         PINMUX_IPSR_GPSR(IP7_23_20,     SD0_CMD),
 992         PINMUX_IPSR_MSEL(IP7_23_20,     MSIOF1_SYNC_E,          SEL_MSIOF1_4),
 993         PINMUX_IPSR_MSEL(IP7_23_20,     STP_IVCXO27_0_B,        SEL_SSP1_0_1),
 994
 995         PINMUX_IPSR_GPSR(IP7_27_24,     SD0_DAT0),
 996         PINMUX_IPSR_MSEL(IP7_27_24,     MSIOF1_RXD_E,           SEL_MSIOF1_4),
 997         PINMUX_IPSR_MSEL(IP7_27_24,     TS_SCK0_B,              SEL_TSIF0_1),
 998         PINMUX_IPSR_MSEL(IP7_27_24,     STP_ISCLK_0_B,          SEL_SSP1_0_1),
 999
1000         PINMUX_IPSR_GPSR(IP7_31_28,     SD0_DAT1),
1001         PINMUX_IPSR_MSEL(IP7_31_28,     MSIOF1_TXD_E,           SEL_MSIOF1_4),
1002         PINMUX_IPSR_MSEL(IP7_31_28,     TS_SPSYNC0_B,           SEL_TSIF0_1),
1003         PINMUX_IPSR_MSEL(IP7_31_28,     STP_ISSYNC_0_B,         SEL_SSP1_0_1),
1004
1005         /* IPSR8 */
1006         PINMUX_IPSR_GPSR(IP8_3_0,       SD0_DAT2),
1007         PINMUX_IPSR_MSEL(IP8_3_0,       MSIOF1_SS1_E,           SEL_MSIOF1_4),
1008         PINMUX_IPSR_MSEL(IP8_3_0,       TS_SDAT0_B,             SEL_TSIF0_1),
1009         PINMUX_IPSR_MSEL(IP8_3_0,       STP_ISD_0_B,            SEL_SSP1_0_1),
1010
1011         PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT3),
1012         PINMUX_IPSR_MSEL(IP8_7_4,       MSIOF1_SS2_E,           SEL_MSIOF1_4),
1013         PINMUX_IPSR_MSEL(IP8_7_4,       TS_SDEN0_B,             SEL_TSIF0_1),
1014         PINMUX_IPSR_MSEL(IP8_7_4,       STP_ISEN_0_B,           SEL_SSP1_0_1),
1015
1016         PINMUX_IPSR_GPSR(IP8_11_8,      SD1_CLK),
1017         PINMUX_IPSR_MSEL(IP8_11_8,      MSIOF1_SCK_G,           SEL_MSIOF1_6),
1018         PINMUX_IPSR_MSEL(IP8_11_8,      SIM0_CLK_A,             SEL_SIMCARD_0),
1019
1020         PINMUX_IPSR_GPSR(IP8_15_12,     SD1_CMD),
1021         PINMUX_IPSR_MSEL(IP8_15_12,     MSIOF1_SYNC_G,          SEL_MSIOF1_6),
1022         PINMUX_IPSR_MSEL(IP8_15_12,     NFCE_N_B,               SEL_NDFC_1),
1023         PINMUX_IPSR_MSEL(IP8_15_12,     SIM0_D_A,               SEL_SIMCARD_0),
1024         PINMUX_IPSR_MSEL(IP8_15_12,     STP_IVCXO27_1_B,        SEL_SSP1_1_1),
1025
1026         PINMUX_IPSR_GPSR(IP8_19_16,     SD1_DAT0),
1027         PINMUX_IPSR_GPSR(IP8_19_16,     SD2_DAT4),
1028         PINMUX_IPSR_MSEL(IP8_19_16,     MSIOF1_RXD_G,           SEL_MSIOF1_6),
1029         PINMUX_IPSR_MSEL(IP8_19_16,     NFWP_N_B,               SEL_NDFC_1),
1030         PINMUX_IPSR_MSEL(IP8_19_16,     TS_SCK1_B,              SEL_TSIF1_1),
1031         PINMUX_IPSR_MSEL(IP8_19_16,     STP_ISCLK_1_B,          SEL_SSP1_1_1),
1032
1033         PINMUX_IPSR_GPSR(IP8_23_20,     SD1_DAT1),
1034         PINMUX_IPSR_GPSR(IP8_23_20,     SD2_DAT5),
1035         PINMUX_IPSR_MSEL(IP8_23_20,     MSIOF1_TXD_G,           SEL_MSIOF1_6),
1036         PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B,             SEL_NDFC_1),
1037         PINMUX_IPSR_MSEL(IP8_23_20,     TS_SPSYNC1_B,           SEL_TSIF1_1),
1038         PINMUX_IPSR_MSEL(IP8_23_20,     STP_ISSYNC_1_B,         SEL_SSP1_1_1),
1039
1040         PINMUX_IPSR_GPSR(IP8_27_24,     SD1_DAT2),
1041         PINMUX_IPSR_GPSR(IP8_27_24,     SD2_DAT6),
1042         PINMUX_IPSR_MSEL(IP8_27_24,     MSIOF1_SS1_G,           SEL_MSIOF1_6),
1043         PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B,             SEL_NDFC_1),
1044         PINMUX_IPSR_MSEL(IP8_27_24,     TS_SDAT1_B,             SEL_TSIF1_1),
1045         PINMUX_IPSR_MSEL(IP8_27_24,     STP_ISD_1_B,            SEL_SSP1_1_1),
1046
1047         PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT3),
1048         PINMUX_IPSR_GPSR(IP8_31_28,     SD2_DAT7),
1049         PINMUX_IPSR_MSEL(IP8_31_28,     MSIOF1_SS2_G,           SEL_MSIOF1_6),
1050         PINMUX_IPSR_MSEL(IP8_31_28,     NFRB_N_B,               SEL_NDFC_1),
1051         PINMUX_IPSR_MSEL(IP8_31_28,     TS_SDEN1_B,             SEL_TSIF1_1),
1052         PINMUX_IPSR_MSEL(IP8_31_28,     STP_ISEN_1_B,           SEL_SSP1_1_1),
1053
1054         /* IPSR9 */
1055         PINMUX_IPSR_GPSR(IP9_3_0,       SD2_CLK),
1056         PINMUX_IPSR_GPSR(IP9_3_0,       NFDATA8),
1057
1058         PINMUX_IPSR_GPSR(IP9_7_4,       SD2_CMD),
1059         PINMUX_IPSR_GPSR(IP9_7_4,       NFDATA9),
1060
1061         PINMUX_IPSR_GPSR(IP9_11_8,      SD2_DAT0),
1062         PINMUX_IPSR_GPSR(IP9_11_8,      NFDATA10),
1063
1064         PINMUX_IPSR_GPSR(IP9_15_12,     SD2_DAT1),
1065         PINMUX_IPSR_GPSR(IP9_15_12,     NFDATA11),
1066
1067         PINMUX_IPSR_GPSR(IP9_19_16,     SD2_DAT2),
1068         PINMUX_IPSR_GPSR(IP9_19_16,     NFDATA12),
1069
1070         PINMUX_IPSR_GPSR(IP9_23_20,     SD2_DAT3),
1071         PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA13),
1072
1073         PINMUX_IPSR_GPSR(IP9_27_24,     SD2_DS),
1074         PINMUX_IPSR_GPSR(IP9_27_24,     NFALE),
1075         PINMUX_IPSR_GPSR(IP9_27_24,     SATA_DEVSLP_B),
1076
1077         PINMUX_IPSR_GPSR(IP9_31_28,     SD3_CLK),
1078         PINMUX_IPSR_GPSR(IP9_31_28,     NFWE_N),
1079
1080         /* IPSR10 */
1081         PINMUX_IPSR_GPSR(IP10_3_0,      SD3_CMD),
1082         PINMUX_IPSR_GPSR(IP10_3_0,      NFRE_N),
1083
1084         PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT0),
1085         PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA0),
1086
1087         PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT1),
1088         PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA1),
1089
1090         PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1091         PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1092
1093         PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1094         PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1095
1096         PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1097         PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,               SEL_SDHI2_0),
1098         PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1099
1100         PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1101         PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,               SEL_SDHI2_0),
1102         PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1103
1104         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1105         PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1106         PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1107
1108         /* IPSR11 */
1109         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_DAT7),
1110         PINMUX_IPSR_GPSR(IP11_3_0,      SD3_WP),
1111         PINMUX_IPSR_GPSR(IP11_3_0,      NFDATA7),
1112
1113         PINMUX_IPSR_GPSR(IP11_7_4,      SD3_DS),
1114         PINMUX_IPSR_GPSR(IP11_7_4,      NFCLE),
1115
1116         PINMUX_IPSR_GPSR(IP11_11_8,     SD0_CD),
1117         PINMUX_IPSR_MSEL(IP11_11_8,     NFDATA14_A,             SEL_NDFC_0),
1118         PINMUX_IPSR_MSEL(IP11_11_8,     SCL2_B,                 SEL_I2C2_1),
1119         PINMUX_IPSR_MSEL(IP11_11_8,     SIM0_RST_A,             SEL_SIMCARD_0),
1120
1121         PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1122         PINMUX_IPSR_MSEL(IP11_15_12,    NFDATA15_A,             SEL_NDFC_0),
1123         PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,                 SEL_I2C2_1),
1124
1125         PINMUX_IPSR_GPSR(IP11_19_16,    SD1_CD),
1126         PINMUX_IPSR_MSEL(IP11_19_16,    NFRB_N_A,               SEL_NDFC_0),
1127         PINMUX_IPSR_MSEL(IP11_19_16,    SIM0_CLK_B,             SEL_SIMCARD_1),
1128
1129         PINMUX_IPSR_GPSR(IP11_23_20,    SD1_WP),
1130         PINMUX_IPSR_MSEL(IP11_23_20,    NFCE_N_A,               SEL_NDFC_0),
1131         PINMUX_IPSR_MSEL(IP11_23_20,    SIM0_D_B,               SEL_SIMCARD_1),
1132
1133         PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1134         PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,                SEL_HSCIF1_1),
1135         PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,           SEL_MSIOF1_1),
1136         PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,           SEL_ADG_C_1),
1137         PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,                 SEL_I2C2_0),
1138         PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,             SEL_SIMCARD_1),
1139         PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,           SEL_SSP1_0_2),
1140         PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,             SEL_DRIF0_1),
1141         PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1142         PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,                 SEL_SCIF5_1),
1143
1144         PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1145         PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,                 SEL_HSCIF1_1),
1146         PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,              SEL_TSIF0_2),
1147         PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,          SEL_SSP1_0_2),
1148         PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,              SEL_DRIF0_1),
1149
1150         /* IPSR12 */
1151         PINMUX_IPSR_GPSR(IP12_3_0,      TX0),
1152         PINMUX_IPSR_MSEL(IP12_3_0,      HTX1_B,                 SEL_HSCIF1_1),
1153         PINMUX_IPSR_MSEL(IP12_3_0,      TS_SPSYNC0_C,           SEL_TSIF0_2),
1154         PINMUX_IPSR_MSEL(IP12_3_0,      STP_ISSYNC_0_C,         SEL_SSP1_0_2),
1155         PINMUX_IPSR_MSEL(IP12_3_0,      RIF0_D1_B,              SEL_DRIF0_1),
1156
1157         PINMUX_IPSR_GPSR(IP12_7_4,      CTS0_N),
1158         PINMUX_IPSR_MSEL(IP12_7_4,      HCTS1_N_B,              SEL_HSCIF1_1),
1159         PINMUX_IPSR_MSEL(IP12_7_4,      MSIOF1_SYNC_B,          SEL_MSIOF1_1),
1160         PINMUX_IPSR_MSEL(IP12_7_4,      TS_SPSYNC1_C,           SEL_TSIF1_2),
1161         PINMUX_IPSR_MSEL(IP12_7_4,      STP_ISSYNC_1_C,         SEL_SSP1_1_2),
1162         PINMUX_IPSR_MSEL(IP12_7_4,      RIF1_SYNC_B,            SEL_DRIF1_1),
1163         PINMUX_IPSR_GPSR(IP12_7_4,      AUDIO_CLKOUT_C),
1164         PINMUX_IPSR_GPSR(IP12_7_4,      ADICS_SAMP),
1165
1166         PINMUX_IPSR_GPSR(IP12_11_8,     RTS0_N),
1167         PINMUX_IPSR_MSEL(IP12_11_8,     HRTS1_N_B,              SEL_HSCIF1_1),
1168         PINMUX_IPSR_MSEL(IP12_11_8,     MSIOF1_SS1_B,           SEL_MSIOF1_1),
1169         PINMUX_IPSR_MSEL(IP12_11_8,     AUDIO_CLKA_B,           SEL_ADG_A_1),
1170         PINMUX_IPSR_MSEL(IP12_11_8,     SCL2_A,                 SEL_I2C2_0),
1171         PINMUX_IPSR_MSEL(IP12_11_8,     STP_IVCXO27_1_C,        SEL_SSP1_1_2),
1172         PINMUX_IPSR_MSEL(IP12_11_8,     RIF0_SYNC_B,            SEL_DRIF0_1),
1173         PINMUX_IPSR_GPSR(IP12_11_8,     ADICHS1),
1174
1175         PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,                  SEL_SCIF1_0),
1176         PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,                 SEL_HSCIF1_0),
1177         PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,             SEL_TSIF0_2),
1178         PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,            SEL_SSP1_0_2),
1179         PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,             SEL_DRIF1_2),
1180
1181         PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,                  SEL_SCIF1_0),
1182         PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,                 SEL_HSCIF1_0),
1183         PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,             SEL_TSIF0_2),
1184         PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,           SEL_SSP1_0_2),
1185         PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,              SEL_DRIF1_2),
1186
1187         PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1188         PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,              SEL_HSCIF1_0),
1189         PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,           SEL_MSIOF1_1),
1190         PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,             SEL_TSIF1_2),
1191         PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,           SEL_SSP1_1_2),
1192         PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,              SEL_DRIF1_1),
1193         PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1194
1195         PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1196         PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,              SEL_HSCIF1_0),
1197         PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,           SEL_MSIOF1_1),
1198         PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,             SEL_TSIF1_2),
1199         PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,            SEL_SSP1_1_2),
1200         PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,              SEL_DRIF1_1),
1201         PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1202
1203         PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1204         PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,             SEL_SCIF_1),
1205         PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,           SEL_MSIOF1_1),
1206         PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,              SEL_TSIF1_2),
1207         PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,          SEL_SSP1_1_2),
1208         PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,             SEL_DRIF1_1),
1209         PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1210
1211         /* IPSR13 */
1212         PINMUX_IPSR_MSEL(IP13_3_0,      TX2_A,                  SEL_SCIF2_0),
1213         PINMUX_IPSR_MSEL(IP13_3_0,      SD2_CD_B,               SEL_SDHI2_1),
1214         PINMUX_IPSR_MSEL(IP13_3_0,      SCL1_A,                 SEL_I2C1_0),
1215         PINMUX_IPSR_MSEL(IP13_3_0,      FMCLK_A,                SEL_FM_0),
1216         PINMUX_IPSR_MSEL(IP13_3_0,      RIF1_D1_C,              SEL_DRIF1_2),
1217         PINMUX_IPSR_GPSR(IP13_3_0,      FSO_CFE_0_N),
1218
1219         PINMUX_IPSR_MSEL(IP13_7_4,      RX2_A,                  SEL_SCIF2_0),
1220         PINMUX_IPSR_MSEL(IP13_7_4,      SD2_WP_B,               SEL_SDHI2_1),
1221         PINMUX_IPSR_MSEL(IP13_7_4,      SDA1_A,                 SEL_I2C1_0),
1222         PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_A,                 SEL_FM_0),
1223         PINMUX_IPSR_MSEL(IP13_7_4,      RIF1_SYNC_C,            SEL_DRIF1_2),
1224         PINMUX_IPSR_GPSR(IP13_7_4,      FSO_CFE_1_N),
1225
1226         PINMUX_IPSR_GPSR(IP13_11_8,     HSCK0),
1227         PINMUX_IPSR_MSEL(IP13_11_8,     MSIOF1_SCK_D,           SEL_MSIOF1_3),
1228         PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKB_A,           SEL_ADG_B_0),
1229         PINMUX_IPSR_MSEL(IP13_11_8,     SSI_SDATA1_B,           SEL_SSI1_1),
1230         PINMUX_IPSR_MSEL(IP13_11_8,     TS_SCK0_D,              SEL_TSIF0_3),
1231         PINMUX_IPSR_MSEL(IP13_11_8,     STP_ISCLK_0_D,          SEL_SSP1_0_3),
1232         PINMUX_IPSR_MSEL(IP13_11_8,     RIF0_CLK_C,             SEL_DRIF0_2),
1233         PINMUX_IPSR_MSEL(IP13_11_8,     RX5_B,                  SEL_SCIF5_1),
1234
1235         PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1236         PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,           SEL_MSIOF1_3),
1237         PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,           SEL_SSI2_1),
1238         PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,             SEL_TSIF0_3),
1239         PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,           SEL_SSP1_0_3),
1240         PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,              SEL_DRIF0_2),
1241
1242         PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1243         PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,           SEL_MSIOF1_3),
1244         PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,           SEL_SSI9_1),
1245         PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,             SEL_TSIF0_3),
1246         PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,            SEL_SSP1_0_3),
1247         PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,              SEL_DRIF0_2),
1248
1249         PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1250         PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,                  SEL_SCIF2_1),
1251         PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,          SEL_MSIOF1_3),
1252         PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,             SEL_SSI9_0),
1253         PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,           SEL_TSIF0_3),
1254         PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,         SEL_SSP1_0_3),
1255         PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,            SEL_DRIF0_2),
1256         PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1257
1258         PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1259         PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,                  SEL_SCIF2_1),
1260         PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,           SEL_MSIOF1_3),
1261         PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,              SEL_SSI9_0),
1262         PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,        SEL_SSP1_0_3),
1263         PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,               SEL_FM_0),
1264         PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1265
1266         PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1267         PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1268         PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,                  SEL_SCIF5_1),
1269         PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,               SEL_FM_3),
1270
1271         /* IPSR14 */
1272         PINMUX_IPSR_GPSR(IP14_3_0,      MSIOF0_SS1),
1273         PINMUX_IPSR_MSEL(IP14_3_0,      RX5_A,                  SEL_SCIF5_0),
1274         PINMUX_IPSR_MSEL(IP14_3_0,      NFWP_N_A,               SEL_NDFC_0),
1275         PINMUX_IPSR_MSEL(IP14_3_0,      AUDIO_CLKA_C,           SEL_ADG_A_2),
1276         PINMUX_IPSR_MSEL(IP14_3_0,      SSI_SCK2_A,             SEL_SSI2_0),
1277         PINMUX_IPSR_MSEL(IP14_3_0,      STP_IVCXO27_0_C,        SEL_SSP1_0_2),
1278         PINMUX_IPSR_GPSR(IP14_3_0,      AUDIO_CLKOUT3_A),
1279         PINMUX_IPSR_MSEL(IP14_3_0,      TCLK1_B,                SEL_TIMER_TMU_1),
1280
1281         PINMUX_IPSR_GPSR(IP14_7_4,      MSIOF0_SS2),
1282         PINMUX_IPSR_MSEL(IP14_7_4,      TX5_A,                  SEL_SCIF5_0),
1283         PINMUX_IPSR_MSEL(IP14_7_4,      MSIOF1_SS2_D,           SEL_MSIOF1_3),
1284         PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_A,           SEL_ADG_C_0),
1285         PINMUX_IPSR_MSEL(IP14_7_4,      SSI_WS2_A,              SEL_SSI2_0),
1286         PINMUX_IPSR_MSEL(IP14_7_4,      STP_OPWM_0_D,           SEL_SSP1_0_3),
1287         PINMUX_IPSR_GPSR(IP14_7_4,      AUDIO_CLKOUT_D),
1288         PINMUX_IPSR_MSEL(IP14_7_4,      SPEEDIN_B,              SEL_SPEED_PULSE_1),
1289
1290         PINMUX_IPSR_GPSR(IP14_11_8,     MLB_CLK),
1291         PINMUX_IPSR_MSEL(IP14_11_8,     MSIOF1_SCK_F,           SEL_MSIOF1_5),
1292         PINMUX_IPSR_MSEL(IP14_11_8,     SCL1_B,                 SEL_I2C1_1),
1293
1294         PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1295         PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,                  SEL_SCIF1_1),
1296         PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,          SEL_MSIOF1_5),
1297         PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,                 SEL_I2C1_1),
1298
1299         PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1300         PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,                  SEL_SCIF1_1),
1301         PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,           SEL_MSIOF1_5),
1302
1303         PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1304         PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,           SEL_MSIOF1_5),
1305
1306         PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1307         PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,           SEL_MSIOF1_5),
1308
1309         PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1310         PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,           SEL_MSIOF1_5),
1311
1312         /* IPSR15 */
1313         PINMUX_IPSR_MSEL(IP15_3_0,      SSI_SDATA1_A,           SEL_SSI1_0),
1314
1315         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SDATA2_A,           SEL_SSI2_0),
1316         PINMUX_IPSR_MSEL(IP15_7_4,      SSI_SCK1_B,             SEL_SSI1_1),
1317
1318         PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK349),
1319         PINMUX_IPSR_MSEL(IP15_11_8,     MSIOF1_SS1_A,           SEL_MSIOF1_0),
1320         PINMUX_IPSR_MSEL(IP15_11_8,     STP_OPWM_0_A,           SEL_SSP1_0_0),
1321
1322         PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1323         PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,              SEL_HSCIF2_0),
1324         PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,           SEL_MSIOF1_0),
1325         PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,        SEL_SSP1_0_0),
1326
1327         PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1328         PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,              SEL_HSCIF2_0),
1329         PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,           SEL_MSIOF1_0),
1330         PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,              SEL_TSIF0_0),
1331         PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,          SEL_SSP1_0_0),
1332         PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,              SEL_DRIF0_0),
1333         PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,              SEL_DRIF2_0),
1334
1335         PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1336         PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,                 SEL_HSCIF2_0),
1337         PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,           SEL_MSIOF1_0),
1338         PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,             SEL_TSIF0_0),
1339         PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,            SEL_SSP1_0_0),
1340         PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,             SEL_DRIF0_0),
1341         PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,             SEL_DRIF2_0),
1342
1343         PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1344         PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,                 SEL_HSCIF2_0),
1345         PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,          SEL_MSIOF1_0),
1346         PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,             SEL_TSIF0_0),
1347         PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,           SEL_SSP1_0_0),
1348         PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,            SEL_DRIF0_0),
1349         PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,            SEL_DRIF2_0),
1350
1351         PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1352         PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,                SEL_HSCIF2_0),
1353         PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,           SEL_MSIOF1_0),
1354         PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,           SEL_TSIF0_0),
1355         PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,         SEL_SSP1_0_0),
1356         PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,              SEL_DRIF0_0),
1357         PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,              SEL_DRIF2_0),
1358
1359         /* IPSR16 */
1360         PINMUX_IPSR_GPSR(IP16_3_0,      SSI_SCK6),
1361         PINMUX_IPSR_MSEL(IP16_3_0,      SIM0_RST_D,             SEL_SIMCARD_3),
1362
1363         PINMUX_IPSR_GPSR(IP16_7_4,      SSI_WS6),
1364         PINMUX_IPSR_MSEL(IP16_7_4,      SIM0_D_D,               SEL_SIMCARD_3),
1365
1366         PINMUX_IPSR_GPSR(IP16_11_8,     SSI_SDATA6),
1367         PINMUX_IPSR_MSEL(IP16_11_8,     SIM0_CLK_D,             SEL_SIMCARD_3),
1368         PINMUX_IPSR_GPSR(IP16_11_8,     SATA_DEVSLP_A),
1369
1370         PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1371         PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,                 SEL_HSCIF2_1),
1372         PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,           SEL_MSIOF1_2),
1373         PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,              SEL_TSIF1_0),
1374         PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,          SEL_SSP1_1_0),
1375         PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,             SEL_DRIF1_0),
1376         PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,             SEL_DRIF3_0),
1377
1378         PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1379         PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,                 SEL_HSCIF2_1),
1380         PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,          SEL_MSIOF1_2),
1381         PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,             SEL_TSIF1_0),
1382         PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,            SEL_SSP1_1_0),
1383         PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,            SEL_DRIF1_0),
1384         PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,            SEL_DRIF3_0),
1385
1386         PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1387         PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,              SEL_HSCIF2_1),
1388         PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,           SEL_MSIOF1_2),
1389         PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,             SEL_TSIF1_0),
1390         PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,           SEL_SSP1_1_0),
1391         PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,              SEL_DRIF1_0),
1392         PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,              SEL_DRIF3_0),
1393         PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,                SEL_TIMER_TMU2_0),
1394
1395         PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1396         PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,              SEL_HSCIF2_1),
1397         PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,           SEL_MSIOF1_2),
1398         PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,           SEL_TSIF1_0),
1399         PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,         SEL_SSP1_1_0),
1400         PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,              SEL_DRIF1_0),
1401         PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,              SEL_DRIF3_0),
1402
1403         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,           SEL_SSI9_0),
1404         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,                SEL_HSCIF2_1),
1405         PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,           SEL_MSIOF1_2),
1406         PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,                SEL_HSCIF1_0),
1407         PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,              SEL_SSI1_1),
1408         PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1409         PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,        SEL_SSP1_1_0),
1410         PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,                 SEL_SCIF5_0),
1411
1412         /* IPSR17 */
1413         PINMUX_IPSR_MSEL(IP17_3_0,      AUDIO_CLKA_A,           SEL_ADG_A_0),
1414         PINMUX_IPSR_GPSR(IP17_3_0,      CC5_OSCOUT),
1415
1416         PINMUX_IPSR_MSEL(IP17_7_4,      AUDIO_CLKB_B,           SEL_ADG_B_1),
1417         PINMUX_IPSR_MSEL(IP17_7_4,      SCIF_CLK_A,             SEL_SCIF_0),
1418         PINMUX_IPSR_MSEL(IP17_7_4,      STP_IVCXO27_1_D,        SEL_SSP1_1_3),
1419         PINMUX_IPSR_MSEL(IP17_7_4,      REMOCON_A,              SEL_REMOCON_0),
1420         PINMUX_IPSR_MSEL(IP17_7_4,      TCLK1_A,                SEL_TIMER_TMU_0),
1421
1422         PINMUX_IPSR_GPSR(IP17_11_8,     USB0_PWEN),
1423         PINMUX_IPSR_MSEL(IP17_11_8,     SIM0_RST_C,             SEL_SIMCARD_2),
1424         PINMUX_IPSR_MSEL(IP17_11_8,     TS_SCK1_D,              SEL_TSIF1_3),
1425         PINMUX_IPSR_MSEL(IP17_11_8,     STP_ISCLK_1_D,          SEL_SSP1_1_3),
1426         PINMUX_IPSR_MSEL(IP17_11_8,     BPFCLK_B,               SEL_FM_1),
1427         PINMUX_IPSR_MSEL(IP17_11_8,     RIF3_CLK_B,             SEL_DRIF3_1),
1428         PINMUX_IPSR_MSEL(IP17_11_8,     HSCK2_C,                SEL_HSCIF2_2),
1429
1430         PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1431         PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,               SEL_SIMCARD_2),
1432         PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,             SEL_TSIF1_3),
1433         PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,            SEL_SSP1_1_3),
1434         PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,            SEL_DRIF3_1),
1435         PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,                 SEL_HSCIF2_2),
1436
1437         PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1438         PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,             SEL_SIMCARD_2),
1439         PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,             SEL_SSI1_0),
1440         PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,              SEL_TSIF0_4),
1441         PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,          SEL_SSP1_0_4),
1442         PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,                SEL_FM_1),
1443         PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,             SEL_DRIF2_1),
1444         PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,              SEL_SPEED_PULSE_0),
1445         PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,                 SEL_HSCIF2_2),
1446
1447         PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1448         PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,           SEL_MSIOF1_2),
1449         PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,              SEL_SSI1_0),
1450         PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,             SEL_TSIF0_4),
1451         PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,            SEL_SSP1_0_4),
1452         PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,                 SEL_FM_1),
1453         PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,            SEL_DRIF2_1),
1454         PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,              SEL_REMOCON_1),
1455         PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,              SEL_HSCIF2_2),
1456
1457         PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1458         PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1459         PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,             SEL_SSI2_1),
1460         PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,             SEL_TSIF1_3),
1461         PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,           SEL_SSP1_1_3),
1462         PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,           SEL_SSP1_0_4),
1463         PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,              SEL_DRIF3_1),
1464         PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,                SEL_TIMER_TMU2_1),
1465         PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1466         PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,               SEL_FM_2),
1467         PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,              SEL_HSCIF2_2),
1468
1469         PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1470         PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1471         PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,              SEL_SSI2_1),
1472         PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,           SEL_TSIF1_3),
1473         PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,         SEL_SSP1_1_3),
1474         PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,        SEL_SSP1_0_4),
1475         PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,              SEL_DRIF3_1),
1476         PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1477         PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1478
1479         /* IPSR18 */
1480         PINMUX_IPSR_GPSR(IP18_3_0,      GP6_30),
1481         PINMUX_IPSR_GPSR(IP18_3_0,      AUDIO_CLKOUT2_B),
1482         PINMUX_IPSR_MSEL(IP18_3_0,      SSI_SCK9_B,             SEL_SSI9_1),
1483         PINMUX_IPSR_MSEL(IP18_3_0,      TS_SDEN0_E,             SEL_TSIF0_4),
1484         PINMUX_IPSR_MSEL(IP18_3_0,      STP_ISEN_0_E,           SEL_SSP1_0_4),
1485         PINMUX_IPSR_MSEL(IP18_3_0,      RIF2_D0_B,              SEL_DRIF2_1),
1486         PINMUX_IPSR_GPSR(IP18_3_0,      TPU0TO2),
1487         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_C,                SEL_FM_2),
1488         PINMUX_IPSR_MSEL(IP18_3_0,      FMCLK_D,                SEL_FM_3),
1489
1490         PINMUX_IPSR_GPSR(IP18_7_4,      GP6_31),
1491         PINMUX_IPSR_GPSR(IP18_7_4,      AUDIO_CLKOUT3_B),
1492         PINMUX_IPSR_MSEL(IP18_7_4,      SSI_WS9_B,              SEL_SSI9_1),
1493         PINMUX_IPSR_MSEL(IP18_7_4,      TS_SPSYNC0_E,           SEL_TSIF0_4),
1494         PINMUX_IPSR_MSEL(IP18_7_4,      STP_ISSYNC_0_E,         SEL_SSP1_0_4),
1495         PINMUX_IPSR_MSEL(IP18_7_4,      RIF2_D1_B,              SEL_DRIF2_1),
1496         PINMUX_IPSR_GPSR(IP18_7_4,      TPU0TO3),
1497         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_C,                 SEL_FM_2),
1498         PINMUX_IPSR_MSEL(IP18_7_4,      FMIN_D,                 SEL_FM_3),
1499
1500         /* I2C */
1501         PINMUX_IPSR_NOGP(0,             I2C_SEL_0_1),
1502         PINMUX_IPSR_NOGP(0,             I2C_SEL_3_1),
1503         PINMUX_IPSR_NOGP(0,             I2C_SEL_5_1),
1504
1505 /*
1506  * Static pins can not be muxed between different functions but
1507  * still need mark entries in the pinmux list. Add each static
1508  * pin to the list without an associated function. The sh-pfc
1509  * core will do the right thing and skip trying to mux the pin
1510  * while still applying configuration to it.
1511  */
1512 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1513         PINMUX_STATIC
1514 #undef FM
1515 };
1516
1517 /*
1518  * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1519  * Physical layout rows: A - AW, cols: 1 - 39.
1520  */
1521 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1522 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1523 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1524 #define PIN_NONE U16_MAX
1525
1526 static const struct sh_pfc_pin pinmux_pins[] = {
1527         PINMUX_GPIO_GP_ALL(),
1528
1529         /*
1530          * Pins not associated with a GPIO port.
1531          *
1532          * The pin positions are different between different r8a77965
1533          * packages, all that is needed for the pfc driver is a unique
1534          * number for each pin. To this end use the pin layout from
1535          * R-Car M3SiP to calculate a unique number for each pin.
1536          */
1537         SH_PFC_PIN_NAMED_CFG('A',  8, AVB_TX_CTL, CFG_FLAGS),
1538         SH_PFC_PIN_NAMED_CFG('A',  9, AVB_MDIO, CFG_FLAGS),
1539         SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1540         SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1541         SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1542         SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1543         SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1544         SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1545         SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1546         SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1547         SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1548         SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1549         SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1550         SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1551         SH_PFC_PIN_NAMED_CFG('C',  1, PRESETOUT#, CFG_FLAGS),
1552         SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1553         SH_PFC_PIN_NAMED_CFG('V',  3, QSPI1_SPCLK, CFG_FLAGS),
1554         SH_PFC_PIN_NAMED_CFG('V',  5, QSPI1_SSL, CFG_FLAGS),
1555         SH_PFC_PIN_NAMED_CFG('V',  6, RPC_WP#, CFG_FLAGS),
1556         SH_PFC_PIN_NAMED_CFG('V',  7, RPC_RESET#, CFG_FLAGS),
1557         SH_PFC_PIN_NAMED_CFG('W',  3, QSPI0_SPCLK, CFG_FLAGS),
1558         SH_PFC_PIN_NAMED_CFG('Y',  3, QSPI0_SSL, CFG_FLAGS),
1559         SH_PFC_PIN_NAMED_CFG('Y',  6, QSPI0_IO2, CFG_FLAGS),
1560         SH_PFC_PIN_NAMED_CFG('Y',  7, RPC_INT#, CFG_FLAGS),
1561         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  4, QSPI0_MISO_IO1, CFG_FLAGS),
1562         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'),  6, QSPI0_IO3, CFG_FLAGS),
1563         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  3, QSPI1_IO3, CFG_FLAGS),
1564         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  5, QSPI0_MOSI_IO0, CFG_FLAGS),
1565         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'),  7, QSPI1_MOSI_IO0, CFG_FLAGS),
1566         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1567         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  4, QSPI1_IO2, CFG_FLAGS),
1569         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'),  5, QSPI1_MISO_IO1, CFG_FLAGS),
1570         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  7, DU_DOTCLKIN0, CFG_FLAGS),
1571         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'),  8, DU_DOTCLKIN1, CFG_FLAGS),
1572         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'),  8, DU_DOTCLKIN3, CFG_FLAGS),
1573         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1575         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1576         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1577         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1578         SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1579 };
1580
1581 /* - AUDIO CLOCK ------------------------------------------------------------ */
1582 static const unsigned int audio_clk_a_a_pins[] = {
1583         /* CLK A */
1584         RCAR_GP_PIN(6, 22),
1585 };
1586 static const unsigned int audio_clk_a_a_mux[] = {
1587         AUDIO_CLKA_A_MARK,
1588 };
1589 static const unsigned int audio_clk_a_b_pins[] = {
1590         /* CLK A */
1591         RCAR_GP_PIN(5, 4),
1592 };
1593 static const unsigned int audio_clk_a_b_mux[] = {
1594         AUDIO_CLKA_B_MARK,
1595 };
1596 static const unsigned int audio_clk_a_c_pins[] = {
1597         /* CLK A */
1598         RCAR_GP_PIN(5, 19),
1599 };
1600 static const unsigned int audio_clk_a_c_mux[] = {
1601         AUDIO_CLKA_C_MARK,
1602 };
1603 static const unsigned int audio_clk_b_a_pins[] = {
1604         /* CLK B */
1605         RCAR_GP_PIN(5, 12),
1606 };
1607 static const unsigned int audio_clk_b_a_mux[] = {
1608         AUDIO_CLKB_A_MARK,
1609 };
1610 static const unsigned int audio_clk_b_b_pins[] = {
1611         /* CLK B */
1612         RCAR_GP_PIN(6, 23),
1613 };
1614 static const unsigned int audio_clk_b_b_mux[] = {
1615         AUDIO_CLKB_B_MARK,
1616 };
1617 static const unsigned int audio_clk_c_a_pins[] = {
1618         /* CLK C */
1619         RCAR_GP_PIN(5, 21),
1620 };
1621 static const unsigned int audio_clk_c_a_mux[] = {
1622         AUDIO_CLKC_A_MARK,
1623 };
1624 static const unsigned int audio_clk_c_b_pins[] = {
1625         /* CLK C */
1626         RCAR_GP_PIN(5, 0),
1627 };
1628 static const unsigned int audio_clk_c_b_mux[] = {
1629         AUDIO_CLKC_B_MARK,
1630 };
1631 static const unsigned int audio_clkout_a_pins[] = {
1632         /* CLKOUT */
1633         RCAR_GP_PIN(5, 18),
1634 };
1635 static const unsigned int audio_clkout_a_mux[] = {
1636         AUDIO_CLKOUT_A_MARK,
1637 };
1638 static const unsigned int audio_clkout_b_pins[] = {
1639         /* CLKOUT */
1640         RCAR_GP_PIN(6, 28),
1641 };
1642 static const unsigned int audio_clkout_b_mux[] = {
1643         AUDIO_CLKOUT_B_MARK,
1644 };
1645 static const unsigned int audio_clkout_c_pins[] = {
1646         /* CLKOUT */
1647         RCAR_GP_PIN(5, 3),
1648 };
1649 static const unsigned int audio_clkout_c_mux[] = {
1650         AUDIO_CLKOUT_C_MARK,
1651 };
1652 static const unsigned int audio_clkout_d_pins[] = {
1653         /* CLKOUT */
1654         RCAR_GP_PIN(5, 21),
1655 };
1656 static const unsigned int audio_clkout_d_mux[] = {
1657         AUDIO_CLKOUT_D_MARK,
1658 };
1659 static const unsigned int audio_clkout1_a_pins[] = {
1660         /* CLKOUT1 */
1661         RCAR_GP_PIN(5, 15),
1662 };
1663 static const unsigned int audio_clkout1_a_mux[] = {
1664         AUDIO_CLKOUT1_A_MARK,
1665 };
1666 static const unsigned int audio_clkout1_b_pins[] = {
1667         /* CLKOUT1 */
1668         RCAR_GP_PIN(6, 29),
1669 };
1670 static const unsigned int audio_clkout1_b_mux[] = {
1671         AUDIO_CLKOUT1_B_MARK,
1672 };
1673 static const unsigned int audio_clkout2_a_pins[] = {
1674         /* CLKOUT2 */
1675         RCAR_GP_PIN(5, 16),
1676 };
1677 static const unsigned int audio_clkout2_a_mux[] = {
1678         AUDIO_CLKOUT2_A_MARK,
1679 };
1680 static const unsigned int audio_clkout2_b_pins[] = {
1681         /* CLKOUT2 */
1682         RCAR_GP_PIN(6, 30),
1683 };
1684 static const unsigned int audio_clkout2_b_mux[] = {
1685         AUDIO_CLKOUT2_B_MARK,
1686 };
1687
1688 static const unsigned int audio_clkout3_a_pins[] = {
1689         /* CLKOUT3 */
1690         RCAR_GP_PIN(5, 19),
1691 };
1692 static const unsigned int audio_clkout3_a_mux[] = {
1693         AUDIO_CLKOUT3_A_MARK,
1694 };
1695 static const unsigned int audio_clkout3_b_pins[] = {
1696         /* CLKOUT3 */
1697         RCAR_GP_PIN(6, 31),
1698 };
1699 static const unsigned int audio_clkout3_b_mux[] = {
1700         AUDIO_CLKOUT3_B_MARK,
1701 };
1702
1703 /* - EtherAVB --------------------------------------------------------------- */
1704 static const unsigned int avb_link_pins[] = {
1705         /* AVB_LINK */
1706         RCAR_GP_PIN(2, 12),
1707 };
1708 static const unsigned int avb_link_mux[] = {
1709         AVB_LINK_MARK,
1710 };
1711 static const unsigned int avb_magic_pins[] = {
1712         /* AVB_MAGIC_ */
1713         RCAR_GP_PIN(2, 10),
1714 };
1715 static const unsigned int avb_magic_mux[] = {
1716         AVB_MAGIC_MARK,
1717 };
1718 static const unsigned int avb_phy_int_pins[] = {
1719         /* AVB_PHY_INT */
1720         RCAR_GP_PIN(2, 11),
1721 };
1722 static const unsigned int avb_phy_int_mux[] = {
1723         AVB_PHY_INT_MARK,
1724 };
1725 static const unsigned int avb_mdio_pins[] = {
1726         /* AVB_MDC, AVB_MDIO */
1727         RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1728 };
1729 static const unsigned int avb_mdio_mux[] = {
1730         AVB_MDC_MARK, AVB_MDIO_MARK,
1731 };
1732 static const unsigned int avb_mii_pins[] = {
1733         /*
1734          * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1735          * AVB_TD1, AVB_TD2, AVB_TD3,
1736          * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1737          * AVB_RD1, AVB_RD2, AVB_RD3,
1738          * AVB_TXCREFCLK
1739          */
1740         PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1741         PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1742         PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1743         PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1744         PIN_NUMBER('A', 12),
1745
1746 };
1747 static const unsigned int avb_mii_mux[] = {
1748         AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1749         AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1750         AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1751         AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1752         AVB_TXCREFCLK_MARK,
1753 };
1754 static const unsigned int avb_avtp_pps_pins[] = {
1755         /* AVB_AVTP_PPS */
1756         RCAR_GP_PIN(2, 6),
1757 };
1758 static const unsigned int avb_avtp_pps_mux[] = {
1759         AVB_AVTP_PPS_MARK,
1760 };
1761 static const unsigned int avb_avtp_match_a_pins[] = {
1762         /* AVB_AVTP_MATCH_A */
1763         RCAR_GP_PIN(2, 13),
1764 };
1765 static const unsigned int avb_avtp_match_a_mux[] = {
1766         AVB_AVTP_MATCH_A_MARK,
1767 };
1768 static const unsigned int avb_avtp_capture_a_pins[] = {
1769         /* AVB_AVTP_CAPTURE_A */
1770         RCAR_GP_PIN(2, 14),
1771 };
1772 static const unsigned int avb_avtp_capture_a_mux[] = {
1773         AVB_AVTP_CAPTURE_A_MARK,
1774 };
1775 static const unsigned int avb_avtp_match_b_pins[] = {
1776         /*  AVB_AVTP_MATCH_B */
1777         RCAR_GP_PIN(1, 8),
1778 };
1779 static const unsigned int avb_avtp_match_b_mux[] = {
1780         AVB_AVTP_MATCH_B_MARK,
1781 };
1782 static const unsigned int avb_avtp_capture_b_pins[] = {
1783         /* AVB_AVTP_CAPTURE_B */
1784         RCAR_GP_PIN(1, 11),
1785 };
1786 static const unsigned int avb_avtp_capture_b_mux[] = {
1787         AVB_AVTP_CAPTURE_B_MARK,
1788 };
1789
1790 /* - CAN ------------------------------------------------------------------ */
1791 static const unsigned int can0_data_a_pins[] = {
1792         /* TX, RX */
1793         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1794 };
1795
1796 static const unsigned int can0_data_a_mux[] = {
1797         CAN0_TX_A_MARK,         CAN0_RX_A_MARK,
1798 };
1799
1800 static const unsigned int can0_data_b_pins[] = {
1801         /* TX, RX */
1802         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1803 };
1804
1805 static const unsigned int can0_data_b_mux[] = {
1806         CAN0_TX_B_MARK,         CAN0_RX_B_MARK,
1807 };
1808
1809 static const unsigned int can1_data_pins[] = {
1810         /* TX, RX */
1811         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1812 };
1813
1814 static const unsigned int can1_data_mux[] = {
1815         CAN1_TX_MARK,           CAN1_RX_MARK,
1816 };
1817
1818 /* - CAN Clock -------------------------------------------------------------- */
1819 static const unsigned int can_clk_pins[] = {
1820         /* CLK */
1821         RCAR_GP_PIN(1, 25),
1822 };
1823
1824 static const unsigned int can_clk_mux[] = {
1825         CAN_CLK_MARK,
1826 };
1827
1828 /* - CAN FD --------------------------------------------------------------- */
1829 static const unsigned int canfd0_data_a_pins[] = {
1830         /* TX, RX */
1831         RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1832 };
1833
1834 static const unsigned int canfd0_data_a_mux[] = {
1835         CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1836 };
1837
1838 static const unsigned int canfd0_data_b_pins[] = {
1839         /* TX, RX */
1840         RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1841 };
1842
1843 static const unsigned int canfd0_data_b_mux[] = {
1844         CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1845 };
1846
1847 static const unsigned int canfd1_data_pins[] = {
1848         /* TX, RX */
1849         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1850 };
1851
1852 static const unsigned int canfd1_data_mux[] = {
1853         CANFD1_TX_MARK,         CANFD1_RX_MARK,
1854 };
1855
1856 /* - DRIF0 --------------------------------------------------------------- */
1857 static const unsigned int drif0_ctrl_a_pins[] = {
1858         /* CLK, SYNC */
1859         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1860 };
1861
1862 static const unsigned int drif0_ctrl_a_mux[] = {
1863         RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1864 };
1865
1866 static const unsigned int drif0_data0_a_pins[] = {
1867         /* D0 */
1868         RCAR_GP_PIN(6, 10),
1869 };
1870
1871 static const unsigned int drif0_data0_a_mux[] = {
1872         RIF0_D0_A_MARK,
1873 };
1874
1875 static const unsigned int drif0_data1_a_pins[] = {
1876         /* D1 */
1877         RCAR_GP_PIN(6, 7),
1878 };
1879
1880 static const unsigned int drif0_data1_a_mux[] = {
1881         RIF0_D1_A_MARK,
1882 };
1883
1884 static const unsigned int drif0_ctrl_b_pins[] = {
1885         /* CLK, SYNC */
1886         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1887 };
1888
1889 static const unsigned int drif0_ctrl_b_mux[] = {
1890         RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1891 };
1892
1893 static const unsigned int drif0_data0_b_pins[] = {
1894         /* D0 */
1895         RCAR_GP_PIN(5, 1),
1896 };
1897
1898 static const unsigned int drif0_data0_b_mux[] = {
1899         RIF0_D0_B_MARK,
1900 };
1901
1902 static const unsigned int drif0_data1_b_pins[] = {
1903         /* D1 */
1904         RCAR_GP_PIN(5, 2),
1905 };
1906
1907 static const unsigned int drif0_data1_b_mux[] = {
1908         RIF0_D1_B_MARK,
1909 };
1910
1911 static const unsigned int drif0_ctrl_c_pins[] = {
1912         /* CLK, SYNC */
1913         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1914 };
1915
1916 static const unsigned int drif0_ctrl_c_mux[] = {
1917         RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1918 };
1919
1920 static const unsigned int drif0_data0_c_pins[] = {
1921         /* D0 */
1922         RCAR_GP_PIN(5, 13),
1923 };
1924
1925 static const unsigned int drif0_data0_c_mux[] = {
1926         RIF0_D0_C_MARK,
1927 };
1928
1929 static const unsigned int drif0_data1_c_pins[] = {
1930         /* D1 */
1931         RCAR_GP_PIN(5, 14),
1932 };
1933
1934 static const unsigned int drif0_data1_c_mux[] = {
1935         RIF0_D1_C_MARK,
1936 };
1937
1938 /* - DRIF1 --------------------------------------------------------------- */
1939 static const unsigned int drif1_ctrl_a_pins[] = {
1940         /* CLK, SYNC */
1941         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1942 };
1943
1944 static const unsigned int drif1_ctrl_a_mux[] = {
1945         RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1946 };
1947
1948 static const unsigned int drif1_data0_a_pins[] = {
1949         /* D0 */
1950         RCAR_GP_PIN(6, 19),
1951 };
1952
1953 static const unsigned int drif1_data0_a_mux[] = {
1954         RIF1_D0_A_MARK,
1955 };
1956
1957 static const unsigned int drif1_data1_a_pins[] = {
1958         /* D1 */
1959         RCAR_GP_PIN(6, 20),
1960 };
1961
1962 static const unsigned int drif1_data1_a_mux[] = {
1963         RIF1_D1_A_MARK,
1964 };
1965
1966 static const unsigned int drif1_ctrl_b_pins[] = {
1967         /* CLK, SYNC */
1968         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1969 };
1970
1971 static const unsigned int drif1_ctrl_b_mux[] = {
1972         RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1973 };
1974
1975 static const unsigned int drif1_data0_b_pins[] = {
1976         /* D0 */
1977         RCAR_GP_PIN(5, 7),
1978 };
1979
1980 static const unsigned int drif1_data0_b_mux[] = {
1981         RIF1_D0_B_MARK,
1982 };
1983
1984 static const unsigned int drif1_data1_b_pins[] = {
1985         /* D1 */
1986         RCAR_GP_PIN(5, 8),
1987 };
1988
1989 static const unsigned int drif1_data1_b_mux[] = {
1990         RIF1_D1_B_MARK,
1991 };
1992
1993 static const unsigned int drif1_ctrl_c_pins[] = {
1994         /* CLK, SYNC */
1995         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1996 };
1997
1998 static const unsigned int drif1_ctrl_c_mux[] = {
1999         RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
2000 };
2001
2002 static const unsigned int drif1_data0_c_pins[] = {
2003         /* D0 */
2004         RCAR_GP_PIN(5, 6),
2005 };
2006
2007 static const unsigned int drif1_data0_c_mux[] = {
2008         RIF1_D0_C_MARK,
2009 };
2010
2011 static const unsigned int drif1_data1_c_pins[] = {
2012         /* D1 */
2013         RCAR_GP_PIN(5, 10),
2014 };
2015
2016 static const unsigned int drif1_data1_c_mux[] = {
2017         RIF1_D1_C_MARK,
2018 };
2019
2020 /* - DRIF2 --------------------------------------------------------------- */
2021 static const unsigned int drif2_ctrl_a_pins[] = {
2022         /* CLK, SYNC */
2023         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2024 };
2025
2026 static const unsigned int drif2_ctrl_a_mux[] = {
2027         RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2028 };
2029
2030 static const unsigned int drif2_data0_a_pins[] = {
2031         /* D0 */
2032         RCAR_GP_PIN(6, 7),
2033 };
2034
2035 static const unsigned int drif2_data0_a_mux[] = {
2036         RIF2_D0_A_MARK,
2037 };
2038
2039 static const unsigned int drif2_data1_a_pins[] = {
2040         /* D1 */
2041         RCAR_GP_PIN(6, 10),
2042 };
2043
2044 static const unsigned int drif2_data1_a_mux[] = {
2045         RIF2_D1_A_MARK,
2046 };
2047
2048 static const unsigned int drif2_ctrl_b_pins[] = {
2049         /* CLK, SYNC */
2050         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2051 };
2052
2053 static const unsigned int drif2_ctrl_b_mux[] = {
2054         RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2055 };
2056
2057 static const unsigned int drif2_data0_b_pins[] = {
2058         /* D0 */
2059         RCAR_GP_PIN(6, 30),
2060 };
2061
2062 static const unsigned int drif2_data0_b_mux[] = {
2063         RIF2_D0_B_MARK,
2064 };
2065
2066 static const unsigned int drif2_data1_b_pins[] = {
2067         /* D1 */
2068         RCAR_GP_PIN(6, 31),
2069 };
2070
2071 static const unsigned int drif2_data1_b_mux[] = {
2072         RIF2_D1_B_MARK,
2073 };
2074
2075 /* - DRIF3 --------------------------------------------------------------- */
2076 static const unsigned int drif3_ctrl_a_pins[] = {
2077         /* CLK, SYNC */
2078         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2079 };
2080
2081 static const unsigned int drif3_ctrl_a_mux[] = {
2082         RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2083 };
2084
2085 static const unsigned int drif3_data0_a_pins[] = {
2086         /* D0 */
2087         RCAR_GP_PIN(6, 19),
2088 };
2089
2090 static const unsigned int drif3_data0_a_mux[] = {
2091         RIF3_D0_A_MARK,
2092 };
2093
2094 static const unsigned int drif3_data1_a_pins[] = {
2095         /* D1 */
2096         RCAR_GP_PIN(6, 20),
2097 };
2098
2099 static const unsigned int drif3_data1_a_mux[] = {
2100         RIF3_D1_A_MARK,
2101 };
2102
2103 static const unsigned int drif3_ctrl_b_pins[] = {
2104         /* CLK, SYNC */
2105         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2106 };
2107
2108 static const unsigned int drif3_ctrl_b_mux[] = {
2109         RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2110 };
2111
2112 static const unsigned int drif3_data0_b_pins[] = {
2113         /* D0 */
2114         RCAR_GP_PIN(6, 28),
2115 };
2116
2117 static const unsigned int drif3_data0_b_mux[] = {
2118         RIF3_D0_B_MARK,
2119 };
2120
2121 static const unsigned int drif3_data1_b_pins[] = {
2122         /* D1 */
2123         RCAR_GP_PIN(6, 29),
2124 };
2125
2126 static const unsigned int drif3_data1_b_mux[] = {
2127         RIF3_D1_B_MARK,
2128 };
2129
2130 /* - DU --------------------------------------------------------------------- */
2131 static const unsigned int du_rgb666_pins[] = {
2132         /* R[7:2], G[7:2], B[7:2] */
2133         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2134         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2135         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2136         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2137         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2138         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2139 };
2140
2141 static const unsigned int du_rgb666_mux[] = {
2142         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2143         DU_DR3_MARK, DU_DR2_MARK,
2144         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2145         DU_DG3_MARK, DU_DG2_MARK,
2146         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2147         DU_DB3_MARK, DU_DB2_MARK,
2148 };
2149
2150 static const unsigned int du_rgb888_pins[] = {
2151         /* R[7:0], G[7:0], B[7:0] */
2152         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2153         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2154         RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2155         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2156         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2157         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2158         RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2159         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2160         RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2161 };
2162
2163 static const unsigned int du_rgb888_mux[] = {
2164         DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2165         DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2166         DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2167         DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2168         DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2169         DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2170 };
2171
2172 static const unsigned int du_clk_out_0_pins[] = {
2173         /* CLKOUT */
2174         RCAR_GP_PIN(1, 27),
2175 };
2176
2177 static const unsigned int du_clk_out_0_mux[] = {
2178         DU_DOTCLKOUT0_MARK
2179 };
2180
2181 static const unsigned int du_clk_out_1_pins[] = {
2182         /* CLKOUT */
2183         RCAR_GP_PIN(2, 3),
2184 };
2185
2186 static const unsigned int du_clk_out_1_mux[] = {
2187         DU_DOTCLKOUT1_MARK
2188 };
2189
2190 static const unsigned int du_sync_pins[] = {
2191         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2192         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2193 };
2194
2195 static const unsigned int du_sync_mux[] = {
2196         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2197 };
2198
2199 static const unsigned int du_oddf_pins[] = {
2200         /* EXDISP/EXODDF/EXCDE */
2201         RCAR_GP_PIN(2, 2),
2202 };
2203
2204 static const unsigned int du_oddf_mux[] = {
2205         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2206 };
2207
2208 static const unsigned int du_cde_pins[] = {
2209         /* CDE */
2210         RCAR_GP_PIN(2, 0),
2211 };
2212
2213 static const unsigned int du_cde_mux[] = {
2214         DU_CDE_MARK,
2215 };
2216
2217 static const unsigned int du_disp_pins[] = {
2218         /* DISP */
2219         RCAR_GP_PIN(2, 1),
2220 };
2221
2222 static const unsigned int du_disp_mux[] = {
2223         DU_DISP_MARK,
2224 };
2225
2226 /* - HSCIF0 ----------------------------------------------------------------- */
2227 static const unsigned int hscif0_data_pins[] = {
2228         /* RX, TX */
2229         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2230 };
2231
2232 static const unsigned int hscif0_data_mux[] = {
2233         HRX0_MARK, HTX0_MARK,
2234 };
2235
2236 static const unsigned int hscif0_clk_pins[] = {
2237         /* SCK */
2238         RCAR_GP_PIN(5, 12),
2239 };
2240
2241 static const unsigned int hscif0_clk_mux[] = {
2242         HSCK0_MARK,
2243 };
2244
2245 static const unsigned int hscif0_ctrl_pins[] = {
2246         /* RTS, CTS */
2247         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2248 };
2249
2250 static const unsigned int hscif0_ctrl_mux[] = {
2251         HRTS0_N_MARK, HCTS0_N_MARK,
2252 };
2253
2254 /* - HSCIF1 ----------------------------------------------------------------- */
2255 static const unsigned int hscif1_data_a_pins[] = {
2256         /* RX, TX */
2257         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2258 };
2259
2260 static const unsigned int hscif1_data_a_mux[] = {
2261         HRX1_A_MARK, HTX1_A_MARK,
2262 };
2263
2264 static const unsigned int hscif1_clk_a_pins[] = {
2265         /* SCK */
2266         RCAR_GP_PIN(6, 21),
2267 };
2268
2269 static const unsigned int hscif1_clk_a_mux[] = {
2270         HSCK1_A_MARK,
2271 };
2272
2273 static const unsigned int hscif1_ctrl_a_pins[] = {
2274         /* RTS, CTS */
2275         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2276 };
2277
2278 static const unsigned int hscif1_ctrl_a_mux[] = {
2279         HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2280 };
2281
2282 static const unsigned int hscif1_data_b_pins[] = {
2283         /* RX, TX */
2284         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2285 };
2286
2287 static const unsigned int hscif1_data_b_mux[] = {
2288         HRX1_B_MARK, HTX1_B_MARK,
2289 };
2290
2291 static const unsigned int hscif1_clk_b_pins[] = {
2292         /* SCK */
2293         RCAR_GP_PIN(5, 0),
2294 };
2295
2296 static const unsigned int hscif1_clk_b_mux[] = {
2297         HSCK1_B_MARK,
2298 };
2299
2300 static const unsigned int hscif1_ctrl_b_pins[] = {
2301         /* RTS, CTS */
2302         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2303 };
2304
2305 static const unsigned int hscif1_ctrl_b_mux[] = {
2306         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2307 };
2308
2309 /* - HSCIF2 ----------------------------------------------------------------- */
2310 static const unsigned int hscif2_data_a_pins[] = {
2311         /* RX, TX */
2312         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2313 };
2314
2315 static const unsigned int hscif2_data_a_mux[] = {
2316         HRX2_A_MARK, HTX2_A_MARK,
2317 };
2318
2319 static const unsigned int hscif2_clk_a_pins[] = {
2320         /* SCK */
2321         RCAR_GP_PIN(6, 10),
2322 };
2323
2324 static const unsigned int hscif2_clk_a_mux[] = {
2325         HSCK2_A_MARK,
2326 };
2327
2328 static const unsigned int hscif2_ctrl_a_pins[] = {
2329         /* RTS, CTS */
2330         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2331 };
2332
2333 static const unsigned int hscif2_ctrl_a_mux[] = {
2334         HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2335 };
2336
2337 static const unsigned int hscif2_data_b_pins[] = {
2338         /* RX, TX */
2339         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2340 };
2341
2342 static const unsigned int hscif2_data_b_mux[] = {
2343         HRX2_B_MARK, HTX2_B_MARK,
2344 };
2345
2346 static const unsigned int hscif2_clk_b_pins[] = {
2347         /* SCK */
2348         RCAR_GP_PIN(6, 21),
2349 };
2350
2351 static const unsigned int hscif2_clk_b_mux[] = {
2352         HSCK2_B_MARK,
2353 };
2354
2355 static const unsigned int hscif2_ctrl_b_pins[] = {
2356         /* RTS, CTS */
2357         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2358 };
2359
2360 static const unsigned int hscif2_ctrl_b_mux[] = {
2361         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2362 };
2363
2364 static const unsigned int hscif2_data_c_pins[] = {
2365         /* RX, TX */
2366         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2367 };
2368
2369 static const unsigned int hscif2_data_c_mux[] = {
2370         HRX2_C_MARK, HTX2_C_MARK,
2371 };
2372
2373 static const unsigned int hscif2_clk_c_pins[] = {
2374         /* SCK */
2375         RCAR_GP_PIN(6, 24),
2376 };
2377
2378 static const unsigned int hscif2_clk_c_mux[] = {
2379         HSCK2_C_MARK,
2380 };
2381
2382 static const unsigned int hscif2_ctrl_c_pins[] = {
2383         /* RTS, CTS */
2384         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2385 };
2386
2387 static const unsigned int hscif2_ctrl_c_mux[] = {
2388         HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2389 };
2390
2391 /* - HSCIF3 ----------------------------------------------------------------- */
2392 static const unsigned int hscif3_data_a_pins[] = {
2393         /* RX, TX */
2394         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2395 };
2396
2397 static const unsigned int hscif3_data_a_mux[] = {
2398         HRX3_A_MARK, HTX3_A_MARK,
2399 };
2400
2401 static const unsigned int hscif3_clk_pins[] = {
2402         /* SCK */
2403         RCAR_GP_PIN(1, 22),
2404 };
2405
2406 static const unsigned int hscif3_clk_mux[] = {
2407         HSCK3_MARK,
2408 };
2409
2410 static const unsigned int hscif3_ctrl_pins[] = {
2411         /* RTS, CTS */
2412         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2413 };
2414
2415 static const unsigned int hscif3_ctrl_mux[] = {
2416         HRTS3_N_MARK, HCTS3_N_MARK,
2417 };
2418
2419 static const unsigned int hscif3_data_b_pins[] = {
2420         /* RX, TX */
2421         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2422 };
2423
2424 static const unsigned int hscif3_data_b_mux[] = {
2425         HRX3_B_MARK, HTX3_B_MARK,
2426 };
2427
2428 static const unsigned int hscif3_data_c_pins[] = {
2429         /* RX, TX */
2430         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2431 };
2432
2433 static const unsigned int hscif3_data_c_mux[] = {
2434         HRX3_C_MARK, HTX3_C_MARK,
2435 };
2436
2437 static const unsigned int hscif3_data_d_pins[] = {
2438         /* RX, TX */
2439         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2440 };
2441
2442 static const unsigned int hscif3_data_d_mux[] = {
2443         HRX3_D_MARK, HTX3_D_MARK,
2444 };
2445
2446 /* - HSCIF4 ----------------------------------------------------------------- */
2447 static const unsigned int hscif4_data_a_pins[] = {
2448         /* RX, TX */
2449         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2450 };
2451
2452 static const unsigned int hscif4_data_a_mux[] = {
2453         HRX4_A_MARK, HTX4_A_MARK,
2454 };
2455
2456 static const unsigned int hscif4_clk_pins[] = {
2457         /* SCK */
2458         RCAR_GP_PIN(1, 11),
2459 };
2460
2461 static const unsigned int hscif4_clk_mux[] = {
2462         HSCK4_MARK,
2463 };
2464
2465 static const unsigned int hscif4_ctrl_pins[] = {
2466         /* RTS, CTS */
2467         RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2468 };
2469
2470 static const unsigned int hscif4_ctrl_mux[] = {
2471         HRTS4_N_MARK, HCTS4_N_MARK,
2472 };
2473
2474 static const unsigned int hscif4_data_b_pins[] = {
2475         /* RX, TX */
2476         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2477 };
2478
2479 static const unsigned int hscif4_data_b_mux[] = {
2480         HRX4_B_MARK, HTX4_B_MARK,
2481 };
2482
2483 /* - I2C -------------------------------------------------------------------- */
2484 static const unsigned int i2c1_a_pins[] = {
2485         /* SDA, SCL */
2486         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2487 };
2488 static const unsigned int i2c1_a_mux[] = {
2489         SDA1_A_MARK, SCL1_A_MARK,
2490 };
2491 static const unsigned int i2c1_b_pins[] = {
2492         /* SDA, SCL */
2493         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2494 };
2495 static const unsigned int i2c1_b_mux[] = {
2496         SDA1_B_MARK, SCL1_B_MARK,
2497 };
2498 static const unsigned int i2c2_a_pins[] = {
2499         /* SDA, SCL */
2500         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2501 };
2502 static const unsigned int i2c2_a_mux[] = {
2503         SDA2_A_MARK, SCL2_A_MARK,
2504 };
2505 static const unsigned int i2c2_b_pins[] = {
2506         /* SDA, SCL */
2507         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2508 };
2509 static const unsigned int i2c2_b_mux[] = {
2510         SDA2_B_MARK, SCL2_B_MARK,
2511 };
2512 static const unsigned int i2c6_a_pins[] = {
2513         /* SDA, SCL */
2514         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2515 };
2516 static const unsigned int i2c6_a_mux[] = {
2517         SDA6_A_MARK, SCL6_A_MARK,
2518 };
2519 static const unsigned int i2c6_b_pins[] = {
2520         /* SDA, SCL */
2521         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2522 };
2523 static const unsigned int i2c6_b_mux[] = {
2524         SDA6_B_MARK, SCL6_B_MARK,
2525 };
2526 static const unsigned int i2c6_c_pins[] = {
2527         /* SDA, SCL */
2528         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2529 };
2530 static const unsigned int i2c6_c_mux[] = {
2531         SDA6_C_MARK, SCL6_C_MARK,
2532 };
2533
2534 /* - INTC-EX ---------------------------------------------------------------- */
2535 static const unsigned int intc_ex_irq0_pins[] = {
2536         /* IRQ0 */
2537         RCAR_GP_PIN(2, 0),
2538 };
2539 static const unsigned int intc_ex_irq0_mux[] = {
2540         IRQ0_MARK,
2541 };
2542 static const unsigned int intc_ex_irq1_pins[] = {
2543         /* IRQ1 */
2544         RCAR_GP_PIN(2, 1),
2545 };
2546 static const unsigned int intc_ex_irq1_mux[] = {
2547         IRQ1_MARK,
2548 };
2549 static const unsigned int intc_ex_irq2_pins[] = {
2550         /* IRQ2 */
2551         RCAR_GP_PIN(2, 2),
2552 };
2553 static const unsigned int intc_ex_irq2_mux[] = {
2554         IRQ2_MARK,
2555 };
2556 static const unsigned int intc_ex_irq3_pins[] = {
2557         /* IRQ3 */
2558         RCAR_GP_PIN(2, 3),
2559 };
2560 static const unsigned int intc_ex_irq3_mux[] = {
2561         IRQ3_MARK,
2562 };
2563 static const unsigned int intc_ex_irq4_pins[] = {
2564         /* IRQ4 */
2565         RCAR_GP_PIN(2, 4),
2566 };
2567 static const unsigned int intc_ex_irq4_mux[] = {
2568         IRQ4_MARK,
2569 };
2570 static const unsigned int intc_ex_irq5_pins[] = {
2571         /* IRQ5 */
2572         RCAR_GP_PIN(2, 5),
2573 };
2574 static const unsigned int intc_ex_irq5_mux[] = {
2575         IRQ5_MARK,
2576 };
2577
2578 /* - MSIOF0 ----------------------------------------------------------------- */
2579 static const unsigned int msiof0_clk_pins[] = {
2580         /* SCK */
2581         RCAR_GP_PIN(5, 17),
2582 };
2583 static const unsigned int msiof0_clk_mux[] = {
2584         MSIOF0_SCK_MARK,
2585 };
2586 static const unsigned int msiof0_sync_pins[] = {
2587         /* SYNC */
2588         RCAR_GP_PIN(5, 18),
2589 };
2590 static const unsigned int msiof0_sync_mux[] = {
2591         MSIOF0_SYNC_MARK,
2592 };
2593 static const unsigned int msiof0_ss1_pins[] = {
2594         /* SS1 */
2595         RCAR_GP_PIN(5, 19),
2596 };
2597 static const unsigned int msiof0_ss1_mux[] = {
2598         MSIOF0_SS1_MARK,
2599 };
2600 static const unsigned int msiof0_ss2_pins[] = {
2601         /* SS2 */
2602         RCAR_GP_PIN(5, 21),
2603 };
2604 static const unsigned int msiof0_ss2_mux[] = {
2605         MSIOF0_SS2_MARK,
2606 };
2607 static const unsigned int msiof0_txd_pins[] = {
2608         /* TXD */
2609         RCAR_GP_PIN(5, 20),
2610 };
2611 static const unsigned int msiof0_txd_mux[] = {
2612         MSIOF0_TXD_MARK,
2613 };
2614 static const unsigned int msiof0_rxd_pins[] = {
2615         /* RXD */
2616         RCAR_GP_PIN(5, 22),
2617 };
2618 static const unsigned int msiof0_rxd_mux[] = {
2619         MSIOF0_RXD_MARK,
2620 };
2621 /* - MSIOF1 ----------------------------------------------------------------- */
2622 static const unsigned int msiof1_clk_a_pins[] = {
2623         /* SCK */
2624         RCAR_GP_PIN(6, 8),
2625 };
2626 static const unsigned int msiof1_clk_a_mux[] = {
2627         MSIOF1_SCK_A_MARK,
2628 };
2629 static const unsigned int msiof1_sync_a_pins[] = {
2630         /* SYNC */
2631         RCAR_GP_PIN(6, 9),
2632 };
2633 static const unsigned int msiof1_sync_a_mux[] = {
2634         MSIOF1_SYNC_A_MARK,
2635 };
2636 static const unsigned int msiof1_ss1_a_pins[] = {
2637         /* SS1 */
2638         RCAR_GP_PIN(6, 5),
2639 };
2640 static const unsigned int msiof1_ss1_a_mux[] = {
2641         MSIOF1_SS1_A_MARK,
2642 };
2643 static const unsigned int msiof1_ss2_a_pins[] = {
2644         /* SS2 */
2645         RCAR_GP_PIN(6, 6),
2646 };
2647 static const unsigned int msiof1_ss2_a_mux[] = {
2648         MSIOF1_SS2_A_MARK,
2649 };
2650 static const unsigned int msiof1_txd_a_pins[] = {
2651         /* TXD */
2652         RCAR_GP_PIN(6, 7),
2653 };
2654 static const unsigned int msiof1_txd_a_mux[] = {
2655         MSIOF1_TXD_A_MARK,
2656 };
2657 static const unsigned int msiof1_rxd_a_pins[] = {
2658         /* RXD */
2659         RCAR_GP_PIN(6, 10),
2660 };
2661 static const unsigned int msiof1_rxd_a_mux[] = {
2662         MSIOF1_RXD_A_MARK,
2663 };
2664 static const unsigned int msiof1_clk_b_pins[] = {
2665         /* SCK */
2666         RCAR_GP_PIN(5, 9),
2667 };
2668 static const unsigned int msiof1_clk_b_mux[] = {
2669         MSIOF1_SCK_B_MARK,
2670 };
2671 static const unsigned int msiof1_sync_b_pins[] = {
2672         /* SYNC */
2673         RCAR_GP_PIN(5, 3),
2674 };
2675 static const unsigned int msiof1_sync_b_mux[] = {
2676         MSIOF1_SYNC_B_MARK,
2677 };
2678 static const unsigned int msiof1_ss1_b_pins[] = {
2679         /* SS1 */
2680         RCAR_GP_PIN(5, 4),
2681 };
2682 static const unsigned int msiof1_ss1_b_mux[] = {
2683         MSIOF1_SS1_B_MARK,
2684 };
2685 static const unsigned int msiof1_ss2_b_pins[] = {
2686         /* SS2 */
2687         RCAR_GP_PIN(5, 0),
2688 };
2689 static const unsigned int msiof1_ss2_b_mux[] = {
2690         MSIOF1_SS2_B_MARK,
2691 };
2692 static const unsigned int msiof1_txd_b_pins[] = {
2693         /* TXD */
2694         RCAR_GP_PIN(5, 8),
2695 };
2696 static const unsigned int msiof1_txd_b_mux[] = {
2697         MSIOF1_TXD_B_MARK,
2698 };
2699 static const unsigned int msiof1_rxd_b_pins[] = {
2700         /* RXD */
2701         RCAR_GP_PIN(5, 7),
2702 };
2703 static const unsigned int msiof1_rxd_b_mux[] = {
2704         MSIOF1_RXD_B_MARK,
2705 };
2706 static const unsigned int msiof1_clk_c_pins[] = {
2707         /* SCK */
2708         RCAR_GP_PIN(6, 17),
2709 };
2710 static const unsigned int msiof1_clk_c_mux[] = {
2711         MSIOF1_SCK_C_MARK,
2712 };
2713 static const unsigned int msiof1_sync_c_pins[] = {
2714         /* SYNC */
2715         RCAR_GP_PIN(6, 18),
2716 };
2717 static const unsigned int msiof1_sync_c_mux[] = {
2718         MSIOF1_SYNC_C_MARK,
2719 };
2720 static const unsigned int msiof1_ss1_c_pins[] = {
2721         /* SS1 */
2722         RCAR_GP_PIN(6, 21),
2723 };
2724 static const unsigned int msiof1_ss1_c_mux[] = {
2725         MSIOF1_SS1_C_MARK,
2726 };
2727 static const unsigned int msiof1_ss2_c_pins[] = {
2728         /* SS2 */
2729         RCAR_GP_PIN(6, 27),
2730 };
2731 static const unsigned int msiof1_ss2_c_mux[] = {
2732         MSIOF1_SS2_C_MARK,
2733 };
2734 static const unsigned int msiof1_txd_c_pins[] = {
2735         /* TXD */
2736         RCAR_GP_PIN(6, 20),
2737 };
2738 static const unsigned int msiof1_txd_c_mux[] = {
2739         MSIOF1_TXD_C_MARK,
2740 };
2741 static const unsigned int msiof1_rxd_c_pins[] = {
2742         /* RXD */
2743         RCAR_GP_PIN(6, 19),
2744 };
2745 static const unsigned int msiof1_rxd_c_mux[] = {
2746         MSIOF1_RXD_C_MARK,
2747 };
2748 static const unsigned int msiof1_clk_d_pins[] = {
2749         /* SCK */
2750         RCAR_GP_PIN(5, 12),
2751 };
2752 static const unsigned int msiof1_clk_d_mux[] = {
2753         MSIOF1_SCK_D_MARK,
2754 };
2755 static const unsigned int msiof1_sync_d_pins[] = {
2756         /* SYNC */
2757         RCAR_GP_PIN(5, 15),
2758 };
2759 static const unsigned int msiof1_sync_d_mux[] = {
2760         MSIOF1_SYNC_D_MARK,
2761 };
2762 static const unsigned int msiof1_ss1_d_pins[] = {
2763         /* SS1 */
2764         RCAR_GP_PIN(5, 16),
2765 };
2766 static const unsigned int msiof1_ss1_d_mux[] = {
2767         MSIOF1_SS1_D_MARK,
2768 };
2769 static const unsigned int msiof1_ss2_d_pins[] = {
2770         /* SS2 */
2771         RCAR_GP_PIN(5, 21),
2772 };
2773 static const unsigned int msiof1_ss2_d_mux[] = {
2774         MSIOF1_SS2_D_MARK,
2775 };
2776 static const unsigned int msiof1_txd_d_pins[] = {
2777         /* TXD */
2778         RCAR_GP_PIN(5, 14),
2779 };
2780 static const unsigned int msiof1_txd_d_mux[] = {
2781         MSIOF1_TXD_D_MARK,
2782 };
2783 static const unsigned int msiof1_rxd_d_pins[] = {
2784         /* RXD */
2785         RCAR_GP_PIN(5, 13),
2786 };
2787 static const unsigned int msiof1_rxd_d_mux[] = {
2788         MSIOF1_RXD_D_MARK,
2789 };
2790 static const unsigned int msiof1_clk_e_pins[] = {
2791         /* SCK */
2792         RCAR_GP_PIN(3, 0),
2793 };
2794 static const unsigned int msiof1_clk_e_mux[] = {
2795         MSIOF1_SCK_E_MARK,
2796 };
2797 static const unsigned int msiof1_sync_e_pins[] = {
2798         /* SYNC */
2799         RCAR_GP_PIN(3, 1),
2800 };
2801 static const unsigned int msiof1_sync_e_mux[] = {
2802         MSIOF1_SYNC_E_MARK,
2803 };
2804 static const unsigned int msiof1_ss1_e_pins[] = {
2805         /* SS1 */
2806         RCAR_GP_PIN(3, 4),
2807 };
2808 static const unsigned int msiof1_ss1_e_mux[] = {
2809         MSIOF1_SS1_E_MARK,
2810 };
2811 static const unsigned int msiof1_ss2_e_pins[] = {
2812         /* SS2 */
2813         RCAR_GP_PIN(3, 5),
2814 };
2815 static const unsigned int msiof1_ss2_e_mux[] = {
2816         MSIOF1_SS2_E_MARK,
2817 };
2818 static const unsigned int msiof1_txd_e_pins[] = {
2819         /* TXD */
2820         RCAR_GP_PIN(3, 3),
2821 };
2822 static const unsigned int msiof1_txd_e_mux[] = {
2823         MSIOF1_TXD_E_MARK,
2824 };
2825 static const unsigned int msiof1_rxd_e_pins[] = {
2826         /* RXD */
2827         RCAR_GP_PIN(3, 2),
2828 };
2829 static const unsigned int msiof1_rxd_e_mux[] = {
2830         MSIOF1_RXD_E_MARK,
2831 };
2832 static const unsigned int msiof1_clk_f_pins[] = {
2833         /* SCK */
2834         RCAR_GP_PIN(5, 23),
2835 };
2836 static const unsigned int msiof1_clk_f_mux[] = {
2837         MSIOF1_SCK_F_MARK,
2838 };
2839 static const unsigned int msiof1_sync_f_pins[] = {
2840         /* SYNC */
2841         RCAR_GP_PIN(5, 24),
2842 };
2843 static const unsigned int msiof1_sync_f_mux[] = {
2844         MSIOF1_SYNC_F_MARK,
2845 };
2846 static const unsigned int msiof1_ss1_f_pins[] = {
2847         /* SS1 */
2848         RCAR_GP_PIN(6, 1),
2849 };
2850 static const unsigned int msiof1_ss1_f_mux[] = {
2851         MSIOF1_SS1_F_MARK,
2852 };
2853 static const unsigned int msiof1_ss2_f_pins[] = {
2854         /* SS2 */
2855         RCAR_GP_PIN(6, 2),
2856 };
2857 static const unsigned int msiof1_ss2_f_mux[] = {
2858         MSIOF1_SS2_F_MARK,
2859 };
2860 static const unsigned int msiof1_txd_f_pins[] = {
2861         /* TXD */
2862         RCAR_GP_PIN(6, 0),
2863 };
2864 static const unsigned int msiof1_txd_f_mux[] = {
2865         MSIOF1_TXD_F_MARK,
2866 };
2867 static const unsigned int msiof1_rxd_f_pins[] = {
2868         /* RXD */
2869         RCAR_GP_PIN(5, 25),
2870 };
2871 static const unsigned int msiof1_rxd_f_mux[] = {
2872         MSIOF1_RXD_F_MARK,
2873 };
2874 static const unsigned int msiof1_clk_g_pins[] = {
2875         /* SCK */
2876         RCAR_GP_PIN(3, 6),
2877 };
2878 static const unsigned int msiof1_clk_g_mux[] = {
2879         MSIOF1_SCK_G_MARK,
2880 };
2881 static const unsigned int msiof1_sync_g_pins[] = {
2882         /* SYNC */
2883         RCAR_GP_PIN(3, 7),
2884 };
2885 static const unsigned int msiof1_sync_g_mux[] = {
2886         MSIOF1_SYNC_G_MARK,
2887 };
2888 static const unsigned int msiof1_ss1_g_pins[] = {
2889         /* SS1 */
2890         RCAR_GP_PIN(3, 10),
2891 };
2892 static const unsigned int msiof1_ss1_g_mux[] = {
2893         MSIOF1_SS1_G_MARK,
2894 };
2895 static const unsigned int msiof1_ss2_g_pins[] = {
2896         /* SS2 */
2897         RCAR_GP_PIN(3, 11),
2898 };
2899 static const unsigned int msiof1_ss2_g_mux[] = {
2900         MSIOF1_SS2_G_MARK,
2901 };
2902 static const unsigned int msiof1_txd_g_pins[] = {
2903         /* TXD */
2904         RCAR_GP_PIN(3, 9),
2905 };
2906 static const unsigned int msiof1_txd_g_mux[] = {
2907         MSIOF1_TXD_G_MARK,
2908 };
2909 static const unsigned int msiof1_rxd_g_pins[] = {
2910         /* RXD */
2911         RCAR_GP_PIN(3, 8),
2912 };
2913 static const unsigned int msiof1_rxd_g_mux[] = {
2914         MSIOF1_RXD_G_MARK,
2915 };
2916 /* - MSIOF2 ----------------------------------------------------------------- */
2917 static const unsigned int msiof2_clk_a_pins[] = {
2918         /* SCK */
2919         RCAR_GP_PIN(1, 9),
2920 };
2921 static const unsigned int msiof2_clk_a_mux[] = {
2922         MSIOF2_SCK_A_MARK,
2923 };
2924 static const unsigned int msiof2_sync_a_pins[] = {
2925         /* SYNC */
2926         RCAR_GP_PIN(1, 8),
2927 };
2928 static const unsigned int msiof2_sync_a_mux[] = {
2929         MSIOF2_SYNC_A_MARK,
2930 };
2931 static const unsigned int msiof2_ss1_a_pins[] = {
2932         /* SS1 */
2933         RCAR_GP_PIN(1, 6),
2934 };
2935 static const unsigned int msiof2_ss1_a_mux[] = {
2936         MSIOF2_SS1_A_MARK,
2937 };
2938 static const unsigned int msiof2_ss2_a_pins[] = {
2939         /* SS2 */
2940         RCAR_GP_PIN(1, 7),
2941 };
2942 static const unsigned int msiof2_ss2_a_mux[] = {
2943         MSIOF2_SS2_A_MARK,
2944 };
2945 static const unsigned int msiof2_txd_a_pins[] = {
2946         /* TXD */
2947         RCAR_GP_PIN(1, 11),
2948 };
2949 static const unsigned int msiof2_txd_a_mux[] = {
2950         MSIOF2_TXD_A_MARK,
2951 };
2952 static const unsigned int msiof2_rxd_a_pins[] = {
2953         /* RXD */
2954         RCAR_GP_PIN(1, 10),
2955 };
2956 static const unsigned int msiof2_rxd_a_mux[] = {
2957         MSIOF2_RXD_A_MARK,
2958 };
2959 static const unsigned int msiof2_clk_b_pins[] = {
2960         /* SCK */
2961         RCAR_GP_PIN(0, 4),
2962 };
2963 static const unsigned int msiof2_clk_b_mux[] = {
2964         MSIOF2_SCK_B_MARK,
2965 };
2966 static const unsigned int msiof2_sync_b_pins[] = {
2967         /* SYNC */
2968         RCAR_GP_PIN(0, 5),
2969 };
2970 static const unsigned int msiof2_sync_b_mux[] = {
2971         MSIOF2_SYNC_B_MARK,
2972 };
2973 static const unsigned int msiof2_ss1_b_pins[] = {
2974         /* SS1 */
2975         RCAR_GP_PIN(0, 0),
2976 };
2977 static const unsigned int msiof2_ss1_b_mux[] = {
2978         MSIOF2_SS1_B_MARK,
2979 };
2980 static const unsigned int msiof2_ss2_b_pins[] = {
2981         /* SS2 */
2982         RCAR_GP_PIN(0, 1),
2983 };
2984 static const unsigned int msiof2_ss2_b_mux[] = {
2985         MSIOF2_SS2_B_MARK,
2986 };
2987 static const unsigned int msiof2_txd_b_pins[] = {
2988         /* TXD */
2989         RCAR_GP_PIN(0, 7),
2990 };
2991 static const unsigned int msiof2_txd_b_mux[] = {
2992         MSIOF2_TXD_B_MARK,
2993 };
2994 static const unsigned int msiof2_rxd_b_pins[] = {
2995         /* RXD */
2996         RCAR_GP_PIN(0, 6),
2997 };
2998 static const unsigned int msiof2_rxd_b_mux[] = {
2999         MSIOF2_RXD_B_MARK,
3000 };
3001 static const unsigned int msiof2_clk_c_pins[] = {
3002         /* SCK */
3003         RCAR_GP_PIN(2, 12),
3004 };
3005 static const unsigned int msiof2_clk_c_mux[] = {
3006         MSIOF2_SCK_C_MARK,
3007 };
3008 static const unsigned int msiof2_sync_c_pins[] = {
3009         /* SYNC */
3010         RCAR_GP_PIN(2, 11),
3011 };
3012 static const unsigned int msiof2_sync_c_mux[] = {
3013         MSIOF2_SYNC_C_MARK,
3014 };
3015 static const unsigned int msiof2_ss1_c_pins[] = {
3016         /* SS1 */
3017         RCAR_GP_PIN(2, 10),
3018 };
3019 static const unsigned int msiof2_ss1_c_mux[] = {
3020         MSIOF2_SS1_C_MARK,
3021 };
3022 static const unsigned int msiof2_ss2_c_pins[] = {
3023         /* SS2 */
3024         RCAR_GP_PIN(2, 9),
3025 };
3026 static const unsigned int msiof2_ss2_c_mux[] = {
3027         MSIOF2_SS2_C_MARK,
3028 };
3029 static const unsigned int msiof2_txd_c_pins[] = {
3030         /* TXD */
3031         RCAR_GP_PIN(2, 14),
3032 };
3033 static const unsigned int msiof2_txd_c_mux[] = {
3034         MSIOF2_TXD_C_MARK,
3035 };
3036 static const unsigned int msiof2_rxd_c_pins[] = {
3037         /* RXD */
3038         RCAR_GP_PIN(2, 13),
3039 };
3040 static const unsigned int msiof2_rxd_c_mux[] = {
3041         MSIOF2_RXD_C_MARK,
3042 };
3043 static const unsigned int msiof2_clk_d_pins[] = {
3044         /* SCK */
3045         RCAR_GP_PIN(0, 8),
3046 };
3047 static const unsigned int msiof2_clk_d_mux[] = {
3048         MSIOF2_SCK_D_MARK,
3049 };
3050 static const unsigned int msiof2_sync_d_pins[] = {
3051         /* SYNC */
3052         RCAR_GP_PIN(0, 9),
3053 };
3054 static const unsigned int msiof2_sync_d_mux[] = {
3055         MSIOF2_SYNC_D_MARK,
3056 };
3057 static const unsigned int msiof2_ss1_d_pins[] = {
3058         /* SS1 */
3059         RCAR_GP_PIN(0, 12),
3060 };
3061 static const unsigned int msiof2_ss1_d_mux[] = {
3062         MSIOF2_SS1_D_MARK,
3063 };
3064 static const unsigned int msiof2_ss2_d_pins[] = {
3065         /* SS2 */
3066         RCAR_GP_PIN(0, 13),
3067 };
3068 static const unsigned int msiof2_ss2_d_mux[] = {
3069         MSIOF2_SS2_D_MARK,
3070 };
3071 static const unsigned int msiof2_txd_d_pins[] = {
3072         /* TXD */
3073         RCAR_GP_PIN(0, 11),
3074 };
3075 static const unsigned int msiof2_txd_d_mux[] = {
3076         MSIOF2_TXD_D_MARK,
3077 };
3078 static const unsigned int msiof2_rxd_d_pins[] = {
3079         /* RXD */
3080         RCAR_GP_PIN(0, 10),
3081 };
3082 static const unsigned int msiof2_rxd_d_mux[] = {
3083         MSIOF2_RXD_D_MARK,
3084 };
3085 /* - MSIOF3 ----------------------------------------------------------------- */
3086 static const unsigned int msiof3_clk_a_pins[] = {
3087         /* SCK */
3088         RCAR_GP_PIN(0, 0),
3089 };
3090 static const unsigned int msiof3_clk_a_mux[] = {
3091         MSIOF3_SCK_A_MARK,
3092 };
3093 static const unsigned int msiof3_sync_a_pins[] = {
3094         /* SYNC */
3095         RCAR_GP_PIN(0, 1),
3096 };
3097 static const unsigned int msiof3_sync_a_mux[] = {
3098         MSIOF3_SYNC_A_MARK,
3099 };
3100 static const unsigned int msiof3_ss1_a_pins[] = {
3101         /* SS1 */
3102         RCAR_GP_PIN(0, 14),
3103 };
3104 static const unsigned int msiof3_ss1_a_mux[] = {
3105         MSIOF3_SS1_A_MARK,
3106 };
3107 static const unsigned int msiof3_ss2_a_pins[] = {
3108         /* SS2 */
3109         RCAR_GP_PIN(0, 15),
3110 };
3111 static const unsigned int msiof3_ss2_a_mux[] = {
3112         MSIOF3_SS2_A_MARK,
3113 };
3114 static const unsigned int msiof3_txd_a_pins[] = {
3115         /* TXD */
3116         RCAR_GP_PIN(0, 3),
3117 };
3118 static const unsigned int msiof3_txd_a_mux[] = {
3119         MSIOF3_TXD_A_MARK,
3120 };
3121 static const unsigned int msiof3_rxd_a_pins[] = {
3122         /* RXD */
3123         RCAR_GP_PIN(0, 2),
3124 };
3125 static const unsigned int msiof3_rxd_a_mux[] = {
3126         MSIOF3_RXD_A_MARK,
3127 };
3128 static const unsigned int msiof3_clk_b_pins[] = {
3129         /* SCK */
3130         RCAR_GP_PIN(1, 2),
3131 };
3132 static const unsigned int msiof3_clk_b_mux[] = {
3133         MSIOF3_SCK_B_MARK,
3134 };
3135 static const unsigned int msiof3_sync_b_pins[] = {
3136         /* SYNC */
3137         RCAR_GP_PIN(1, 0),
3138 };
3139 static const unsigned int msiof3_sync_b_mux[] = {
3140         MSIOF3_SYNC_B_MARK,
3141 };
3142 static const unsigned int msiof3_ss1_b_pins[] = {
3143         /* SS1 */
3144         RCAR_GP_PIN(1, 4),
3145 };
3146 static const unsigned int msiof3_ss1_b_mux[] = {
3147         MSIOF3_SS1_B_MARK,
3148 };
3149 static const unsigned int msiof3_ss2_b_pins[] = {
3150         /* SS2 */
3151         RCAR_GP_PIN(1, 5),
3152 };
3153 static const unsigned int msiof3_ss2_b_mux[] = {
3154         MSIOF3_SS2_B_MARK,
3155 };
3156 static const unsigned int msiof3_txd_b_pins[] = {
3157         /* TXD */
3158         RCAR_GP_PIN(1, 1),
3159 };
3160 static const unsigned int msiof3_txd_b_mux[] = {
3161         MSIOF3_TXD_B_MARK,
3162 };
3163 static const unsigned int msiof3_rxd_b_pins[] = {
3164         /* RXD */
3165         RCAR_GP_PIN(1, 3),
3166 };
3167 static const unsigned int msiof3_rxd_b_mux[] = {
3168         MSIOF3_RXD_B_MARK,
3169 };
3170 static const unsigned int msiof3_clk_c_pins[] = {
3171         /* SCK */
3172         RCAR_GP_PIN(1, 12),
3173 };
3174 static const unsigned int msiof3_clk_c_mux[] = {
3175         MSIOF3_SCK_C_MARK,
3176 };
3177 static const unsigned int msiof3_sync_c_pins[] = {
3178         /* SYNC */
3179         RCAR_GP_PIN(1, 13),
3180 };
3181 static const unsigned int msiof3_sync_c_mux[] = {
3182         MSIOF3_SYNC_C_MARK,
3183 };
3184 static const unsigned int msiof3_txd_c_pins[] = {
3185         /* TXD */
3186         RCAR_GP_PIN(1, 15),
3187 };
3188 static const unsigned int msiof3_txd_c_mux[] = {
3189         MSIOF3_TXD_C_MARK,
3190 };
3191 static const unsigned int msiof3_rxd_c_pins[] = {
3192         /* RXD */
3193         RCAR_GP_PIN(1, 14),
3194 };
3195 static const unsigned int msiof3_rxd_c_mux[] = {
3196         MSIOF3_RXD_C_MARK,
3197 };
3198 static const unsigned int msiof3_clk_d_pins[] = {
3199         /* SCK */
3200         RCAR_GP_PIN(1, 22),
3201 };
3202 static const unsigned int msiof3_clk_d_mux[] = {
3203         MSIOF3_SCK_D_MARK,
3204 };
3205 static const unsigned int msiof3_sync_d_pins[] = {
3206         /* SYNC */
3207         RCAR_GP_PIN(1, 23),
3208 };
3209 static const unsigned int msiof3_sync_d_mux[] = {
3210         MSIOF3_SYNC_D_MARK,
3211 };
3212 static const unsigned int msiof3_ss1_d_pins[] = {
3213         /* SS1 */
3214         RCAR_GP_PIN(1, 26),
3215 };
3216 static const unsigned int msiof3_ss1_d_mux[] = {
3217         MSIOF3_SS1_D_MARK,
3218 };
3219 static const unsigned int msiof3_txd_d_pins[] = {
3220         /* TXD */
3221         RCAR_GP_PIN(1, 25),
3222 };
3223 static const unsigned int msiof3_txd_d_mux[] = {
3224         MSIOF3_TXD_D_MARK,
3225 };
3226 static const unsigned int msiof3_rxd_d_pins[] = {
3227         /* RXD */
3228         RCAR_GP_PIN(1, 24),
3229 };
3230 static const unsigned int msiof3_rxd_d_mux[] = {
3231         MSIOF3_RXD_D_MARK,
3232 };
3233 static const unsigned int msiof3_clk_e_pins[] = {
3234         /* SCK */
3235         RCAR_GP_PIN(2, 3),
3236 };
3237 static const unsigned int msiof3_clk_e_mux[] = {
3238         MSIOF3_SCK_E_MARK,
3239 };
3240 static const unsigned int msiof3_sync_e_pins[] = {
3241         /* SYNC */
3242         RCAR_GP_PIN(2, 2),
3243 };
3244 static const unsigned int msiof3_sync_e_mux[] = {
3245         MSIOF3_SYNC_E_MARK,
3246 };
3247 static const unsigned int msiof3_ss1_e_pins[] = {
3248         /* SS1 */
3249         RCAR_GP_PIN(2, 1),
3250 };
3251 static const unsigned int msiof3_ss1_e_mux[] = {
3252         MSIOF3_SS1_E_MARK,
3253 };
3254 static const unsigned int msiof3_ss2_e_pins[] = {
3255         /* SS2 */
3256         RCAR_GP_PIN(2, 0),
3257 };
3258 static const unsigned int msiof3_ss2_e_mux[] = {
3259         MSIOF3_SS2_E_MARK,
3260 };
3261 static const unsigned int msiof3_txd_e_pins[] = {
3262         /* TXD */
3263         RCAR_GP_PIN(2, 5),
3264 };
3265 static const unsigned int msiof3_txd_e_mux[] = {
3266         MSIOF3_TXD_E_MARK,
3267 };
3268 static const unsigned int msiof3_rxd_e_pins[] = {
3269         /* RXD */
3270         RCAR_GP_PIN(2, 4),
3271 };
3272 static const unsigned int msiof3_rxd_e_mux[] = {
3273         MSIOF3_RXD_E_MARK,
3274 };
3275
3276 /* - PWM0 --------------------------------------------------------------------*/
3277 static const unsigned int pwm0_pins[] = {
3278         /* PWM */
3279         RCAR_GP_PIN(2, 6),
3280 };
3281 static const unsigned int pwm0_mux[] = {
3282         PWM0_MARK,
3283 };
3284 /* - PWM1 --------------------------------------------------------------------*/
3285 static const unsigned int pwm1_a_pins[] = {
3286         /* PWM */
3287         RCAR_GP_PIN(2, 7),
3288 };
3289 static const unsigned int pwm1_a_mux[] = {
3290         PWM1_A_MARK,
3291 };
3292 static const unsigned int pwm1_b_pins[] = {
3293         /* PWM */
3294         RCAR_GP_PIN(1, 8),
3295 };
3296 static const unsigned int pwm1_b_mux[] = {
3297         PWM1_B_MARK,
3298 };
3299 /* - PWM2 --------------------------------------------------------------------*/
3300 static const unsigned int pwm2_a_pins[] = {
3301         /* PWM */
3302         RCAR_GP_PIN(2, 8),
3303 };
3304 static const unsigned int pwm2_a_mux[] = {
3305         PWM2_A_MARK,
3306 };
3307 static const unsigned int pwm2_b_pins[] = {
3308         /* PWM */
3309         RCAR_GP_PIN(1, 11),
3310 };
3311 static const unsigned int pwm2_b_mux[] = {
3312         PWM2_B_MARK,
3313 };
3314 /* - PWM3 --------------------------------------------------------------------*/
3315 static const unsigned int pwm3_a_pins[] = {
3316         /* PWM */
3317         RCAR_GP_PIN(1, 0),
3318 };
3319 static const unsigned int pwm3_a_mux[] = {
3320         PWM3_A_MARK,
3321 };
3322 static const unsigned int pwm3_b_pins[] = {
3323         /* PWM */
3324         RCAR_GP_PIN(2, 2),
3325 };
3326 static const unsigned int pwm3_b_mux[] = {
3327         PWM3_B_MARK,
3328 };
3329 /* - PWM4 --------------------------------------------------------------------*/
3330 static const unsigned int pwm4_a_pins[] = {
3331         /* PWM */
3332         RCAR_GP_PIN(1, 1),
3333 };
3334 static const unsigned int pwm4_a_mux[] = {
3335         PWM4_A_MARK,
3336 };
3337 static const unsigned int pwm4_b_pins[] = {
3338         /* PWM */
3339         RCAR_GP_PIN(2, 3),
3340 };
3341 static const unsigned int pwm4_b_mux[] = {
3342         PWM4_B_MARK,
3343 };
3344 /* - PWM5 --------------------------------------------------------------------*/
3345 static const unsigned int pwm5_a_pins[] = {
3346         /* PWM */
3347         RCAR_GP_PIN(1, 2),
3348 };
3349 static const unsigned int pwm5_a_mux[] = {
3350         PWM5_A_MARK,
3351 };
3352 static const unsigned int pwm5_b_pins[] = {
3353         /* PWM */
3354         RCAR_GP_PIN(2, 4),
3355 };
3356 static const unsigned int pwm5_b_mux[] = {
3357         PWM5_B_MARK,
3358 };
3359 /* - PWM6 --------------------------------------------------------------------*/
3360 static const unsigned int pwm6_a_pins[] = {
3361         /* PWM */
3362         RCAR_GP_PIN(1, 3),
3363 };
3364 static const unsigned int pwm6_a_mux[] = {
3365         PWM6_A_MARK,
3366 };
3367 static const unsigned int pwm6_b_pins[] = {
3368         /* PWM */
3369         RCAR_GP_PIN(2, 5),
3370 };
3371 static const unsigned int pwm6_b_mux[] = {
3372         PWM6_B_MARK,
3373 };
3374
3375 /* - SATA --------------------------------------------------------------------*/
3376 static const unsigned int sata0_devslp_a_pins[] = {
3377         /* DEVSLP */
3378         RCAR_GP_PIN(6, 16),
3379 };
3380
3381 static const unsigned int sata0_devslp_a_mux[] = {
3382         SATA_DEVSLP_A_MARK,
3383 };
3384
3385 static const unsigned int sata0_devslp_b_pins[] = {
3386         /* DEVSLP */
3387         RCAR_GP_PIN(4, 6),
3388 };
3389
3390 static const unsigned int sata0_devslp_b_mux[] = {
3391         SATA_DEVSLP_B_MARK,
3392 };
3393
3394 /* - SCIF0 ------------------------------------------------------------------ */
3395 static const unsigned int scif0_data_pins[] = {
3396         /* RX, TX */
3397         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3398 };
3399 static const unsigned int scif0_data_mux[] = {
3400         RX0_MARK, TX0_MARK,
3401 };
3402 static const unsigned int scif0_clk_pins[] = {
3403         /* SCK */
3404         RCAR_GP_PIN(5, 0),
3405 };
3406 static const unsigned int scif0_clk_mux[] = {
3407         SCK0_MARK,
3408 };
3409 static const unsigned int scif0_ctrl_pins[] = {
3410         /* RTS, CTS */
3411         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3412 };
3413 static const unsigned int scif0_ctrl_mux[] = {
3414         RTS0_N_MARK, CTS0_N_MARK,
3415 };
3416 /* - SCIF1 ------------------------------------------------------------------ */
3417 static const unsigned int scif1_data_a_pins[] = {
3418         /* RX, TX */
3419         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3420 };
3421 static const unsigned int scif1_data_a_mux[] = {
3422         RX1_A_MARK, TX1_A_MARK,
3423 };
3424 static const unsigned int scif1_clk_pins[] = {
3425         /* SCK */
3426         RCAR_GP_PIN(6, 21),
3427 };
3428 static const unsigned int scif1_clk_mux[] = {
3429         SCK1_MARK,
3430 };
3431 static const unsigned int scif1_ctrl_pins[] = {
3432         /* RTS, CTS */
3433         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3434 };
3435 static const unsigned int scif1_ctrl_mux[] = {
3436         RTS1_N_MARK, CTS1_N_MARK,
3437 };
3438 static const unsigned int scif1_data_b_pins[] = {
3439         /* RX, TX */
3440         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3441 };
3442 static const unsigned int scif1_data_b_mux[] = {
3443         RX1_B_MARK, TX1_B_MARK,
3444 };
3445 /* - SCIF2 ------------------------------------------------------------------ */
3446 static const unsigned int scif2_data_a_pins[] = {
3447         /* RX, TX */
3448         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3449 };
3450 static const unsigned int scif2_data_a_mux[] = {
3451         RX2_A_MARK, TX2_A_MARK,
3452 };
3453 static const unsigned int scif2_clk_pins[] = {
3454         /* SCK */
3455         RCAR_GP_PIN(5, 9),
3456 };
3457 static const unsigned int scif2_clk_mux[] = {
3458         SCK2_MARK,
3459 };
3460 static const unsigned int scif2_data_b_pins[] = {
3461         /* RX, TX */
3462         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3463 };
3464 static const unsigned int scif2_data_b_mux[] = {
3465         RX2_B_MARK, TX2_B_MARK,
3466 };
3467 /* - SCIF3 ------------------------------------------------------------------ */
3468 static const unsigned int scif3_data_a_pins[] = {
3469         /* RX, TX */
3470         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3471 };
3472 static const unsigned int scif3_data_a_mux[] = {
3473         RX3_A_MARK, TX3_A_MARK,
3474 };
3475 static const unsigned int scif3_clk_pins[] = {
3476         /* SCK */
3477         RCAR_GP_PIN(1, 22),
3478 };
3479 static const unsigned int scif3_clk_mux[] = {
3480         SCK3_MARK,
3481 };
3482 static const unsigned int scif3_ctrl_pins[] = {
3483         /* RTS, CTS */
3484         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3485 };
3486 static const unsigned int scif3_ctrl_mux[] = {
3487         RTS3_N_MARK, CTS3_N_MARK,
3488 };
3489 static const unsigned int scif3_data_b_pins[] = {
3490         /* RX, TX */
3491         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3492 };
3493 static const unsigned int scif3_data_b_mux[] = {
3494         RX3_B_MARK, TX3_B_MARK,
3495 };
3496 /* - SCIF4 ------------------------------------------------------------------ */
3497 static const unsigned int scif4_data_a_pins[] = {
3498         /* RX, TX */
3499         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3500 };
3501 static const unsigned int scif4_data_a_mux[] = {
3502         RX4_A_MARK, TX4_A_MARK,
3503 };
3504 static const unsigned int scif4_clk_a_pins[] = {
3505         /* SCK */
3506         RCAR_GP_PIN(2, 10),
3507 };
3508 static const unsigned int scif4_clk_a_mux[] = {
3509         SCK4_A_MARK,
3510 };
3511 static const unsigned int scif4_ctrl_a_pins[] = {
3512         /* RTS, CTS */
3513         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3514 };
3515 static const unsigned int scif4_ctrl_a_mux[] = {
3516         RTS4_N_A_MARK, CTS4_N_A_MARK,
3517 };
3518 static const unsigned int scif4_data_b_pins[] = {
3519         /* RX, TX */
3520         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3521 };
3522 static const unsigned int scif4_data_b_mux[] = {
3523         RX4_B_MARK, TX4_B_MARK,
3524 };
3525 static const unsigned int scif4_clk_b_pins[] = {
3526         /* SCK */
3527         RCAR_GP_PIN(1, 5),
3528 };
3529 static const unsigned int scif4_clk_b_mux[] = {
3530         SCK4_B_MARK,
3531 };
3532 static const unsigned int scif4_ctrl_b_pins[] = {
3533         /* RTS, CTS */
3534         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3535 };
3536 static const unsigned int scif4_ctrl_b_mux[] = {
3537         RTS4_N_B_MARK, CTS4_N_B_MARK,
3538 };
3539 static const unsigned int scif4_data_c_pins[] = {
3540         /* RX, TX */
3541         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3542 };
3543 static const unsigned int scif4_data_c_mux[] = {
3544         RX4_C_MARK, TX4_C_MARK,
3545 };
3546 static const unsigned int scif4_clk_c_pins[] = {
3547         /* SCK */
3548         RCAR_GP_PIN(0, 8),
3549 };
3550 static const unsigned int scif4_clk_c_mux[] = {
3551         SCK4_C_MARK,
3552 };
3553 static const unsigned int scif4_ctrl_c_pins[] = {
3554         /* RTS, CTS */
3555         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3556 };
3557 static const unsigned int scif4_ctrl_c_mux[] = {
3558         RTS4_N_C_MARK, CTS4_N_C_MARK,
3559 };
3560 /* - SCIF5 ------------------------------------------------------------------ */
3561 static const unsigned int scif5_data_a_pins[] = {
3562         /* RX, TX */
3563         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3564 };
3565 static const unsigned int scif5_data_a_mux[] = {
3566         RX5_A_MARK, TX5_A_MARK,
3567 };
3568 static const unsigned int scif5_clk_a_pins[] = {
3569         /* SCK */
3570         RCAR_GP_PIN(6, 21),
3571 };
3572 static const unsigned int scif5_clk_a_mux[] = {
3573         SCK5_A_MARK,
3574 };
3575 static const unsigned int scif5_data_b_pins[] = {
3576         /* RX, TX */
3577         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3578 };
3579 static const unsigned int scif5_data_b_mux[] = {
3580         RX5_B_MARK, TX5_B_MARK,
3581 };
3582 static const unsigned int scif5_clk_b_pins[] = {
3583         /* SCK */
3584         RCAR_GP_PIN(5, 0),
3585 };
3586 static const unsigned int scif5_clk_b_mux[] = {
3587         SCK5_B_MARK,
3588 };
3589 /* - SCIF Clock ------------------------------------------------------------- */
3590 static const unsigned int scif_clk_a_pins[] = {
3591         /* SCIF_CLK */
3592         RCAR_GP_PIN(6, 23),
3593 };
3594 static const unsigned int scif_clk_a_mux[] = {
3595         SCIF_CLK_A_MARK,
3596 };
3597 static const unsigned int scif_clk_b_pins[] = {
3598         /* SCIF_CLK */
3599         RCAR_GP_PIN(5, 9),
3600 };
3601 static const unsigned int scif_clk_b_mux[] = {
3602         SCIF_CLK_B_MARK,
3603 };
3604
3605 /* - SDHI0 ------------------------------------------------------------------ */
3606 static const unsigned int sdhi0_data1_pins[] = {
3607         /* D0 */
3608         RCAR_GP_PIN(3, 2),
3609 };
3610
3611 static const unsigned int sdhi0_data1_mux[] = {
3612         SD0_DAT0_MARK,
3613 };
3614
3615 static const unsigned int sdhi0_data4_pins[] = {
3616         /* D[0:3] */
3617         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3618         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3619 };
3620
3621 static const unsigned int sdhi0_data4_mux[] = {
3622         SD0_DAT0_MARK, SD0_DAT1_MARK,
3623         SD0_DAT2_MARK, SD0_DAT3_MARK,
3624 };
3625
3626 static const unsigned int sdhi0_ctrl_pins[] = {
3627         /* CLK, CMD */
3628         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3629 };
3630
3631 static const unsigned int sdhi0_ctrl_mux[] = {
3632         SD0_CLK_MARK, SD0_CMD_MARK,
3633 };
3634
3635 static const unsigned int sdhi0_cd_pins[] = {
3636         /* CD */
3637         RCAR_GP_PIN(3, 12),
3638 };
3639
3640 static const unsigned int sdhi0_cd_mux[] = {
3641         SD0_CD_MARK,
3642 };
3643
3644 static const unsigned int sdhi0_wp_pins[] = {
3645         /* WP */
3646         RCAR_GP_PIN(3, 13),
3647 };
3648
3649 static const unsigned int sdhi0_wp_mux[] = {
3650         SD0_WP_MARK,
3651 };
3652
3653 /* - SDHI1 ------------------------------------------------------------------ */
3654 static const unsigned int sdhi1_data1_pins[] = {
3655         /* D0 */
3656         RCAR_GP_PIN(3, 8),
3657 };
3658
3659 static const unsigned int sdhi1_data1_mux[] = {
3660         SD1_DAT0_MARK,
3661 };
3662
3663 static const unsigned int sdhi1_data4_pins[] = {
3664         /* D[0:3] */
3665         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3666         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3667 };
3668
3669 static const unsigned int sdhi1_data4_mux[] = {
3670         SD1_DAT0_MARK, SD1_DAT1_MARK,
3671         SD1_DAT2_MARK, SD1_DAT3_MARK,
3672 };
3673
3674 static const unsigned int sdhi1_ctrl_pins[] = {
3675         /* CLK, CMD */
3676         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3677 };
3678
3679 static const unsigned int sdhi1_ctrl_mux[] = {
3680         SD1_CLK_MARK, SD1_CMD_MARK,
3681 };
3682
3683 static const unsigned int sdhi1_cd_pins[] = {
3684         /* CD */
3685         RCAR_GP_PIN(3, 14),
3686 };
3687
3688 static const unsigned int sdhi1_cd_mux[] = {
3689         SD1_CD_MARK,
3690 };
3691
3692 static const unsigned int sdhi1_wp_pins[] = {
3693         /* WP */
3694         RCAR_GP_PIN(3, 15),
3695 };
3696
3697 static const unsigned int sdhi1_wp_mux[] = {
3698         SD1_WP_MARK,
3699 };
3700
3701 /* - SDHI2 ------------------------------------------------------------------ */
3702 static const unsigned int sdhi2_data1_pins[] = {
3703         /* D0 */
3704         RCAR_GP_PIN(4, 2),
3705 };
3706
3707 static const unsigned int sdhi2_data1_mux[] = {
3708         SD2_DAT0_MARK,
3709 };
3710
3711 static const unsigned int sdhi2_data4_pins[] = {
3712         /* D[0:3] */
3713         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3714         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3715 };
3716
3717 static const unsigned int sdhi2_data4_mux[] = {
3718         SD2_DAT0_MARK, SD2_DAT1_MARK,
3719         SD2_DAT2_MARK, SD2_DAT3_MARK,
3720 };
3721
3722 static const unsigned int sdhi2_data8_pins[] = {
3723         /* D[0:7] */
3724         RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3725         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3726         RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3727         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3728 };
3729
3730 static const unsigned int sdhi2_data8_mux[] = {
3731         SD2_DAT0_MARK, SD2_DAT1_MARK,
3732         SD2_DAT2_MARK, SD2_DAT3_MARK,
3733         SD2_DAT4_MARK, SD2_DAT5_MARK,
3734         SD2_DAT6_MARK, SD2_DAT7_MARK,
3735 };
3736
3737 static const unsigned int sdhi2_ctrl_pins[] = {
3738         /* CLK, CMD */
3739         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3740 };
3741
3742 static const unsigned int sdhi2_ctrl_mux[] = {
3743         SD2_CLK_MARK, SD2_CMD_MARK,
3744 };
3745
3746 static const unsigned int sdhi2_cd_a_pins[] = {
3747         /* CD */
3748         RCAR_GP_PIN(4, 13),
3749 };
3750
3751 static const unsigned int sdhi2_cd_a_mux[] = {
3752         SD2_CD_A_MARK,
3753 };
3754
3755 static const unsigned int sdhi2_cd_b_pins[] = {
3756         /* CD */
3757         RCAR_GP_PIN(5, 10),
3758 };
3759
3760 static const unsigned int sdhi2_cd_b_mux[] = {
3761         SD2_CD_B_MARK,
3762 };
3763
3764 static const unsigned int sdhi2_wp_a_pins[] = {
3765         /* WP */
3766         RCAR_GP_PIN(4, 14),
3767 };
3768
3769 static const unsigned int sdhi2_wp_a_mux[] = {
3770         SD2_WP_A_MARK,
3771 };
3772
3773 static const unsigned int sdhi2_wp_b_pins[] = {
3774         /* WP */
3775         RCAR_GP_PIN(5, 11),
3776 };
3777
3778 static const unsigned int sdhi2_wp_b_mux[] = {
3779         SD2_WP_B_MARK,
3780 };
3781
3782 static const unsigned int sdhi2_ds_pins[] = {
3783         /* DS */
3784         RCAR_GP_PIN(4, 6),
3785 };
3786
3787 static const unsigned int sdhi2_ds_mux[] = {
3788         SD2_DS_MARK,
3789 };
3790
3791 /* - SDHI3 ------------------------------------------------------------------ */
3792 static const unsigned int sdhi3_data1_pins[] = {
3793         /* D0 */
3794         RCAR_GP_PIN(4, 9),
3795 };
3796
3797 static const unsigned int sdhi3_data1_mux[] = {
3798         SD3_DAT0_MARK,
3799 };
3800
3801 static const unsigned int sdhi3_data4_pins[] = {
3802         /* D[0:3] */
3803         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3804         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3805 };
3806
3807 static const unsigned int sdhi3_data4_mux[] = {
3808         SD3_DAT0_MARK, SD3_DAT1_MARK,
3809         SD3_DAT2_MARK, SD3_DAT3_MARK,
3810 };
3811
3812 static const unsigned int sdhi3_data8_pins[] = {
3813         /* D[0:7] */
3814         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3815         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3816         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3817         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3818 };
3819
3820 static const unsigned int sdhi3_data8_mux[] = {
3821         SD3_DAT0_MARK, SD3_DAT1_MARK,
3822         SD3_DAT2_MARK, SD3_DAT3_MARK,
3823         SD3_DAT4_MARK, SD3_DAT5_MARK,
3824         SD3_DAT6_MARK, SD3_DAT7_MARK,
3825 };
3826
3827 static const unsigned int sdhi3_ctrl_pins[] = {
3828         /* CLK, CMD */
3829         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3830 };
3831
3832 static const unsigned int sdhi3_ctrl_mux[] = {
3833         SD3_CLK_MARK, SD3_CMD_MARK,
3834 };
3835
3836 static const unsigned int sdhi3_cd_pins[] = {
3837         /* CD */
3838         RCAR_GP_PIN(4, 15),
3839 };
3840
3841 static const unsigned int sdhi3_cd_mux[] = {
3842         SD3_CD_MARK,
3843 };
3844
3845 static const unsigned int sdhi3_wp_pins[] = {
3846         /* WP */
3847         RCAR_GP_PIN(4, 16),
3848 };
3849
3850 static const unsigned int sdhi3_wp_mux[] = {
3851         SD3_WP_MARK,
3852 };
3853
3854 static const unsigned int sdhi3_ds_pins[] = {
3855         /* DS */
3856         RCAR_GP_PIN(4, 17),
3857 };
3858
3859 static const unsigned int sdhi3_ds_mux[] = {
3860         SD3_DS_MARK,
3861 };
3862
3863 /* - SSI -------------------------------------------------------------------- */
3864 static const unsigned int ssi0_data_pins[] = {
3865         /* SDATA */
3866         RCAR_GP_PIN(6, 2),
3867 };
3868 static const unsigned int ssi0_data_mux[] = {
3869         SSI_SDATA0_MARK,
3870 };
3871 static const unsigned int ssi01239_ctrl_pins[] = {
3872         /* SCK, WS */
3873         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3874 };
3875 static const unsigned int ssi01239_ctrl_mux[] = {
3876         SSI_SCK01239_MARK, SSI_WS01239_MARK,
3877 };
3878 static const unsigned int ssi1_data_a_pins[] = {
3879         /* SDATA */
3880         RCAR_GP_PIN(6, 3),
3881 };
3882 static const unsigned int ssi1_data_a_mux[] = {
3883         SSI_SDATA1_A_MARK,
3884 };
3885 static const unsigned int ssi1_data_b_pins[] = {
3886         /* SDATA */
3887         RCAR_GP_PIN(5, 12),
3888 };
3889 static const unsigned int ssi1_data_b_mux[] = {
3890         SSI_SDATA1_B_MARK,
3891 };
3892 static const unsigned int ssi1_ctrl_a_pins[] = {
3893         /* SCK, WS */
3894         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3895 };
3896 static const unsigned int ssi1_ctrl_a_mux[] = {
3897         SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3898 };
3899 static const unsigned int ssi1_ctrl_b_pins[] = {
3900         /* SCK, WS */
3901         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3902 };
3903 static const unsigned int ssi1_ctrl_b_mux[] = {
3904         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3905 };
3906 static const unsigned int ssi2_data_a_pins[] = {
3907         /* SDATA */
3908         RCAR_GP_PIN(6, 4),
3909 };
3910 static const unsigned int ssi2_data_a_mux[] = {
3911         SSI_SDATA2_A_MARK,
3912 };
3913 static const unsigned int ssi2_data_b_pins[] = {
3914         /* SDATA */
3915         RCAR_GP_PIN(5, 13),
3916 };
3917 static const unsigned int ssi2_data_b_mux[] = {
3918         SSI_SDATA2_B_MARK,
3919 };
3920 static const unsigned int ssi2_ctrl_a_pins[] = {
3921         /* SCK, WS */
3922         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3923 };
3924 static const unsigned int ssi2_ctrl_a_mux[] = {
3925         SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3926 };
3927 static const unsigned int ssi2_ctrl_b_pins[] = {
3928         /* SCK, WS */
3929         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3930 };
3931 static const unsigned int ssi2_ctrl_b_mux[] = {
3932         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3933 };
3934 static const unsigned int ssi3_data_pins[] = {
3935         /* SDATA */
3936         RCAR_GP_PIN(6, 7),
3937 };
3938 static const unsigned int ssi3_data_mux[] = {
3939         SSI_SDATA3_MARK,
3940 };
3941 static const unsigned int ssi349_ctrl_pins[] = {
3942         /* SCK, WS */
3943         RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3944 };
3945 static const unsigned int ssi349_ctrl_mux[] = {
3946         SSI_SCK349_MARK, SSI_WS349_MARK,
3947 };
3948 static const unsigned int ssi4_data_pins[] = {
3949         /* SDATA */
3950         RCAR_GP_PIN(6, 10),
3951 };
3952 static const unsigned int ssi4_data_mux[] = {
3953         SSI_SDATA4_MARK,
3954 };
3955 static const unsigned int ssi4_ctrl_pins[] = {
3956         /* SCK, WS */
3957         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3958 };
3959 static const unsigned int ssi4_ctrl_mux[] = {
3960         SSI_SCK4_MARK, SSI_WS4_MARK,
3961 };
3962 static const unsigned int ssi5_data_pins[] = {
3963         /* SDATA */
3964         RCAR_GP_PIN(6, 13),
3965 };
3966 static const unsigned int ssi5_data_mux[] = {
3967         SSI_SDATA5_MARK,
3968 };
3969 static const unsigned int ssi5_ctrl_pins[] = {
3970         /* SCK, WS */
3971         RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3972 };
3973 static const unsigned int ssi5_ctrl_mux[] = {
3974         SSI_SCK5_MARK, SSI_WS5_MARK,
3975 };
3976 static const unsigned int ssi6_data_pins[] = {
3977         /* SDATA */
3978         RCAR_GP_PIN(6, 16),
3979 };
3980 static const unsigned int ssi6_data_mux[] = {
3981         SSI_SDATA6_MARK,
3982 };
3983 static const unsigned int ssi6_ctrl_pins[] = {
3984         /* SCK, WS */
3985         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3986 };
3987 static const unsigned int ssi6_ctrl_mux[] = {
3988         SSI_SCK6_MARK, SSI_WS6_MARK,
3989 };
3990 static const unsigned int ssi7_data_pins[] = {
3991         /* SDATA */
3992         RCAR_GP_PIN(6, 19),
3993 };
3994 static const unsigned int ssi7_data_mux[] = {
3995         SSI_SDATA7_MARK,
3996 };
3997 static const unsigned int ssi78_ctrl_pins[] = {
3998         /* SCK, WS */
3999         RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
4000 };
4001 static const unsigned int ssi78_ctrl_mux[] = {
4002         SSI_SCK78_MARK, SSI_WS78_MARK,
4003 };
4004 static const unsigned int ssi8_data_pins[] = {
4005         /* SDATA */
4006         RCAR_GP_PIN(6, 20),
4007 };
4008 static const unsigned int ssi8_data_mux[] = {
4009         SSI_SDATA8_MARK,
4010 };
4011 static const unsigned int ssi9_data_a_pins[] = {
4012         /* SDATA */
4013         RCAR_GP_PIN(6, 21),
4014 };
4015 static const unsigned int ssi9_data_a_mux[] = {
4016         SSI_SDATA9_A_MARK,
4017 };
4018 static const unsigned int ssi9_data_b_pins[] = {
4019         /* SDATA */
4020         RCAR_GP_PIN(5, 14),
4021 };
4022 static const unsigned int ssi9_data_b_mux[] = {
4023         SSI_SDATA9_B_MARK,
4024 };
4025 static const unsigned int ssi9_ctrl_a_pins[] = {
4026         /* SCK, WS */
4027         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4028 };
4029 static const unsigned int ssi9_ctrl_a_mux[] = {
4030         SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4031 };
4032 static const unsigned int ssi9_ctrl_b_pins[] = {
4033         /* SCK, WS */
4034         RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4035 };
4036 static const unsigned int ssi9_ctrl_b_mux[] = {
4037         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4038 };
4039
4040 /* - TMU -------------------------------------------------------------------- */
4041 static const unsigned int tmu_tclk1_a_pins[] = {
4042         /* TCLK */
4043         RCAR_GP_PIN(6, 23),
4044 };
4045
4046 static const unsigned int tmu_tclk1_a_mux[] = {
4047         TCLK1_A_MARK,
4048 };
4049
4050 static const unsigned int tmu_tclk1_b_pins[] = {
4051         /* TCLK */
4052         RCAR_GP_PIN(5, 19),
4053 };
4054
4055 static const unsigned int tmu_tclk1_b_mux[] = {
4056         TCLK1_B_MARK,
4057 };
4058
4059 static const unsigned int tmu_tclk2_a_pins[] = {
4060         /* TCLK */
4061         RCAR_GP_PIN(6, 19),
4062 };
4063
4064 static const unsigned int tmu_tclk2_a_mux[] = {
4065         TCLK2_A_MARK,
4066 };
4067
4068 static const unsigned int tmu_tclk2_b_pins[] = {
4069         /* TCLK */
4070         RCAR_GP_PIN(6, 28),
4071 };
4072
4073 static const unsigned int tmu_tclk2_b_mux[] = {
4074         TCLK2_B_MARK,
4075 };
4076
4077 /* - USB0 ------------------------------------------------------------------- */
4078 static const unsigned int usb0_pins[] = {
4079         /* PWEN, OVC */
4080         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4081 };
4082
4083 static const unsigned int usb0_mux[] = {
4084         USB0_PWEN_MARK, USB0_OVC_MARK,
4085 };
4086
4087 /* - USB1 ------------------------------------------------------------------- */
4088 static const unsigned int usb1_pins[] = {
4089         /* PWEN, OVC */
4090         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4091 };
4092
4093 static const unsigned int usb1_mux[] = {
4094         USB1_PWEN_MARK, USB1_OVC_MARK,
4095 };
4096
4097 /* - USB30 ------------------------------------------------------------------ */
4098 static const unsigned int usb30_pins[] = {
4099         /* PWEN, OVC */
4100         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4101 };
4102
4103 static const unsigned int usb30_mux[] = {
4104         USB30_PWEN_MARK, USB30_OVC_MARK,
4105 };
4106
4107 /* - VIN4 ------------------------------------------------------------------- */
4108 static const unsigned int vin4_data18_a_pins[] = {
4109         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4110         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4111         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4112         RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
4113         RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
4114         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
4115         RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
4116         RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
4117         RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
4118 };
4119
4120 static const unsigned int vin4_data18_a_mux[] = {
4121         VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4122         VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4123         VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4124         VI4_DATA10_MARK,  VI4_DATA11_MARK,
4125         VI4_DATA12_MARK,  VI4_DATA13_MARK,
4126         VI4_DATA14_MARK,  VI4_DATA15_MARK,
4127         VI4_DATA18_MARK,  VI4_DATA19_MARK,
4128         VI4_DATA20_MARK,  VI4_DATA21_MARK,
4129         VI4_DATA22_MARK,  VI4_DATA23_MARK,
4130 };
4131
4132 static const union vin_data vin4_data_a_pins = {
4133         .data24 = {
4134                 RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 9),
4135                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4136                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4137                 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4138                 RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
4139                 RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
4140                 RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
4141                 RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
4142                 RCAR_GP_PIN(0, 0),  RCAR_GP_PIN(0, 1),
4143                 RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
4144                 RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
4145                 RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
4146         },
4147 };
4148
4149 static const union vin_data vin4_data_a_mux = {
4150         .data24 = {
4151                 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4152                 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4153                 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4154                 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4155                 VI4_DATA8_MARK,   VI4_DATA9_MARK,
4156                 VI4_DATA10_MARK,  VI4_DATA11_MARK,
4157                 VI4_DATA12_MARK,  VI4_DATA13_MARK,
4158                 VI4_DATA14_MARK,  VI4_DATA15_MARK,
4159                 VI4_DATA16_MARK,  VI4_DATA17_MARK,
4160                 VI4_DATA18_MARK,  VI4_DATA19_MARK,
4161                 VI4_DATA20_MARK,  VI4_DATA21_MARK,
4162                 VI4_DATA22_MARK,  VI4_DATA23_MARK,
4163         },
4164 };
4165
4166 static const unsigned int vin4_data18_b_pins[] = {
4167         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4168         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4169         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4170         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4171         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4172         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4173         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4174         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4175         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4176 };
4177
4178 static const unsigned int vin4_data18_b_mux[] = {
4179         VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4180         VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4181         VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4182         VI4_DATA10_MARK,  VI4_DATA11_MARK,
4183         VI4_DATA12_MARK,  VI4_DATA13_MARK,
4184         VI4_DATA14_MARK,  VI4_DATA15_MARK,
4185         VI4_DATA18_MARK,  VI4_DATA19_MARK,
4186         VI4_DATA20_MARK,  VI4_DATA21_MARK,
4187         VI4_DATA22_MARK,  VI4_DATA23_MARK,
4188 };
4189
4190 static const union vin_data vin4_data_b_pins = {
4191         .data24 = {
4192                 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4193                 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4194                 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4195                 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4196                 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4197                 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4198                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4199                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4200                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4201                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4202                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4203                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4204         },
4205 };
4206
4207 static const union vin_data vin4_data_b_mux = {
4208         .data24 = {
4209                 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4210                 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4211                 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4212                 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4213                 VI4_DATA8_MARK,   VI4_DATA9_MARK,
4214                 VI4_DATA10_MARK,  VI4_DATA11_MARK,
4215                 VI4_DATA12_MARK,  VI4_DATA13_MARK,
4216                 VI4_DATA14_MARK,  VI4_DATA15_MARK,
4217                 VI4_DATA16_MARK,  VI4_DATA17_MARK,
4218                 VI4_DATA18_MARK,  VI4_DATA19_MARK,
4219                 VI4_DATA20_MARK,  VI4_DATA21_MARK,
4220                 VI4_DATA22_MARK,  VI4_DATA23_MARK,
4221         },
4222 };
4223
4224 static const unsigned int vin4_sync_pins[] = {
4225         /* VSYNC_N, HSYNC_N */
4226         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4227 };
4228
4229 static const unsigned int vin4_sync_mux[] = {
4230         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4231 };
4232
4233 static const unsigned int vin4_field_pins[] = {
4234         RCAR_GP_PIN(1, 16),
4235 };
4236
4237 static const unsigned int vin4_field_mux[] = {
4238         VI4_FIELD_MARK,
4239 };
4240
4241 static const unsigned int vin4_clkenb_pins[] = {
4242         RCAR_GP_PIN(1, 19),
4243 };
4244
4245 static const unsigned int vin4_clkenb_mux[] = {
4246         VI4_CLKENB_MARK,
4247 };
4248
4249 static const unsigned int vin4_clk_pins[] = {
4250         RCAR_GP_PIN(1, 27),
4251 };
4252
4253 static const unsigned int vin4_clk_mux[] = {
4254         VI4_CLK_MARK,
4255 };
4256
4257 /* - VIN5 ------------------------------------------------------------------- */
4258 static const union vin_data16 vin5_data_pins = {
4259         .data16 = {
4260                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4261                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4262                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4263                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4264                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4265                 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4266                 RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
4267                 RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
4268         },
4269 };
4270
4271 static const union vin_data16 vin5_data_mux = {
4272         .data16 = {
4273                 VI5_DATA0_MARK, VI5_DATA1_MARK,
4274                 VI5_DATA2_MARK, VI5_DATA3_MARK,
4275                 VI5_DATA4_MARK, VI5_DATA5_MARK,
4276                 VI5_DATA6_MARK, VI5_DATA7_MARK,
4277                 VI5_DATA8_MARK,  VI5_DATA9_MARK,
4278                 VI5_DATA10_MARK, VI5_DATA11_MARK,
4279                 VI5_DATA12_MARK, VI5_DATA13_MARK,
4280                 VI5_DATA14_MARK, VI5_DATA15_MARK,
4281         },
4282 };
4283
4284 static const unsigned int vin5_sync_pins[] = {
4285         /* VSYNC_N, HSYNC_N */
4286         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4287 };
4288
4289 static const unsigned int vin5_sync_mux[] = {
4290         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4291 };
4292
4293 static const unsigned int vin5_field_pins[] = {
4294         RCAR_GP_PIN(1, 11),
4295 };
4296
4297 static const unsigned int vin5_field_mux[] = {
4298         VI5_FIELD_MARK,
4299 };
4300
4301 static const unsigned int vin5_clkenb_pins[] = {
4302         RCAR_GP_PIN(1, 20),
4303 };
4304
4305 static const unsigned int vin5_clkenb_mux[] = {
4306         VI5_CLKENB_MARK,
4307 };
4308
4309 static const unsigned int vin5_clk_pins[] = {
4310         RCAR_GP_PIN(1, 21),
4311 };
4312
4313 static const unsigned int vin5_clk_mux[] = {
4314         VI5_CLK_MARK,
4315 };
4316
4317 static const struct sh_pfc_pin_group pinmux_groups[] = {
4318         SH_PFC_PIN_GROUP(audio_clk_a_a),
4319         SH_PFC_PIN_GROUP(audio_clk_a_b),
4320         SH_PFC_PIN_GROUP(audio_clk_a_c),
4321         SH_PFC_PIN_GROUP(audio_clk_b_a),
4322         SH_PFC_PIN_GROUP(audio_clk_b_b),
4323         SH_PFC_PIN_GROUP(audio_clk_c_a),
4324         SH_PFC_PIN_GROUP(audio_clk_c_b),
4325         SH_PFC_PIN_GROUP(audio_clkout_a),
4326         SH_PFC_PIN_GROUP(audio_clkout_b),
4327         SH_PFC_PIN_GROUP(audio_clkout_c),
4328         SH_PFC_PIN_GROUP(audio_clkout_d),
4329         SH_PFC_PIN_GROUP(audio_clkout1_a),
4330         SH_PFC_PIN_GROUP(audio_clkout1_b),
4331         SH_PFC_PIN_GROUP(audio_clkout2_a),
4332         SH_PFC_PIN_GROUP(audio_clkout2_b),
4333         SH_PFC_PIN_GROUP(audio_clkout3_a),
4334         SH_PFC_PIN_GROUP(audio_clkout3_b),
4335         SH_PFC_PIN_GROUP(avb_link),
4336         SH_PFC_PIN_GROUP(avb_magic),
4337         SH_PFC_PIN_GROUP(avb_phy_int),
4338         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),      /* Deprecated */
4339         SH_PFC_PIN_GROUP(avb_mdio),
4340         SH_PFC_PIN_GROUP(avb_mii),
4341         SH_PFC_PIN_GROUP(avb_avtp_pps),
4342         SH_PFC_PIN_GROUP(avb_avtp_match_a),
4343         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4344         SH_PFC_PIN_GROUP(avb_avtp_match_b),
4345         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4346         SH_PFC_PIN_GROUP(can0_data_a),
4347         SH_PFC_PIN_GROUP(can0_data_b),
4348         SH_PFC_PIN_GROUP(can1_data),
4349         SH_PFC_PIN_GROUP(can_clk),
4350         SH_PFC_PIN_GROUP(canfd0_data_a),
4351         SH_PFC_PIN_GROUP(canfd0_data_b),
4352         SH_PFC_PIN_GROUP(canfd1_data),
4353         SH_PFC_PIN_GROUP(drif0_ctrl_a),
4354         SH_PFC_PIN_GROUP(drif0_data0_a),
4355         SH_PFC_PIN_GROUP(drif0_data1_a),
4356         SH_PFC_PIN_GROUP(drif0_ctrl_b),
4357         SH_PFC_PIN_GROUP(drif0_data0_b),
4358         SH_PFC_PIN_GROUP(drif0_data1_b),
4359         SH_PFC_PIN_GROUP(drif0_ctrl_c),
4360         SH_PFC_PIN_GROUP(drif0_data0_c),
4361         SH_PFC_PIN_GROUP(drif0_data1_c),
4362         SH_PFC_PIN_GROUP(drif1_ctrl_a),
4363         SH_PFC_PIN_GROUP(drif1_data0_a),
4364         SH_PFC_PIN_GROUP(drif1_data1_a),
4365         SH_PFC_PIN_GROUP(drif1_ctrl_b),
4366         SH_PFC_PIN_GROUP(drif1_data0_b),
4367         SH_PFC_PIN_GROUP(drif1_data1_b),
4368         SH_PFC_PIN_GROUP(drif1_ctrl_c),
4369         SH_PFC_PIN_GROUP(drif1_data0_c),
4370         SH_PFC_PIN_GROUP(drif1_data1_c),
4371         SH_PFC_PIN_GROUP(drif2_ctrl_a),
4372         SH_PFC_PIN_GROUP(drif2_data0_a),
4373         SH_PFC_PIN_GROUP(drif2_data1_a),
4374         SH_PFC_PIN_GROUP(drif2_ctrl_b),
4375         SH_PFC_PIN_GROUP(drif2_data0_b),
4376         SH_PFC_PIN_GROUP(drif2_data1_b),
4377         SH_PFC_PIN_GROUP(drif3_ctrl_a),
4378         SH_PFC_PIN_GROUP(drif3_data0_a),
4379         SH_PFC_PIN_GROUP(drif3_data1_a),
4380         SH_PFC_PIN_GROUP(drif3_ctrl_b),
4381         SH_PFC_PIN_GROUP(drif3_data0_b),
4382         SH_PFC_PIN_GROUP(drif3_data1_b),
4383         SH_PFC_PIN_GROUP(du_rgb666),
4384         SH_PFC_PIN_GROUP(du_rgb888),
4385         SH_PFC_PIN_GROUP(du_clk_out_0),
4386         SH_PFC_PIN_GROUP(du_clk_out_1),
4387         SH_PFC_PIN_GROUP(du_sync),
4388         SH_PFC_PIN_GROUP(du_oddf),
4389         SH_PFC_PIN_GROUP(du_cde),
4390         SH_PFC_PIN_GROUP(du_disp),
4391         SH_PFC_PIN_GROUP(hscif0_data),
4392         SH_PFC_PIN_GROUP(hscif0_clk),
4393         SH_PFC_PIN_GROUP(hscif0_ctrl),
4394         SH_PFC_PIN_GROUP(hscif1_data_a),
4395         SH_PFC_PIN_GROUP(hscif1_clk_a),
4396         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4397         SH_PFC_PIN_GROUP(hscif1_data_b),
4398         SH_PFC_PIN_GROUP(hscif1_clk_b),
4399         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4400         SH_PFC_PIN_GROUP(hscif2_data_a),
4401         SH_PFC_PIN_GROUP(hscif2_clk_a),
4402         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4403         SH_PFC_PIN_GROUP(hscif2_data_b),
4404         SH_PFC_PIN_GROUP(hscif2_clk_b),
4405         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4406         SH_PFC_PIN_GROUP(hscif2_data_c),
4407         SH_PFC_PIN_GROUP(hscif2_clk_c),
4408         SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4409         SH_PFC_PIN_GROUP(hscif3_data_a),
4410         SH_PFC_PIN_GROUP(hscif3_clk),
4411         SH_PFC_PIN_GROUP(hscif3_ctrl),
4412         SH_PFC_PIN_GROUP(hscif3_data_b),
4413         SH_PFC_PIN_GROUP(hscif3_data_c),
4414         SH_PFC_PIN_GROUP(hscif3_data_d),
4415         SH_PFC_PIN_GROUP(hscif4_data_a),
4416         SH_PFC_PIN_GROUP(hscif4_clk),
4417         SH_PFC_PIN_GROUP(hscif4_ctrl),
4418         SH_PFC_PIN_GROUP(hscif4_data_b),
4419         SH_PFC_PIN_GROUP(i2c1_a),
4420         SH_PFC_PIN_GROUP(i2c1_b),
4421         SH_PFC_PIN_GROUP(i2c2_a),
4422         SH_PFC_PIN_GROUP(i2c2_b),
4423         SH_PFC_PIN_GROUP(i2c6_a),
4424         SH_PFC_PIN_GROUP(i2c6_b),
4425         SH_PFC_PIN_GROUP(i2c6_c),
4426         SH_PFC_PIN_GROUP(intc_ex_irq0),
4427         SH_PFC_PIN_GROUP(intc_ex_irq1),
4428         SH_PFC_PIN_GROUP(intc_ex_irq2),
4429         SH_PFC_PIN_GROUP(intc_ex_irq3),
4430         SH_PFC_PIN_GROUP(intc_ex_irq4),
4431         SH_PFC_PIN_GROUP(intc_ex_irq5),
4432         SH_PFC_PIN_GROUP(msiof0_clk),
4433         SH_PFC_PIN_GROUP(msiof0_sync),
4434         SH_PFC_PIN_GROUP(msiof0_ss1),
4435         SH_PFC_PIN_GROUP(msiof0_ss2),
4436         SH_PFC_PIN_GROUP(msiof0_txd),
4437         SH_PFC_PIN_GROUP(msiof0_rxd),
4438         SH_PFC_PIN_GROUP(msiof1_clk_a),
4439         SH_PFC_PIN_GROUP(msiof1_sync_a),
4440         SH_PFC_PIN_GROUP(msiof1_ss1_a),
4441         SH_PFC_PIN_GROUP(msiof1_ss2_a),
4442         SH_PFC_PIN_GROUP(msiof1_txd_a),
4443         SH_PFC_PIN_GROUP(msiof1_rxd_a),
4444         SH_PFC_PIN_GROUP(msiof1_clk_b),
4445         SH_PFC_PIN_GROUP(msiof1_sync_b),
4446         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4447         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4448         SH_PFC_PIN_GROUP(msiof1_txd_b),
4449         SH_PFC_PIN_GROUP(msiof1_rxd_b),
4450         SH_PFC_PIN_GROUP(msiof1_clk_c),
4451         SH_PFC_PIN_GROUP(msiof1_sync_c),
4452         SH_PFC_PIN_GROUP(msiof1_ss1_c),
4453         SH_PFC_PIN_GROUP(msiof1_ss2_c),
4454         SH_PFC_PIN_GROUP(msiof1_txd_c),
4455         SH_PFC_PIN_GROUP(msiof1_rxd_c),
4456         SH_PFC_PIN_GROUP(msiof1_clk_d),
4457         SH_PFC_PIN_GROUP(msiof1_sync_d),
4458         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4459         SH_PFC_PIN_GROUP(msiof1_ss2_d),
4460         SH_PFC_PIN_GROUP(msiof1_txd_d),
4461         SH_PFC_PIN_GROUP(msiof1_rxd_d),
4462         SH_PFC_PIN_GROUP(msiof1_clk_e),
4463         SH_PFC_PIN_GROUP(msiof1_sync_e),
4464         SH_PFC_PIN_GROUP(msiof1_ss1_e),
4465         SH_PFC_PIN_GROUP(msiof1_ss2_e),
4466         SH_PFC_PIN_GROUP(msiof1_txd_e),
4467         SH_PFC_PIN_GROUP(msiof1_rxd_e),
4468         SH_PFC_PIN_GROUP(msiof1_clk_f),
4469         SH_PFC_PIN_GROUP(msiof1_sync_f),
4470         SH_PFC_PIN_GROUP(msiof1_ss1_f),
4471         SH_PFC_PIN_GROUP(msiof1_ss2_f),
4472         SH_PFC_PIN_GROUP(msiof1_txd_f),
4473         SH_PFC_PIN_GROUP(msiof1_rxd_f),
4474         SH_PFC_PIN_GROUP(msiof1_clk_g),
4475         SH_PFC_PIN_GROUP(msiof1_sync_g),
4476         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4477         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4478         SH_PFC_PIN_GROUP(msiof1_txd_g),
4479         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4480         SH_PFC_PIN_GROUP(msiof2_clk_a),
4481         SH_PFC_PIN_GROUP(msiof2_sync_a),
4482         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4483         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4484         SH_PFC_PIN_GROUP(msiof2_txd_a),
4485         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4486         SH_PFC_PIN_GROUP(msiof2_clk_b),
4487         SH_PFC_PIN_GROUP(msiof2_sync_b),
4488         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4489         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4490         SH_PFC_PIN_GROUP(msiof2_txd_b),
4491         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4492         SH_PFC_PIN_GROUP(msiof2_clk_c),
4493         SH_PFC_PIN_GROUP(msiof2_sync_c),
4494         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4495         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4496         SH_PFC_PIN_GROUP(msiof2_txd_c),
4497         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4498         SH_PFC_PIN_GROUP(msiof2_clk_d),
4499         SH_PFC_PIN_GROUP(msiof2_sync_d),
4500         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4501         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4502         SH_PFC_PIN_GROUP(msiof2_txd_d),
4503         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4504         SH_PFC_PIN_GROUP(msiof3_clk_a),
4505         SH_PFC_PIN_GROUP(msiof3_sync_a),
4506         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4507         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4508         SH_PFC_PIN_GROUP(msiof3_txd_a),
4509         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4510         SH_PFC_PIN_GROUP(msiof3_clk_b),
4511         SH_PFC_PIN_GROUP(msiof3_sync_b),
4512         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4513         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4514         SH_PFC_PIN_GROUP(msiof3_txd_b),
4515         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4516         SH_PFC_PIN_GROUP(msiof3_clk_c),
4517         SH_PFC_PIN_GROUP(msiof3_sync_c),
4518         SH_PFC_PIN_GROUP(msiof3_txd_c),
4519         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4520         SH_PFC_PIN_GROUP(msiof3_clk_d),
4521         SH_PFC_PIN_GROUP(msiof3_sync_d),
4522         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4523         SH_PFC_PIN_GROUP(msiof3_txd_d),
4524         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4525         SH_PFC_PIN_GROUP(msiof3_clk_e),
4526         SH_PFC_PIN_GROUP(msiof3_sync_e),
4527         SH_PFC_PIN_GROUP(msiof3_ss1_e),
4528         SH_PFC_PIN_GROUP(msiof3_ss2_e),
4529         SH_PFC_PIN_GROUP(msiof3_txd_e),
4530         SH_PFC_PIN_GROUP(msiof3_rxd_e),
4531         SH_PFC_PIN_GROUP(pwm0),
4532         SH_PFC_PIN_GROUP(pwm1_a),
4533         SH_PFC_PIN_GROUP(pwm1_b),
4534         SH_PFC_PIN_GROUP(pwm2_a),
4535         SH_PFC_PIN_GROUP(pwm2_b),
4536         SH_PFC_PIN_GROUP(pwm3_a),
4537         SH_PFC_PIN_GROUP(pwm3_b),
4538         SH_PFC_PIN_GROUP(pwm4_a),
4539         SH_PFC_PIN_GROUP(pwm4_b),
4540         SH_PFC_PIN_GROUP(pwm5_a),
4541         SH_PFC_PIN_GROUP(pwm5_b),
4542         SH_PFC_PIN_GROUP(pwm6_a),
4543         SH_PFC_PIN_GROUP(pwm6_b),
4544         SH_PFC_PIN_GROUP(sata0_devslp_a),
4545         SH_PFC_PIN_GROUP(sata0_devslp_b),
4546         SH_PFC_PIN_GROUP(scif0_data),
4547         SH_PFC_PIN_GROUP(scif0_clk),
4548         SH_PFC_PIN_GROUP(scif0_ctrl),
4549         SH_PFC_PIN_GROUP(scif1_data_a),
4550         SH_PFC_PIN_GROUP(scif1_clk),
4551         SH_PFC_PIN_GROUP(scif1_ctrl),
4552         SH_PFC_PIN_GROUP(scif1_data_b),
4553         SH_PFC_PIN_GROUP(scif2_data_a),
4554         SH_PFC_PIN_GROUP(scif2_clk),
4555         SH_PFC_PIN_GROUP(scif2_data_b),
4556         SH_PFC_PIN_GROUP(scif3_data_a),
4557         SH_PFC_PIN_GROUP(scif3_clk),
4558         SH_PFC_PIN_GROUP(scif3_ctrl),
4559         SH_PFC_PIN_GROUP(scif3_data_b),
4560         SH_PFC_PIN_GROUP(scif4_data_a),
4561         SH_PFC_PIN_GROUP(scif4_clk_a),
4562         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4563         SH_PFC_PIN_GROUP(scif4_data_b),
4564         SH_PFC_PIN_GROUP(scif4_clk_b),
4565         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4566         SH_PFC_PIN_GROUP(scif4_data_c),
4567         SH_PFC_PIN_GROUP(scif4_clk_c),
4568         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4569         SH_PFC_PIN_GROUP(scif5_data_a),
4570         SH_PFC_PIN_GROUP(scif5_clk_a),
4571         SH_PFC_PIN_GROUP(scif5_data_b),
4572         SH_PFC_PIN_GROUP(scif5_clk_b),
4573         SH_PFC_PIN_GROUP(scif_clk_a),
4574         SH_PFC_PIN_GROUP(scif_clk_b),
4575         SH_PFC_PIN_GROUP(sdhi0_data1),
4576         SH_PFC_PIN_GROUP(sdhi0_data4),
4577         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4578         SH_PFC_PIN_GROUP(sdhi0_cd),
4579         SH_PFC_PIN_GROUP(sdhi0_wp),
4580         SH_PFC_PIN_GROUP(sdhi1_data1),
4581         SH_PFC_PIN_GROUP(sdhi1_data4),
4582         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4583         SH_PFC_PIN_GROUP(sdhi1_cd),
4584         SH_PFC_PIN_GROUP(sdhi1_wp),
4585         SH_PFC_PIN_GROUP(sdhi2_data1),
4586         SH_PFC_PIN_GROUP(sdhi2_data4),
4587         SH_PFC_PIN_GROUP(sdhi2_data8),
4588         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4589         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4590         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4591         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4592         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4593         SH_PFC_PIN_GROUP(sdhi2_ds),
4594         SH_PFC_PIN_GROUP(sdhi3_data1),
4595         SH_PFC_PIN_GROUP(sdhi3_data4),
4596         SH_PFC_PIN_GROUP(sdhi3_data8),
4597         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4598         SH_PFC_PIN_GROUP(sdhi3_cd),
4599         SH_PFC_PIN_GROUP(sdhi3_wp),
4600         SH_PFC_PIN_GROUP(sdhi3_ds),
4601         SH_PFC_PIN_GROUP(ssi0_data),
4602         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4603         SH_PFC_PIN_GROUP(ssi1_data_a),
4604         SH_PFC_PIN_GROUP(ssi1_data_b),
4605         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4606         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4607         SH_PFC_PIN_GROUP(ssi2_data_a),
4608         SH_PFC_PIN_GROUP(ssi2_data_b),
4609         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4610         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4611         SH_PFC_PIN_GROUP(ssi3_data),
4612         SH_PFC_PIN_GROUP(ssi349_ctrl),
4613         SH_PFC_PIN_GROUP(ssi4_data),
4614         SH_PFC_PIN_GROUP(ssi4_ctrl),
4615         SH_PFC_PIN_GROUP(ssi5_data),
4616         SH_PFC_PIN_GROUP(ssi5_ctrl),
4617         SH_PFC_PIN_GROUP(ssi6_data),
4618         SH_PFC_PIN_GROUP(ssi6_ctrl),
4619         SH_PFC_PIN_GROUP(ssi7_data),
4620         SH_PFC_PIN_GROUP(ssi78_ctrl),
4621         SH_PFC_PIN_GROUP(ssi8_data),
4622         SH_PFC_PIN_GROUP(ssi9_data_a),
4623         SH_PFC_PIN_GROUP(ssi9_data_b),
4624         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4625         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4626         SH_PFC_PIN_GROUP(tmu_tclk1_a),
4627         SH_PFC_PIN_GROUP(tmu_tclk1_b),
4628         SH_PFC_PIN_GROUP(tmu_tclk2_a),
4629         SH_PFC_PIN_GROUP(tmu_tclk2_b),
4630         SH_PFC_PIN_GROUP(usb0),
4631         SH_PFC_PIN_GROUP(usb1),
4632         SH_PFC_PIN_GROUP(usb30),
4633         VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4634         VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4635         VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4636         VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4637         SH_PFC_PIN_GROUP(vin4_data18_a),
4638         VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4639         VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4640         VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4641         VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4642         VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4643         VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4644         SH_PFC_PIN_GROUP(vin4_data18_b),
4645         VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4646         VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4647         SH_PFC_PIN_GROUP(vin4_sync),
4648         SH_PFC_PIN_GROUP(vin4_field),
4649         SH_PFC_PIN_GROUP(vin4_clkenb),
4650         SH_PFC_PIN_GROUP(vin4_clk),
4651         VIN_DATA_PIN_GROUP(vin5_data, 8),
4652         VIN_DATA_PIN_GROUP(vin5_data, 10),
4653         VIN_DATA_PIN_GROUP(vin5_data, 12),
4654         VIN_DATA_PIN_GROUP(vin5_data, 16),
4655         SH_PFC_PIN_GROUP(vin5_sync),
4656         SH_PFC_PIN_GROUP(vin5_field),
4657         SH_PFC_PIN_GROUP(vin5_clkenb),
4658         SH_PFC_PIN_GROUP(vin5_clk),
4659 };
4660
4661 static const char * const audio_clk_groups[] = {
4662         "audio_clk_a_a",
4663         "audio_clk_a_b",
4664         "audio_clk_a_c",
4665         "audio_clk_b_a",
4666         "audio_clk_b_b",
4667         "audio_clk_c_a",
4668         "audio_clk_c_b",
4669         "audio_clkout_a",
4670         "audio_clkout_b",
4671         "audio_clkout_c",
4672         "audio_clkout_d",
4673         "audio_clkout1_a",
4674         "audio_clkout1_b",
4675         "audio_clkout2_a",
4676         "audio_clkout2_b",
4677         "audio_clkout3_a",
4678         "audio_clkout3_b",
4679 };
4680
4681 static const char * const avb_groups[] = {
4682         "avb_link",
4683         "avb_magic",
4684         "avb_phy_int",
4685         "avb_mdc",      /* Deprecated, please use "avb_mdio" instead */
4686         "avb_mdio",
4687         "avb_mii",
4688         "avb_avtp_pps",
4689         "avb_avtp_match_a",
4690         "avb_avtp_capture_a",
4691         "avb_avtp_match_b",
4692         "avb_avtp_capture_b",
4693 };
4694
4695 static const char * const can0_groups[] = {
4696         "can0_data_a",
4697         "can0_data_b",
4698 };
4699
4700 static const char * const can1_groups[] = {
4701         "can1_data",
4702 };
4703
4704 static const char * const can_clk_groups[] = {
4705         "can_clk",
4706 };
4707
4708 static const char * const canfd0_groups[] = {
4709         "canfd0_data_a",
4710         "canfd0_data_b",
4711 };
4712
4713 static const char * const canfd1_groups[] = {
4714         "canfd1_data",
4715 };
4716
4717 static const char * const drif0_groups[] = {
4718         "drif0_ctrl_a",
4719         "drif0_data0_a",
4720         "drif0_data1_a",
4721         "drif0_ctrl_b",
4722         "drif0_data0_b",
4723         "drif0_data1_b",
4724         "drif0_ctrl_c",
4725         "drif0_data0_c",
4726         "drif0_data1_c",
4727 };
4728
4729 static const char * const drif1_groups[] = {
4730         "drif1_ctrl_a",
4731         "drif1_data0_a",
4732         "drif1_data1_a",
4733         "drif1_ctrl_b",
4734         "drif1_data0_b",
4735         "drif1_data1_b",
4736         "drif1_ctrl_c",
4737         "drif1_data0_c",
4738         "drif1_data1_c",
4739 };
4740
4741 static const char * const drif2_groups[] = {
4742         "drif2_ctrl_a",
4743         "drif2_data0_a",
4744         "drif2_data1_a",
4745         "drif2_ctrl_b",
4746         "drif2_data0_b",
4747         "drif2_data1_b",
4748 };
4749
4750 static const char * const drif3_groups[] = {
4751         "drif3_ctrl_a",
4752         "drif3_data0_a",
4753         "drif3_data1_a",
4754         "drif3_ctrl_b",
4755         "drif3_data0_b",
4756         "drif3_data1_b",
4757 };
4758
4759 static const char * const du_groups[] = {
4760         "du_rgb666",
4761         "du_rgb888",
4762         "du_clk_out_0",
4763         "du_clk_out_1",
4764         "du_sync",
4765         "du_oddf",
4766         "du_cde",
4767         "du_disp",
4768 };
4769
4770 static const char * const hscif0_groups[] = {
4771         "hscif0_data",
4772         "hscif0_clk",
4773         "hscif0_ctrl",
4774 };
4775
4776 static const char * const hscif1_groups[] = {
4777         "hscif1_data_a",
4778         "hscif1_clk_a",
4779         "hscif1_ctrl_a",
4780         "hscif1_data_b",
4781         "hscif1_clk_b",
4782         "hscif1_ctrl_b",
4783 };
4784
4785 static const char * const hscif2_groups[] = {
4786         "hscif2_data_a",
4787         "hscif2_clk_a",
4788         "hscif2_ctrl_a",
4789         "hscif2_data_b",
4790         "hscif2_clk_b",
4791         "hscif2_ctrl_b",
4792         "hscif2_data_c",
4793         "hscif2_clk_c",
4794         "hscif2_ctrl_c",
4795 };
4796
4797 static const char * const hscif3_groups[] = {
4798         "hscif3_data_a",
4799         "hscif3_clk",
4800         "hscif3_ctrl",
4801         "hscif3_data_b",
4802         "hscif3_data_c",
4803         "hscif3_data_d",
4804 };
4805
4806 static const char * const hscif4_groups[] = {
4807         "hscif4_data_a",
4808         "hscif4_clk",
4809         "hscif4_ctrl",
4810         "hscif4_data_b",
4811 };
4812
4813 static const char * const i2c1_groups[] = {
4814         "i2c1_a",
4815         "i2c1_b",
4816 };
4817
4818 static const char * const i2c2_groups[] = {
4819         "i2c2_a",
4820         "i2c2_b",
4821 };
4822
4823 static const char * const i2c6_groups[] = {
4824         "i2c6_a",
4825         "i2c6_b",
4826         "i2c6_c",
4827 };
4828
4829 static const char * const intc_ex_groups[] = {
4830         "intc_ex_irq0",
4831         "intc_ex_irq1",
4832         "intc_ex_irq2",
4833         "intc_ex_irq3",
4834         "intc_ex_irq4",
4835         "intc_ex_irq5",
4836 };
4837
4838 static const char * const msiof0_groups[] = {
4839         "msiof0_clk",
4840         "msiof0_sync",
4841         "msiof0_ss1",
4842         "msiof0_ss2",
4843         "msiof0_txd",
4844         "msiof0_rxd",
4845 };
4846
4847 static const char * const msiof1_groups[] = {
4848         "msiof1_clk_a",
4849         "msiof1_sync_a",
4850         "msiof1_ss1_a",
4851         "msiof1_ss2_a",
4852         "msiof1_txd_a",
4853         "msiof1_rxd_a",
4854         "msiof1_clk_b",
4855         "msiof1_sync_b",
4856         "msiof1_ss1_b",
4857         "msiof1_ss2_b",
4858         "msiof1_txd_b",
4859         "msiof1_rxd_b",
4860         "msiof1_clk_c",
4861         "msiof1_sync_c",
4862         "msiof1_ss1_c",
4863         "msiof1_ss2_c",
4864         "msiof1_txd_c",
4865         "msiof1_rxd_c",
4866         "msiof1_clk_d",
4867         "msiof1_sync_d",
4868         "msiof1_ss1_d",
4869         "msiof1_ss2_d",
4870         "msiof1_txd_d",
4871         "msiof1_rxd_d",
4872         "msiof1_clk_e",
4873         "msiof1_sync_e",
4874         "msiof1_ss1_e",
4875         "msiof1_ss2_e",
4876         "msiof1_txd_e",
4877         "msiof1_rxd_e",
4878         "msiof1_clk_f",
4879         "msiof1_sync_f",
4880         "msiof1_ss1_f",
4881         "msiof1_ss2_f",
4882         "msiof1_txd_f",
4883         "msiof1_rxd_f",
4884         "msiof1_clk_g",
4885         "msiof1_sync_g",
4886         "msiof1_ss1_g",
4887         "msiof1_ss2_g",
4888         "msiof1_txd_g",
4889         "msiof1_rxd_g",
4890 };
4891
4892 static const char * const msiof2_groups[] = {
4893         "msiof2_clk_a",
4894         "msiof2_sync_a",
4895         "msiof2_ss1_a",
4896         "msiof2_ss2_a",
4897         "msiof2_txd_a",
4898         "msiof2_rxd_a",
4899         "msiof2_clk_b",
4900         "msiof2_sync_b",
4901         "msiof2_ss1_b",
4902         "msiof2_ss2_b",
4903         "msiof2_txd_b",
4904         "msiof2_rxd_b",
4905         "msiof2_clk_c",
4906         "msiof2_sync_c",
4907         "msiof2_ss1_c",
4908         "msiof2_ss2_c",
4909         "msiof2_txd_c",
4910         "msiof2_rxd_c",
4911         "msiof2_clk_d",
4912         "msiof2_sync_d",
4913         "msiof2_ss1_d",
4914         "msiof2_ss2_d",
4915         "msiof2_txd_d",
4916         "msiof2_rxd_d",
4917 };
4918
4919 static const char * const msiof3_groups[] = {
4920         "msiof3_clk_a",
4921         "msiof3_sync_a",
4922         "msiof3_ss1_a",
4923         "msiof3_ss2_a",
4924         "msiof3_txd_a",
4925         "msiof3_rxd_a",
4926         "msiof3_clk_b",
4927         "msiof3_sync_b",
4928         "msiof3_ss1_b",
4929         "msiof3_ss2_b",
4930         "msiof3_txd_b",
4931         "msiof3_rxd_b",
4932         "msiof3_clk_c",
4933         "msiof3_sync_c",
4934         "msiof3_txd_c",
4935         "msiof3_rxd_c",
4936         "msiof3_clk_d",
4937         "msiof3_sync_d",
4938         "msiof3_ss1_d",
4939         "msiof3_txd_d",
4940         "msiof3_rxd_d",
4941         "msiof3_clk_e",
4942         "msiof3_sync_e",
4943         "msiof3_ss1_e",
4944         "msiof3_ss2_e",
4945         "msiof3_txd_e",
4946         "msiof3_rxd_e",
4947 };
4948
4949 static const char * const pwm0_groups[] = {
4950         "pwm0",
4951 };
4952
4953 static const char * const pwm1_groups[] = {
4954         "pwm1_a",
4955         "pwm1_b",
4956 };
4957
4958 static const char * const pwm2_groups[] = {
4959         "pwm2_a",
4960         "pwm2_b",
4961 };
4962
4963 static const char * const pwm3_groups[] = {
4964         "pwm3_a",
4965         "pwm3_b",
4966 };
4967
4968 static const char * const pwm4_groups[] = {
4969         "pwm4_a",
4970         "pwm4_b",
4971 };
4972
4973 static const char * const pwm5_groups[] = {
4974         "pwm5_a",
4975         "pwm5_b",
4976 };
4977
4978 static const char * const pwm6_groups[] = {
4979         "pwm6_a",
4980         "pwm6_b",
4981 };
4982
4983 static const char * const sata0_groups[] = {
4984         "sata0_devslp_a",
4985         "sata0_devslp_b",
4986 };
4987
4988 static const char * const scif0_groups[] = {
4989         "scif0_data",
4990         "scif0_clk",
4991         "scif0_ctrl",
4992 };
4993
4994 static const char * const scif1_groups[] = {
4995         "scif1_data_a",
4996         "scif1_clk",
4997         "scif1_ctrl",
4998         "scif1_data_b",
4999 };
5000 static const char * const scif2_groups[] = {
5001         "scif2_data_a",
5002         "scif2_clk",
5003         "scif2_data_b",
5004 };
5005
5006 static const char * const scif3_groups[] = {
5007         "scif3_data_a",
5008         "scif3_clk",
5009         "scif3_ctrl",
5010         "scif3_data_b",
5011 };
5012
5013 static const char * const scif4_groups[] = {
5014         "scif4_data_a",
5015         "scif4_clk_a",
5016         "scif4_ctrl_a",
5017         "scif4_data_b",
5018         "scif4_clk_b",
5019         "scif4_ctrl_b",
5020         "scif4_data_c",
5021         "scif4_clk_c",
5022         "scif4_ctrl_c",
5023 };
5024
5025 static const char * const scif5_groups[] = {
5026         "scif5_data_a",
5027         "scif5_clk_a",
5028         "scif5_data_b",
5029         "scif5_clk_b",
5030 };
5031
5032 static const char * const scif_clk_groups[] = {
5033         "scif_clk_a",
5034         "scif_clk_b",
5035 };
5036
5037 static const char * const sdhi0_groups[] = {
5038         "sdhi0_data1",
5039         "sdhi0_data4",
5040         "sdhi0_ctrl",
5041         "sdhi0_cd",
5042         "sdhi0_wp",
5043 };
5044
5045 static const char * const sdhi1_groups[] = {
5046         "sdhi1_data1",
5047         "sdhi1_data4",
5048         "sdhi1_ctrl",
5049         "sdhi1_cd",
5050         "sdhi1_wp",
5051 };
5052
5053 static const char * const sdhi2_groups[] = {
5054         "sdhi2_data1",
5055         "sdhi2_data4",
5056         "sdhi2_data8",
5057         "sdhi2_ctrl",
5058         "sdhi2_cd_a",
5059         "sdhi2_wp_a",
5060         "sdhi2_cd_b",
5061         "sdhi2_wp_b",
5062         "sdhi2_ds",
5063 };
5064
5065 static const char * const sdhi3_groups[] = {
5066         "sdhi3_data1",
5067         "sdhi3_data4",
5068         "sdhi3_data8",
5069         "sdhi3_ctrl",
5070         "sdhi3_cd",
5071         "sdhi3_wp",
5072         "sdhi3_ds",
5073 };
5074
5075 static const char * const ssi_groups[] = {
5076         "ssi0_data",
5077         "ssi01239_ctrl",
5078         "ssi1_data_a",
5079         "ssi1_data_b",
5080         "ssi1_ctrl_a",
5081         "ssi1_ctrl_b",
5082         "ssi2_data_a",
5083         "ssi2_data_b",
5084         "ssi2_ctrl_a",
5085         "ssi2_ctrl_b",
5086         "ssi3_data",
5087         "ssi349_ctrl",
5088         "ssi4_data",
5089         "ssi4_ctrl",
5090         "ssi5_data",
5091         "ssi5_ctrl",
5092         "ssi6_data",
5093         "ssi6_ctrl",
5094         "ssi7_data",
5095         "ssi78_ctrl",
5096         "ssi8_data",
5097         "ssi9_data_a",
5098         "ssi9_data_b",
5099         "ssi9_ctrl_a",
5100         "ssi9_ctrl_b",
5101 };
5102
5103 static const char * const tmu_groups[] = {
5104         "tmu_tclk1_a",
5105         "tmu_tclk1_b",
5106         "tmu_tclk2_a",
5107         "tmu_tclk2_b",
5108 };
5109
5110 static const char * const usb0_groups[] = {
5111         "usb0",
5112 };
5113
5114 static const char * const usb1_groups[] = {
5115         "usb1",
5116 };
5117
5118 static const char * const usb30_groups[] = {
5119         "usb30",
5120 };
5121
5122 static const char * const vin4_groups[] = {
5123         "vin4_data8_a",
5124         "vin4_data10_a",
5125         "vin4_data12_a",
5126         "vin4_data16_a",
5127         "vin4_data18_a",
5128         "vin4_data20_a",
5129         "vin4_data24_a",
5130         "vin4_data8_b",
5131         "vin4_data10_b",
5132         "vin4_data12_b",
5133         "vin4_data16_b",
5134         "vin4_data18_b",
5135         "vin4_data20_b",
5136         "vin4_data24_b",
5137         "vin4_sync",
5138         "vin4_field",
5139         "vin4_clkenb",
5140         "vin4_clk",
5141 };
5142
5143 static const char * const vin5_groups[] = {
5144         "vin5_data8",
5145         "vin5_data10",
5146         "vin5_data12",
5147         "vin5_data16",
5148         "vin5_sync",
5149         "vin5_field",
5150         "vin5_clkenb",
5151         "vin5_clk",
5152 };
5153
5154 static const struct sh_pfc_function pinmux_functions[] = {
5155         SH_PFC_FUNCTION(audio_clk),
5156         SH_PFC_FUNCTION(avb),
5157         SH_PFC_FUNCTION(can0),
5158         SH_PFC_FUNCTION(can1),
5159         SH_PFC_FUNCTION(can_clk),
5160         SH_PFC_FUNCTION(canfd0),
5161         SH_PFC_FUNCTION(canfd1),
5162         SH_PFC_FUNCTION(drif0),
5163         SH_PFC_FUNCTION(drif1),
5164         SH_PFC_FUNCTION(drif2),
5165         SH_PFC_FUNCTION(drif3),
5166         SH_PFC_FUNCTION(du),
5167         SH_PFC_FUNCTION(hscif0),
5168         SH_PFC_FUNCTION(hscif1),
5169         SH_PFC_FUNCTION(hscif2),
5170         SH_PFC_FUNCTION(hscif3),
5171         SH_PFC_FUNCTION(hscif4),
5172         SH_PFC_FUNCTION(i2c1),
5173         SH_PFC_FUNCTION(i2c2),
5174         SH_PFC_FUNCTION(i2c6),
5175         SH_PFC_FUNCTION(intc_ex),
5176         SH_PFC_FUNCTION(msiof0),
5177         SH_PFC_FUNCTION(msiof1),
5178         SH_PFC_FUNCTION(msiof2),
5179         SH_PFC_FUNCTION(msiof3),
5180         SH_PFC_FUNCTION(pwm0),
5181         SH_PFC_FUNCTION(pwm1),
5182         SH_PFC_FUNCTION(pwm2),
5183         SH_PFC_FUNCTION(pwm3),
5184         SH_PFC_FUNCTION(pwm4),
5185         SH_PFC_FUNCTION(pwm5),
5186         SH_PFC_FUNCTION(pwm6),
5187         SH_PFC_FUNCTION(sata0),
5188         SH_PFC_FUNCTION(scif0),
5189         SH_PFC_FUNCTION(scif1),
5190         SH_PFC_FUNCTION(scif2),
5191         SH_PFC_FUNCTION(scif3),
5192         SH_PFC_FUNCTION(scif4),
5193         SH_PFC_FUNCTION(scif5),
5194         SH_PFC_FUNCTION(scif_clk),
5195         SH_PFC_FUNCTION(sdhi0),
5196         SH_PFC_FUNCTION(sdhi1),
5197         SH_PFC_FUNCTION(sdhi2),
5198         SH_PFC_FUNCTION(sdhi3),
5199         SH_PFC_FUNCTION(ssi),
5200         SH_PFC_FUNCTION(tmu),
5201         SH_PFC_FUNCTION(usb0),
5202         SH_PFC_FUNCTION(usb1),
5203         SH_PFC_FUNCTION(usb30),
5204         SH_PFC_FUNCTION(vin4),
5205         SH_PFC_FUNCTION(vin5),
5206 };
5207
5208 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5209 #define F_(x, y)        FN_##y
5210 #define FM(x)           FN_##x
5211         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5212                 0, 0,
5213                 0, 0,
5214                 0, 0,
5215                 0, 0,
5216                 0, 0,
5217                 0, 0,
5218                 0, 0,
5219                 0, 0,
5220                 0, 0,
5221                 0, 0,
5222                 0, 0,
5223                 0, 0,
5224                 0, 0,
5225                 0, 0,
5226                 0, 0,
5227                 0, 0,
5228                 GP_0_15_FN,     GPSR0_15,
5229                 GP_0_14_FN,     GPSR0_14,
5230                 GP_0_13_FN,     GPSR0_13,
5231                 GP_0_12_FN,     GPSR0_12,
5232                 GP_0_11_FN,     GPSR0_11,
5233                 GP_0_10_FN,     GPSR0_10,
5234                 GP_0_9_FN,      GPSR0_9,
5235                 GP_0_8_FN,      GPSR0_8,
5236                 GP_0_7_FN,      GPSR0_7,
5237                 GP_0_6_FN,      GPSR0_6,
5238                 GP_0_5_FN,      GPSR0_5,
5239                 GP_0_4_FN,      GPSR0_4,
5240                 GP_0_3_FN,      GPSR0_3,
5241                 GP_0_2_FN,      GPSR0_2,
5242                 GP_0_1_FN,      GPSR0_1,
5243                 GP_0_0_FN,      GPSR0_0, }
5244         },
5245         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5246                 0, 0,
5247                 0, 0,
5248                 0, 0,
5249                 GP_1_28_FN,     GPSR1_28,
5250                 GP_1_27_FN,     GPSR1_27,
5251                 GP_1_26_FN,     GPSR1_26,
5252                 GP_1_25_FN,     GPSR1_25,
5253                 GP_1_24_FN,     GPSR1_24,
5254                 GP_1_23_FN,     GPSR1_23,
5255                 GP_1_22_FN,     GPSR1_22,
5256                 GP_1_21_FN,     GPSR1_21,
5257                 GP_1_20_FN,     GPSR1_20,
5258                 GP_1_19_FN,     GPSR1_19,
5259                 GP_1_18_FN,     GPSR1_18,
5260                 GP_1_17_FN,     GPSR1_17,
5261                 GP_1_16_FN,     GPSR1_16,
5262                 GP_1_15_FN,     GPSR1_15,
5263                 GP_1_14_FN,     GPSR1_14,
5264                 GP_1_13_FN,     GPSR1_13,
5265                 GP_1_12_FN,     GPSR1_12,
5266                 GP_1_11_FN,     GPSR1_11,
5267                 GP_1_10_FN,     GPSR1_10,
5268                 GP_1_9_FN,      GPSR1_9,
5269                 GP_1_8_FN,      GPSR1_8,
5270                 GP_1_7_FN,      GPSR1_7,
5271                 GP_1_6_FN,      GPSR1_6,
5272                 GP_1_5_FN,      GPSR1_5,
5273                 GP_1_4_FN,      GPSR1_4,
5274                 GP_1_3_FN,      GPSR1_3,
5275                 GP_1_2_FN,      GPSR1_2,
5276                 GP_1_1_FN,      GPSR1_1,
5277                 GP_1_0_FN,      GPSR1_0, }
5278         },
5279         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5280                 0, 0,
5281                 0, 0,
5282                 0, 0,
5283                 0, 0,
5284                 0, 0,
5285                 0, 0,
5286                 0, 0,
5287                 0, 0,
5288                 0, 0,
5289                 0, 0,
5290                 0, 0,
5291                 0, 0,
5292                 0, 0,
5293                 0, 0,
5294                 0, 0,
5295                 0, 0,
5296                 0, 0,
5297                 GP_2_14_FN,     GPSR2_14,
5298                 GP_2_13_FN,     GPSR2_13,
5299                 GP_2_12_FN,     GPSR2_12,
5300                 GP_2_11_FN,     GPSR2_11,
5301                 GP_2_10_FN,     GPSR2_10,
5302                 GP_2_9_FN,      GPSR2_9,
5303                 GP_2_8_FN,      GPSR2_8,
5304                 GP_2_7_FN,      GPSR2_7,
5305                 GP_2_6_FN,      GPSR2_6,
5306                 GP_2_5_FN,      GPSR2_5,
5307                 GP_2_4_FN,      GPSR2_4,
5308                 GP_2_3_FN,      GPSR2_3,
5309                 GP_2_2_FN,      GPSR2_2,
5310                 GP_2_1_FN,      GPSR2_1,
5311                 GP_2_0_FN,      GPSR2_0, }
5312         },
5313         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5314                 0, 0,
5315                 0, 0,
5316                 0, 0,
5317                 0, 0,
5318                 0, 0,
5319                 0, 0,
5320                 0, 0,
5321                 0, 0,
5322                 0, 0,
5323                 0, 0,
5324                 0, 0,
5325                 0, 0,
5326                 0, 0,
5327                 0, 0,
5328                 0, 0,
5329                 0, 0,
5330                 GP_3_15_FN,     GPSR3_15,
5331                 GP_3_14_FN,     GPSR3_14,
5332                 GP_3_13_FN,     GPSR3_13,
5333                 GP_3_12_FN,     GPSR3_12,
5334                 GP_3_11_FN,     GPSR3_11,
5335                 GP_3_10_FN,     GPSR3_10,
5336                 GP_3_9_FN,      GPSR3_9,
5337                 GP_3_8_FN,      GPSR3_8,
5338                 GP_3_7_FN,      GPSR3_7,
5339                 GP_3_6_FN,      GPSR3_6,
5340                 GP_3_5_FN,      GPSR3_5,
5341                 GP_3_4_FN,      GPSR3_4,
5342                 GP_3_3_FN,      GPSR3_3,
5343                 GP_3_2_FN,      GPSR3_2,
5344                 GP_3_1_FN,      GPSR3_1,
5345                 GP_3_0_FN,      GPSR3_0, }
5346         },
5347         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5348                 0, 0,
5349                 0, 0,
5350                 0, 0,
5351                 0, 0,
5352                 0, 0,
5353                 0, 0,
5354                 0, 0,
5355                 0, 0,
5356                 0, 0,
5357                 0, 0,
5358                 0, 0,
5359                 0, 0,
5360                 0, 0,
5361                 0, 0,
5362                 GP_4_17_FN,     GPSR4_17,
5363                 GP_4_16_FN,     GPSR4_16,
5364                 GP_4_15_FN,     GPSR4_15,
5365                 GP_4_14_FN,     GPSR4_14,
5366                 GP_4_13_FN,     GPSR4_13,
5367                 GP_4_12_FN,     GPSR4_12,
5368                 GP_4_11_FN,     GPSR4_11,
5369                 GP_4_10_FN,     GPSR4_10,
5370                 GP_4_9_FN,      GPSR4_9,
5371                 GP_4_8_FN,      GPSR4_8,
5372                 GP_4_7_FN,      GPSR4_7,
5373                 GP_4_6_FN,      GPSR4_6,
5374                 GP_4_5_FN,      GPSR4_5,
5375                 GP_4_4_FN,      GPSR4_4,
5376                 GP_4_3_FN,      GPSR4_3,
5377                 GP_4_2_FN,      GPSR4_2,
5378                 GP_4_1_FN,      GPSR4_1,
5379                 GP_4_0_FN,      GPSR4_0, }
5380         },
5381         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5382                 0, 0,
5383                 0, 0,
5384                 0, 0,
5385                 0, 0,
5386                 0, 0,
5387                 0, 0,
5388                 GP_5_25_FN,     GPSR5_25,
5389                 GP_5_24_FN,     GPSR5_24,
5390                 GP_5_23_FN,     GPSR5_23,
5391                 GP_5_22_FN,     GPSR5_22,
5392                 GP_5_21_FN,     GPSR5_21,
5393                 GP_5_20_FN,     GPSR5_20,
5394                 GP_5_19_FN,     GPSR5_19,
5395                 GP_5_18_FN,     GPSR5_18,
5396                 GP_5_17_FN,     GPSR5_17,
5397                 GP_5_16_FN,     GPSR5_16,
5398                 GP_5_15_FN,     GPSR5_15,
5399                 GP_5_14_FN,     GPSR5_14,
5400                 GP_5_13_FN,     GPSR5_13,
5401                 GP_5_12_FN,     GPSR5_12,
5402                 GP_5_11_FN,     GPSR5_11,
5403                 GP_5_10_FN,     GPSR5_10,
5404                 GP_5_9_FN,      GPSR5_9,
5405                 GP_5_8_FN,      GPSR5_8,
5406                 GP_5_7_FN,      GPSR5_7,
5407                 GP_5_6_FN,      GPSR5_6,
5408                 GP_5_5_FN,      GPSR5_5,
5409                 GP_5_4_FN,      GPSR5_4,
5410                 GP_5_3_FN,      GPSR5_3,
5411                 GP_5_2_FN,      GPSR5_2,
5412                 GP_5_1_FN,      GPSR5_1,
5413                 GP_5_0_FN,      GPSR5_0, }
5414         },
5415         { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5416                 GP_6_31_FN,     GPSR6_31,
5417                 GP_6_30_FN,     GPSR6_30,
5418                 GP_6_29_FN,     GPSR6_29,
5419                 GP_6_28_FN,     GPSR6_28,
5420                 GP_6_27_FN,     GPSR6_27,
5421                 GP_6_26_FN,     GPSR6_26,
5422                 GP_6_25_FN,     GPSR6_25,
5423                 GP_6_24_FN,     GPSR6_24,
5424                 GP_6_23_FN,     GPSR6_23,
5425                 GP_6_22_FN,     GPSR6_22,
5426                 GP_6_21_FN,     GPSR6_21,
5427                 GP_6_20_FN,     GPSR6_20,
5428                 GP_6_19_FN,     GPSR6_19,
5429                 GP_6_18_FN,     GPSR6_18,
5430                 GP_6_17_FN,     GPSR6_17,
5431                 GP_6_16_FN,     GPSR6_16,
5432                 GP_6_15_FN,     GPSR6_15,
5433                 GP_6_14_FN,     GPSR6_14,
5434                 GP_6_13_FN,     GPSR6_13,
5435                 GP_6_12_FN,     GPSR6_12,
5436                 GP_6_11_FN,     GPSR6_11,
5437                 GP_6_10_FN,     GPSR6_10,
5438                 GP_6_9_FN,      GPSR6_9,
5439                 GP_6_8_FN,      GPSR6_8,
5440                 GP_6_7_FN,      GPSR6_7,
5441                 GP_6_6_FN,      GPSR6_6,
5442                 GP_6_5_FN,      GPSR6_5,
5443                 GP_6_4_FN,      GPSR6_4,
5444                 GP_6_3_FN,      GPSR6_3,
5445                 GP_6_2_FN,      GPSR6_2,
5446                 GP_6_1_FN,      GPSR6_1,
5447                 GP_6_0_FN,      GPSR6_0, }
5448         },
5449         { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5450                 0, 0,
5451                 0, 0,
5452                 0, 0,
5453                 0, 0,
5454                 0, 0,
5455                 0, 0,
5456                 0, 0,
5457                 0, 0,
5458                 0, 0,
5459                 0, 0,
5460                 0, 0,
5461                 0, 0,
5462                 0, 0,
5463                 0, 0,
5464                 0, 0,
5465                 0, 0,
5466                 0, 0,
5467                 0, 0,
5468                 0, 0,
5469                 0, 0,
5470                 0, 0,
5471                 0, 0,
5472                 0, 0,
5473                 0, 0,
5474                 0, 0,
5475                 0, 0,
5476                 0, 0,
5477                 0, 0,
5478                 GP_7_3_FN, GPSR7_3,
5479                 GP_7_2_FN, GPSR7_2,
5480                 GP_7_1_FN, GPSR7_1,
5481                 GP_7_0_FN, GPSR7_0, }
5482         },
5483 #undef F_
5484 #undef FM
5485
5486 #define F_(x, y)        x,
5487 #define FM(x)           FN_##x,
5488         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5489                 IP0_31_28
5490                 IP0_27_24
5491                 IP0_23_20
5492                 IP0_19_16
5493                 IP0_15_12
5494                 IP0_11_8
5495                 IP0_7_4
5496                 IP0_3_0 }
5497         },
5498         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5499                 IP1_31_28
5500                 IP1_27_24
5501                 IP1_23_20
5502                 IP1_19_16
5503                 IP1_15_12
5504                 IP1_11_8
5505                 IP1_7_4
5506                 IP1_3_0 }
5507         },
5508         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5509                 IP2_31_28
5510                 IP2_27_24
5511                 IP2_23_20
5512                 IP2_19_16
5513                 IP2_15_12
5514                 IP2_11_8
5515                 IP2_7_4
5516                 IP2_3_0 }
5517         },
5518         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5519                 IP3_31_28
5520                 IP3_27_24
5521                 IP3_23_20
5522                 IP3_19_16
5523                 IP3_15_12
5524                 IP3_11_8
5525                 IP3_7_4
5526                 IP3_3_0 }
5527         },
5528         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5529                 IP4_31_28
5530                 IP4_27_24
5531                 IP4_23_20
5532                 IP4_19_16
5533                 IP4_15_12
5534                 IP4_11_8
5535                 IP4_7_4
5536                 IP4_3_0 }
5537         },
5538         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5539                 IP5_31_28
5540                 IP5_27_24
5541                 IP5_23_20
5542                 IP5_19_16
5543                 IP5_15_12
5544                 IP5_11_8
5545                 IP5_7_4
5546                 IP5_3_0 }
5547         },
5548         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5549                 IP6_31_28
5550                 IP6_27_24
5551                 IP6_23_20
5552                 IP6_19_16
5553                 IP6_15_12
5554                 IP6_11_8
5555                 IP6_7_4
5556                 IP6_3_0 }
5557         },
5558         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5559                 IP7_31_28
5560                 IP7_27_24
5561                 IP7_23_20
5562                 IP7_19_16
5563                 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5564                 IP7_11_8
5565                 IP7_7_4
5566                 IP7_3_0 }
5567         },
5568         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5569                 IP8_31_28
5570                 IP8_27_24
5571                 IP8_23_20
5572                 IP8_19_16
5573                 IP8_15_12
5574                 IP8_11_8
5575                 IP8_7_4
5576                 IP8_3_0 }
5577         },
5578         { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5579                 IP9_31_28
5580                 IP9_27_24
5581                 IP9_23_20
5582                 IP9_19_16
5583                 IP9_15_12
5584                 IP9_11_8
5585                 IP9_7_4
5586                 IP9_3_0 }
5587         },
5588         { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5589                 IP10_31_28
5590                 IP10_27_24
5591                 IP10_23_20
5592                 IP10_19_16
5593                 IP10_15_12
5594                 IP10_11_8
5595                 IP10_7_4
5596                 IP10_3_0 }
5597         },
5598         { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5599                 IP11_31_28
5600                 IP11_27_24
5601                 IP11_23_20
5602                 IP11_19_16
5603                 IP11_15_12
5604                 IP11_11_8
5605                 IP11_7_4
5606                 IP11_3_0 }
5607         },
5608         { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5609                 IP12_31_28
5610                 IP12_27_24
5611                 IP12_23_20
5612                 IP12_19_16
5613                 IP12_15_12
5614                 IP12_11_8
5615                 IP12_7_4
5616                 IP12_3_0 }
5617         },
5618         { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5619                 IP13_31_28
5620                 IP13_27_24
5621                 IP13_23_20
5622                 IP13_19_16
5623                 IP13_15_12
5624                 IP13_11_8
5625                 IP13_7_4
5626                 IP13_3_0 }
5627         },
5628         { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5629                 IP14_31_28
5630                 IP14_27_24
5631                 IP14_23_20
5632                 IP14_19_16
5633                 IP14_15_12
5634                 IP14_11_8
5635                 IP14_7_4
5636                 IP14_3_0 }
5637         },
5638         { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5639                 IP15_31_28
5640                 IP15_27_24
5641                 IP15_23_20
5642                 IP15_19_16
5643                 IP15_15_12
5644                 IP15_11_8
5645                 IP15_7_4
5646                 IP15_3_0 }
5647         },
5648         { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5649                 IP16_31_28
5650                 IP16_27_24
5651                 IP16_23_20
5652                 IP16_19_16
5653                 IP16_15_12
5654                 IP16_11_8
5655                 IP16_7_4
5656                 IP16_3_0 }
5657         },
5658         { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5659                 IP17_31_28
5660                 IP17_27_24
5661                 IP17_23_20
5662                 IP17_19_16
5663                 IP17_15_12
5664                 IP17_11_8
5665                 IP17_7_4
5666                 IP17_3_0 }
5667         },
5668         { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5669                 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5670                 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5671                 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5672                 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5673                 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5674                 /* IP18_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5675                 IP18_7_4
5676                 IP18_3_0 }
5677         },
5678 #undef F_
5679 #undef FM
5680
5681 #define F_(x, y)        x,
5682 #define FM(x)           FN_##x,
5683         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5684                              3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5685                              1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5686                 MOD_SEL0_31_30_29
5687                 MOD_SEL0_28_27
5688                 MOD_SEL0_26_25_24
5689                 MOD_SEL0_23
5690                 MOD_SEL0_22
5691                 MOD_SEL0_21
5692                 MOD_SEL0_20
5693                 MOD_SEL0_19
5694                 MOD_SEL0_18_17
5695                 MOD_SEL0_16
5696                 0, 0, /* RESERVED 15 */
5697                 MOD_SEL0_14_13
5698                 MOD_SEL0_12
5699                 MOD_SEL0_11
5700                 MOD_SEL0_10
5701                 MOD_SEL0_9_8
5702                 MOD_SEL0_7_6
5703                 MOD_SEL0_5
5704                 MOD_SEL0_4_3
5705                 /* RESERVED 2, 1, 0 */
5706                 0, 0, 0, 0, 0, 0, 0, 0 }
5707         },
5708         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5709                              2, 3, 1, 2, 3, 1, 1, 2, 1,
5710                              2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5711                 MOD_SEL1_31_30
5712                 MOD_SEL1_29_28_27
5713                 MOD_SEL1_26
5714                 MOD_SEL1_25_24
5715                 MOD_SEL1_23_22_21
5716                 MOD_SEL1_20
5717                 MOD_SEL1_19
5718                 MOD_SEL1_18_17
5719                 MOD_SEL1_16
5720                 MOD_SEL1_15_14
5721                 MOD_SEL1_13
5722                 MOD_SEL1_12
5723                 MOD_SEL1_11
5724                 MOD_SEL1_10
5725                 MOD_SEL1_9
5726                 0, 0, 0, 0, /* RESERVED 8, 7 */
5727                 MOD_SEL1_6
5728                 MOD_SEL1_5
5729                 MOD_SEL1_4
5730                 MOD_SEL1_3
5731                 MOD_SEL1_2
5732                 MOD_SEL1_1
5733                 MOD_SEL1_0 }
5734         },
5735         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5736                              1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5737                              4, 4, 4, 3, 1) {
5738                 MOD_SEL2_31
5739                 MOD_SEL2_30
5740                 MOD_SEL2_29
5741                 MOD_SEL2_28_27
5742                 MOD_SEL2_26
5743                 MOD_SEL2_25_24_23
5744                 MOD_SEL2_22
5745                 MOD_SEL2_21
5746                 MOD_SEL2_20
5747                 MOD_SEL2_19
5748                 MOD_SEL2_18
5749                 MOD_SEL2_17
5750                 /* RESERVED 16 */
5751                 0, 0,
5752                 /* RESERVED 15, 14, 13, 12 */
5753                 0, 0, 0, 0, 0, 0, 0, 0,
5754                 0, 0, 0, 0, 0, 0, 0, 0,
5755                 /* RESERVED 11, 10, 9, 8 */
5756                 0, 0, 0, 0, 0, 0, 0, 0,
5757                 0, 0, 0, 0, 0, 0, 0, 0,
5758                 /* RESERVED 7, 6, 5, 4 */
5759                 0, 0, 0, 0, 0, 0, 0, 0,
5760                 0, 0, 0, 0, 0, 0, 0, 0,
5761                 /* RESERVED 3, 2, 1 */
5762                 0, 0, 0, 0, 0, 0, 0, 0,
5763                 MOD_SEL2_0 }
5764         },
5765         { },
5766 };
5767
5768 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5769         { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5770                 { PIN_NUMBER('W', 3),   28, 2 },        /* QSPI0_SPCLK */
5771                 { PIN_A_NUMBER('C', 5), 24, 2 },        /* QSPI0_MOSI_IO0 */
5772                 { PIN_A_NUMBER('B', 4), 20, 2 },        /* QSPI0_MISO_IO1 */
5773                 { PIN_NUMBER('Y', 6),   16, 2 },        /* QSPI0_IO2 */
5774                 { PIN_A_NUMBER('B', 6), 12, 2 },        /* QSPI0_IO3 */
5775                 { PIN_NUMBER('Y', 3),    8, 2 },        /* QSPI0_SSL */
5776                 { PIN_NUMBER('V', 3),    4, 2 },        /* QSPI1_SPCLK */
5777                 { PIN_A_NUMBER('C', 7),  0, 2 },        /* QSPI1_MOSI_IO0 */
5778         } },
5779         { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5780                 { PIN_A_NUMBER('E', 5), 28, 2 },        /* QSPI1_MISO_IO1 */
5781                 { PIN_A_NUMBER('E', 4), 24, 2 },        /* QSPI1_IO2 */
5782                 { PIN_A_NUMBER('C', 3), 20, 2 },        /* QSPI1_IO3 */
5783                 { PIN_NUMBER('V', 5),   16, 2 },        /* QSPI1_SSL */
5784                 { PIN_NUMBER('Y', 7),   12, 2 },        /* RPC_INT# */
5785                 { PIN_NUMBER('V', 6),    8, 2 },        /* RPC_WP# */
5786                 { PIN_NUMBER('V', 7),    4, 2 },        /* RPC_RESET# */
5787                 { PIN_NUMBER('A', 16),   0, 3 },        /* AVB_RX_CTL */
5788         } },
5789         { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5790                 { PIN_NUMBER('B', 19),  28, 3 },        /* AVB_RXC */
5791                 { PIN_NUMBER('A', 13),  24, 3 },        /* AVB_RD0 */
5792                 { PIN_NUMBER('B', 13),  20, 3 },        /* AVB_RD1 */
5793                 { PIN_NUMBER('A', 14),  16, 3 },        /* AVB_RD2 */
5794                 { PIN_NUMBER('B', 14),  12, 3 },        /* AVB_RD3 */
5795                 { PIN_NUMBER('A', 8),    8, 3 },        /* AVB_TX_CTL */
5796                 { PIN_NUMBER('A', 19),   4, 3 },        /* AVB_TXC */
5797                 { PIN_NUMBER('A', 18),   0, 3 },        /* AVB_TD0 */
5798         } },
5799         { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5800                 { PIN_NUMBER('B', 18),  28, 3 },        /* AVB_TD1 */
5801                 { PIN_NUMBER('A', 17),  24, 3 },        /* AVB_TD2 */
5802                 { PIN_NUMBER('B', 17),  20, 3 },        /* AVB_TD3 */
5803                 { PIN_NUMBER('A', 12),  16, 3 },        /* AVB_TXCREFCLK */
5804                 { PIN_NUMBER('A', 9),   12, 3 },        /* AVB_MDIO */
5805                 { RCAR_GP_PIN(2,  9),    8, 3 },        /* AVB_MDC */
5806                 { RCAR_GP_PIN(2, 10),    4, 3 },        /* AVB_MAGIC */
5807                 { RCAR_GP_PIN(2, 11),    0, 3 },        /* AVB_PHY_INT */
5808         } },
5809         { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5810                 { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5811                 { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5812                 { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5813                 { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5814                 { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5815                 { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5816                 { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5817                 { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5818         } },
5819         { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5820                 { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5821                 { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5822                 { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5823                 { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5824                 { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5825                 { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5826                 { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5827                 { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5828         } },
5829         { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5830                 { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5831                 { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5832                 { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5833                 { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5834                 { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5835                 { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5836                 { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5837                 { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5838         } },
5839         { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5840                 { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5841                 { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5842                 { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5843                 { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5844                 { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5845                 { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5846                 { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5847                 { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5848         } },
5849         { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5850                 { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5851                 { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5852                 { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5853                 { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5854                 { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5855                 { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5856                 { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5857                 { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5858         } },
5859         { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5860                 { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5861                 { PIN_NUMBER('C', 1), 24, 3 },  /* PRESETOUT# */
5862                 { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5863                 { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5864                 { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5865                 { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5866                 { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5867                 { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5868         } },
5869         { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5870                 { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5871                 { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5872                 { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5873                 { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5874                 { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5875                 { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5876                 { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5877                 { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5878         } },
5879         { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5880                 { RCAR_GP_PIN(0, 14),   28, 3 },        /* D14 */
5881                 { RCAR_GP_PIN(0, 15),   24, 3 },        /* D15 */
5882                 { RCAR_GP_PIN(7,  0),   20, 3 },        /* AVS1 */
5883                 { RCAR_GP_PIN(7,  1),   16, 3 },        /* AVS2 */
5884                 { RCAR_GP_PIN(7,  2),   12, 3 },        /* HDMI0_CEC */
5885                 { RCAR_GP_PIN(7,  3),    8, 3 },        /* GP7_03 */
5886                 { PIN_A_NUMBER('P', 7),  4, 2 },        /* DU_DOTCLKIN0 */
5887                 { PIN_A_NUMBER('P', 8),  0, 2 },        /* DU_DOTCLKIN1 */
5888         } },
5889         { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5890                 { PIN_A_NUMBER('R', 8),  28, 2 },       /* DU_DOTCLKIN3 */
5891                 { PIN_A_NUMBER('D', 38), 20, 2 },       /* FSCLKST */
5892                 { PIN_A_NUMBER('R', 30),  4, 2 },       /* TMS */
5893         } },
5894         { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5895                 { PIN_A_NUMBER('T', 28), 28, 2 },       /* TDO */
5896                 { PIN_A_NUMBER('T', 30), 24, 2 },       /* ASEBRK */
5897                 { RCAR_GP_PIN(3,  0),    20, 3 },       /* SD0_CLK */
5898                 { RCAR_GP_PIN(3,  1),    16, 3 },       /* SD0_CMD */
5899                 { RCAR_GP_PIN(3,  2),    12, 3 },       /* SD0_DAT0 */
5900                 { RCAR_GP_PIN(3,  3),     8, 3 },       /* SD0_DAT1 */
5901                 { RCAR_GP_PIN(3,  4),     4, 3 },       /* SD0_DAT2 */
5902                 { RCAR_GP_PIN(3,  5),     0, 3 },       /* SD0_DAT3 */
5903         } },
5904         { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5905                 { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5906                 { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5907                 { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5908                 { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5909                 { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5910                 { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5911                 { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5912                 { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5913         } },
5914         { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5915                 { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5916                 { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5917                 { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5918                 { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5919                 { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5920                 { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5921                 { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5922                 { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5923         } },
5924         { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5925                 { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5926                 { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5927                 { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5928                 { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5929                 { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5930                 { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5931                 { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5932                 { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5933         } },
5934         { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5935                 { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5936                 { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5937                 { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5938                 { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5939                 { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5940                 { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5941                 { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5942                 { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5943         } },
5944         { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5945                 { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5946                 { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5947                 { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5948                 { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5949                 { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5950                 { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5951                 { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5952                 { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5953         } },
5954         { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5955                 { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5956                 { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5957                 { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5958                 { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5959                 { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5960                 { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5961                 { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5962                 { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5963         } },
5964         { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5965                 { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5966                 { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5967                 { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5968                 { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5969                 { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5970                 { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5971                 { PIN_NUMBER('H', 37),  4, 3 }, /* MLB_REF */
5972                 { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5973         } },
5974         { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5975                 { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5976                 { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5977                 { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5978                 { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5979                 { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5980                 { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5981                 { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5982                 { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5983         } },
5984         { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5985                 { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5986                 { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5987                 { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5988                 { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5989                 { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5990                 { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5991                 { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5992                 { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5993         } },
5994         { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5995                 { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5996                 { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5997                 { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5998                 { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5999                 { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
6000                 { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
6001                 { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
6002                 { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
6003         } },
6004         { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6005                 { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
6006                 { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
6007                 { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
6008                 { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
6009                 { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
6010                 { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
6011                 { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
6012         } },
6013         { },
6014 };
6015
6016 enum ioctrl_regs {
6017         POCCTRL,
6018 };
6019
6020 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6021         [POCCTRL] = { 0xe6060380, },
6022         { /* sentinel */ },
6023 };
6024
6025 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6026 {
6027         int bit = -EINVAL;
6028
6029         *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6030
6031         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6032                 bit = pin & 0x1f;
6033
6034         if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6035                 bit = (pin & 0x1f) + 12;
6036
6037         return bit;
6038 }
6039
6040 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6041         { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6042                 [ 0] = PIN_NUMBER('W', 3),      /* QSPI0_SPCLK */
6043                 [ 1] = PIN_A_NUMBER('C', 5),    /* QSPI0_MOSI_IO0 */
6044                 [ 2] = PIN_A_NUMBER('B', 4),    /* QSPI0_MISO_IO1 */
6045                 [ 3] = PIN_NUMBER('Y', 6),      /* QSPI0_IO2 */
6046                 [ 4] = PIN_A_NUMBER('B', 6),    /* QSPI0_IO3 */
6047                 [ 5] = PIN_NUMBER('Y', 3),      /* QSPI0_SSL */
6048                 [ 6] = PIN_NUMBER('V', 3),      /* QSPI1_SPCLK */
6049                 [ 7] = PIN_A_NUMBER('C', 7),    /* QSPI1_MOSI_IO0 */
6050                 [ 8] = PIN_A_NUMBER('E', 5),    /* QSPI1_MISO_IO1 */
6051                 [ 9] = PIN_A_NUMBER('E', 4),    /* QSPI1_IO2 */
6052                 [10] = PIN_A_NUMBER('C', 3),    /* QSPI1_IO3 */
6053                 [11] = PIN_NUMBER('V', 5),      /* QSPI1_SSL */
6054                 [12] = PIN_NUMBER('Y', 7),      /* RPC_INT# */
6055                 [13] = PIN_NUMBER('V', 6),      /* RPC_WP# */
6056                 [14] = PIN_NUMBER('V', 7),      /* RPC_RESET# */
6057                 [15] = PIN_NUMBER('A', 16),     /* AVB_RX_CTL */
6058                 [16] = PIN_NUMBER('B', 19),     /* AVB_RXC */
6059                 [17] = PIN_NUMBER('A', 13),     /* AVB_RD0 */
6060                 [18] = PIN_NUMBER('B', 13),     /* AVB_RD1 */
6061                 [19] = PIN_NUMBER('A', 14),     /* AVB_RD2 */
6062                 [20] = PIN_NUMBER('B', 14),     /* AVB_RD3 */
6063                 [21] = PIN_NUMBER('A', 8),      /* AVB_TX_CTL */
6064                 [22] = PIN_NUMBER('A', 19),     /* AVB_TXC */
6065                 [23] = PIN_NUMBER('A', 18),     /* AVB_TD0 */
6066                 [24] = PIN_NUMBER('B', 18),     /* AVB_TD1 */
6067                 [25] = PIN_NUMBER('A', 17),     /* AVB_TD2 */
6068                 [26] = PIN_NUMBER('B', 17),     /* AVB_TD3 */
6069                 [27] = PIN_NUMBER('A', 12),     /* AVB_TXCREFCLK */
6070                 [28] = PIN_NUMBER('A', 9),      /* AVB_MDIO */
6071                 [29] = RCAR_GP_PIN(2,  9),      /* AVB_MDC */
6072                 [30] = RCAR_GP_PIN(2, 10),      /* AVB_MAGIC */
6073                 [31] = RCAR_GP_PIN(2, 11),      /* AVB_PHY_INT */
6074         } },
6075         { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6076                 [ 0] = RCAR_GP_PIN(2, 12),      /* AVB_LINK */
6077                 [ 1] = RCAR_GP_PIN(2, 13),      /* AVB_AVTP_MATCH_A */
6078                 [ 2] = RCAR_GP_PIN(2, 14),      /* AVB_AVTP_CAPTURE_A */
6079                 [ 3] = RCAR_GP_PIN(2,  0),      /* IRQ0 */
6080                 [ 4] = RCAR_GP_PIN(2,  1),      /* IRQ1 */
6081                 [ 5] = RCAR_GP_PIN(2,  2),      /* IRQ2 */
6082                 [ 6] = RCAR_GP_PIN(2,  3),      /* IRQ3 */
6083                 [ 7] = RCAR_GP_PIN(2,  4),      /* IRQ4 */
6084                 [ 8] = RCAR_GP_PIN(2,  5),      /* IRQ5 */
6085                 [ 9] = RCAR_GP_PIN(2,  6),      /* PWM0 */
6086                 [10] = RCAR_GP_PIN(2,  7),      /* PWM1_A */
6087                 [11] = RCAR_GP_PIN(2,  8),      /* PWM2_A */
6088                 [12] = RCAR_GP_PIN(1,  0),      /* A0 */
6089                 [13] = RCAR_GP_PIN(1,  1),      /* A1 */
6090                 [14] = RCAR_GP_PIN(1,  2),      /* A2 */
6091                 [15] = RCAR_GP_PIN(1,  3),      /* A3 */
6092                 [16] = RCAR_GP_PIN(1,  4),      /* A4 */
6093                 [17] = RCAR_GP_PIN(1,  5),      /* A5 */
6094                 [18] = RCAR_GP_PIN(1,  6),      /* A6 */
6095                 [19] = RCAR_GP_PIN(1,  7),      /* A7 */
6096                 [20] = RCAR_GP_PIN(1,  8),      /* A8 */
6097                 [21] = RCAR_GP_PIN(1,  9),      /* A9 */
6098                 [22] = RCAR_GP_PIN(1, 10),      /* A10 */
6099                 [23] = RCAR_GP_PIN(1, 11),      /* A11 */
6100                 [24] = RCAR_GP_PIN(1, 12),      /* A12 */
6101                 [25] = RCAR_GP_PIN(1, 13),      /* A13 */
6102                 [26] = RCAR_GP_PIN(1, 14),      /* A14 */
6103                 [27] = RCAR_GP_PIN(1, 15),      /* A15 */
6104                 [28] = RCAR_GP_PIN(1, 16),      /* A16 */
6105                 [29] = RCAR_GP_PIN(1, 17),      /* A17 */
6106                 [30] = RCAR_GP_PIN(1, 18),      /* A18 */
6107                 [31] = RCAR_GP_PIN(1, 19),      /* A19 */
6108         } },
6109         { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6110                 [ 0] = RCAR_GP_PIN(1, 28),      /* CLKOUT */
6111                 [ 1] = RCAR_GP_PIN(1, 20),      /* CS0_N */
6112                 [ 2] = RCAR_GP_PIN(1, 21),      /* CS1_N */
6113                 [ 3] = RCAR_GP_PIN(1, 22),      /* BS_N */
6114                 [ 4] = RCAR_GP_PIN(1, 23),      /* RD_N */
6115                 [ 5] = RCAR_GP_PIN(1, 24),      /* RD_WR_N */
6116                 [ 6] = RCAR_GP_PIN(1, 25),      /* WE0_N */
6117                 [ 7] = RCAR_GP_PIN(1, 26),      /* WE1_N */
6118                 [ 8] = RCAR_GP_PIN(1, 27),      /* EX_WAIT0_A */
6119                 [ 9] = PIN_NUMBER('C', 1),      /* PRESETOUT# */
6120                 [10] = RCAR_GP_PIN(0,  0),      /* D0 */
6121                 [11] = RCAR_GP_PIN(0,  1),      /* D1 */
6122                 [12] = RCAR_GP_PIN(0,  2),      /* D2 */
6123                 [13] = RCAR_GP_PIN(0,  3),      /* D3 */
6124                 [14] = RCAR_GP_PIN(0,  4),      /* D4 */
6125                 [15] = RCAR_GP_PIN(0,  5),      /* D5 */
6126                 [16] = RCAR_GP_PIN(0,  6),      /* D6 */
6127                 [17] = RCAR_GP_PIN(0,  7),      /* D7 */
6128                 [18] = RCAR_GP_PIN(0,  8),      /* D8 */
6129                 [19] = RCAR_GP_PIN(0,  9),      /* D9 */
6130                 [20] = RCAR_GP_PIN(0, 10),      /* D10 */
6131                 [21] = RCAR_GP_PIN(0, 11),      /* D11 */
6132                 [22] = RCAR_GP_PIN(0, 12),      /* D12 */
6133                 [23] = RCAR_GP_PIN(0, 13),      /* D13 */
6134                 [24] = RCAR_GP_PIN(0, 14),      /* D14 */
6135                 [25] = RCAR_GP_PIN(0, 15),      /* D15 */
6136                 [26] = RCAR_GP_PIN(7,  0),      /* AVS1 */
6137                 [27] = RCAR_GP_PIN(7,  1),      /* AVS2 */
6138                 [28] = RCAR_GP_PIN(7,  2),      /* HDMI0_CEC */
6139                 [29] = RCAR_GP_PIN(7,  3),      /* GP7_03 */
6140                 [30] = PIN_A_NUMBER('P', 7),    /* DU_DOTCLKIN0 */
6141                 [31] = PIN_A_NUMBER('P', 8),    /* DU_DOTCLKIN1 */
6142         } },
6143         { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6144                 [ 0] = PIN_A_NUMBER('R', 8),    /* DU_DOTCLKIN3 */
6145                 [ 1] = PIN_NONE,
6146                 [ 2] = PIN_A_NUMBER('D', 38),   /* FSCLKST */
6147                 [ 3] = PIN_A_NUMBER('D', 39),   /* EXTALR*/
6148                 [ 4] = PIN_A_NUMBER('R', 26),   /* TRST# */
6149                 [ 5] = PIN_A_NUMBER('T', 27),   /* TCK */
6150                 [ 6] = PIN_A_NUMBER('R', 30),   /* TMS */
6151                 [ 7] = PIN_A_NUMBER('R', 29),   /* TDI */
6152                 [ 8] = PIN_NONE,
6153                 [ 9] = PIN_A_NUMBER('T', 30),   /* ASEBRK */
6154                 [10] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
6155                 [11] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
6156                 [12] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
6157                 [13] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
6158                 [14] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
6159                 [15] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
6160                 [16] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
6161                 [17] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
6162                 [18] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
6163                 [19] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
6164                 [20] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
6165                 [21] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
6166                 [22] = RCAR_GP_PIN(4,  0),      /* SD2_CLK */
6167                 [23] = RCAR_GP_PIN(4,  1),      /* SD2_CMD */
6168                 [24] = RCAR_GP_PIN(4,  2),      /* SD2_DAT0 */
6169                 [25] = RCAR_GP_PIN(4,  3),      /* SD2_DAT1 */
6170                 [26] = RCAR_GP_PIN(4,  4),      /* SD2_DAT2 */
6171                 [27] = RCAR_GP_PIN(4,  5),      /* SD2_DAT3 */
6172                 [28] = RCAR_GP_PIN(4,  6),      /* SD2_DS */
6173                 [29] = RCAR_GP_PIN(4,  7),      /* SD3_CLK */
6174                 [30] = RCAR_GP_PIN(4,  8),      /* SD3_CMD */
6175                 [31] = RCAR_GP_PIN(4,  9),      /* SD3_DAT0 */
6176         } },
6177         { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6178                 [ 0] = RCAR_GP_PIN(4, 10),      /* SD3_DAT1 */
6179                 [ 1] = RCAR_GP_PIN(4, 11),      /* SD3_DAT2 */
6180                 [ 2] = RCAR_GP_PIN(4, 12),      /* SD3_DAT3 */
6181                 [ 3] = RCAR_GP_PIN(4, 13),      /* SD3_DAT4 */
6182                 [ 4] = RCAR_GP_PIN(4, 14),      /* SD3_DAT5 */
6183                 [ 5] = RCAR_GP_PIN(4, 15),      /* SD3_DAT6 */
6184                 [ 6] = RCAR_GP_PIN(4, 16),      /* SD3_DAT7 */
6185                 [ 7] = RCAR_GP_PIN(4, 17),      /* SD3_DS */
6186                 [ 8] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
6187                 [ 9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
6188                 [10] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
6189                 [11] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
6190                 [12] = RCAR_GP_PIN(5,  0),      /* SCK0 */
6191                 [13] = RCAR_GP_PIN(5,  1),      /* RX0 */
6192                 [14] = RCAR_GP_PIN(5,  2),      /* TX0 */
6193                 [15] = RCAR_GP_PIN(5,  3),      /* CTS0_N */
6194                 [16] = RCAR_GP_PIN(5,  4),      /* RTS0_N */
6195                 [17] = RCAR_GP_PIN(5,  5),      /* RX1_A */
6196                 [18] = RCAR_GP_PIN(5,  6),      /* TX1_A */
6197                 [19] = RCAR_GP_PIN(5,  7),      /* CTS1_N */
6198                 [20] = RCAR_GP_PIN(5,  8),      /* RTS1_N */
6199                 [21] = RCAR_GP_PIN(5,  9),      /* SCK2 */
6200                 [22] = RCAR_GP_PIN(5, 10),      /* TX2_A */
6201                 [23] = RCAR_GP_PIN(5, 11),      /* RX2_A */
6202                 [24] = RCAR_GP_PIN(5, 12),      /* HSCK0 */
6203                 [25] = RCAR_GP_PIN(5, 13),      /* HRX0 */
6204                 [26] = RCAR_GP_PIN(5, 14),      /* HTX0 */
6205                 [27] = RCAR_GP_PIN(5, 15),      /* HCTS0_N */
6206                 [28] = RCAR_GP_PIN(5, 16),      /* HRTS0_N */
6207                 [29] = RCAR_GP_PIN(5, 17),      /* MSIOF0_SCK */
6208                 [30] = RCAR_GP_PIN(5, 18),      /* MSIOF0_SYNC */
6209                 [31] = RCAR_GP_PIN(5, 19),      /* MSIOF0_SS1 */
6210         } },
6211         { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6212                 [ 0] = RCAR_GP_PIN(5, 20),      /* MSIOF0_TXD */
6213                 [ 1] = RCAR_GP_PIN(5, 21),      /* MSIOF0_SS2 */
6214                 [ 2] = RCAR_GP_PIN(5, 22),      /* MSIOF0_RXD */
6215                 [ 3] = RCAR_GP_PIN(5, 23),      /* MLB_CLK */
6216                 [ 4] = RCAR_GP_PIN(5, 24),      /* MLB_SIG */
6217                 [ 5] = RCAR_GP_PIN(5, 25),      /* MLB_DAT */
6218                 [ 6] = PIN_NUMBER('H', 37),     /* MLB_REF */
6219                 [ 7] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
6220                 [ 8] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
6221                 [ 9] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
6222                 [10] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1_A */
6223                 [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2_A */
6224                 [12] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
6225                 [13] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
6226                 [14] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
6227                 [15] = RCAR_GP_PIN(6,  8),      /* SSI_SCK4 */
6228                 [16] = RCAR_GP_PIN(6,  9),      /* SSI_WS4 */
6229                 [17] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
6230                 [18] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
6231                 [19] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
6232                 [20] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
6233                 [21] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
6234                 [22] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
6235                 [23] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
6236                 [24] = RCAR_GP_PIN(6, 17),      /* SSI_SCK78 */
6237                 [25] = RCAR_GP_PIN(6, 18),      /* SSI_WS78 */
6238                 [26] = RCAR_GP_PIN(6, 19),      /* SSI_SDATA7 */
6239                 [27] = RCAR_GP_PIN(6, 20),      /* SSI_SDATA8 */
6240                 [28] = RCAR_GP_PIN(6, 21),      /* SSI_SDATA9_A */
6241                 [29] = RCAR_GP_PIN(6, 22),      /* AUDIO_CLKA_A */
6242                 [30] = RCAR_GP_PIN(6, 23),      /* AUDIO_CLKB_B */
6243                 [31] = RCAR_GP_PIN(6, 24),      /* USB0_PWEN */
6244         } },
6245         { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6246                 [ 0] = RCAR_GP_PIN(6, 25),      /* USB0_OVC */
6247                 [ 1] = RCAR_GP_PIN(6, 26),      /* USB1_PWEN */
6248                 [ 2] = RCAR_GP_PIN(6, 27),      /* USB1_OVC */
6249                 [ 3] = RCAR_GP_PIN(6, 28),      /* USB30_PWEN */
6250                 [ 4] = RCAR_GP_PIN(6, 29),      /* USB30_OVC */
6251                 [ 5] = RCAR_GP_PIN(6, 30),      /* GP6_30 */
6252                 [ 6] = RCAR_GP_PIN(6, 31),      /* GP6_31 */
6253                 [ 7] = PIN_NONE,
6254                 [ 8] = PIN_NONE,
6255                 [ 9] = PIN_NONE,
6256                 [10] = PIN_NONE,
6257                 [11] = PIN_NONE,
6258                 [12] = PIN_NONE,
6259                 [13] = PIN_NONE,
6260                 [14] = PIN_NONE,
6261                 [15] = PIN_NONE,
6262                 [16] = PIN_NONE,
6263                 [17] = PIN_NONE,
6264                 [18] = PIN_NONE,
6265                 [19] = PIN_NONE,
6266                 [20] = PIN_NONE,
6267                 [21] = PIN_NONE,
6268                 [22] = PIN_NONE,
6269                 [23] = PIN_NONE,
6270                 [24] = PIN_NONE,
6271                 [25] = PIN_NONE,
6272                 [26] = PIN_NONE,
6273                 [27] = PIN_NONE,
6274                 [28] = PIN_NONE,
6275                 [29] = PIN_NONE,
6276                 [30] = PIN_NONE,
6277                 [31] = PIN_NONE,
6278         } },
6279         { /* sentinel */ },
6280 };
6281
6282 static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
6283                                             unsigned int pin)
6284 {
6285         const struct pinmux_bias_reg *reg;
6286         unsigned int bit;
6287
6288         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6289         if (!reg)
6290                 return PIN_CONFIG_BIAS_DISABLE;
6291
6292         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6293                 return PIN_CONFIG_BIAS_DISABLE;
6294         else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6295                 return PIN_CONFIG_BIAS_PULL_UP;
6296         else
6297                 return PIN_CONFIG_BIAS_PULL_DOWN;
6298 }
6299
6300 static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6301                                    unsigned int bias)
6302 {
6303         const struct pinmux_bias_reg *reg;
6304         u32 enable, updown;
6305         unsigned int bit;
6306
6307         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6308         if (!reg)
6309                 return;
6310
6311         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6312         if (bias != PIN_CONFIG_BIAS_DISABLE)
6313                 enable |= BIT(bit);
6314
6315         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6316         if (bias == PIN_CONFIG_BIAS_PULL_UP)
6317                 updown |= BIT(bit);
6318
6319         sh_pfc_write(pfc, reg->pud, updown);
6320         sh_pfc_write(pfc, reg->puen, enable);
6321 }
6322
6323 static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
6324         .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
6325         .get_bias = r8a77965_pinmux_get_bias,
6326         .set_bias = r8a77965_pinmux_set_bias,
6327 };
6328
6329 const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6330         .name = "r8a77965_pfc",
6331         .ops = &r8a77965_pinmux_ops,
6332         .unlock_reg = 0xe6060000, /* PMMR */
6333
6334         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6335
6336         .pins = pinmux_pins,
6337         .nr_pins = ARRAY_SIZE(pinmux_pins),
6338         .groups = pinmux_groups,
6339         .nr_groups = ARRAY_SIZE(pinmux_groups),
6340         .functions = pinmux_functions,
6341         .nr_functions = ARRAY_SIZE(pinmux_functions),
6342
6343         .cfg_regs = pinmux_config_regs,
6344         .drive_regs = pinmux_drive_regs,
6345         .bias_regs = pinmux_bias_regs,
6346         .ioctrl_regs = pinmux_ioctrl_regs,
6347
6348         .pinmux_data = pinmux_data,
6349         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6350 };