drivers/pinctrl/renesas/pfc-r8a7794.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a7794/r8a7745 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   6  * Copyright (C) 2015 Renesas Solutions Corp.
   7  * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <dm/pinctrl.h>
  14 #include <linux/kernel.h>
  15
  16 #include "sh_pfc.h"
  17
  18 #define CPU_ALL_PORT(fn, sfx)                                           \
  19         PORT_GP_32(0, fn, sfx),                                         \
  20         PORT_GP_26(1, fn, sfx),                                         \
  21         PORT_GP_32(2, fn, sfx),                                         \
  22         PORT_GP_32(3, fn, sfx),                                         \
  23         PORT_GP_32(4, fn, sfx),                                         \
  24         PORT_GP_28(5, fn, sfx),                                         \
  25         PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  26         PORT_GP_1(6, 24, fn, sfx),                                      \
  27         PORT_GP_1(6, 25, fn, sfx)
  28
  29 enum {
  30         PINMUX_RESERVED = 0,
  31
  32         PINMUX_DATA_BEGIN,
  33         GP_ALL(DATA),
  34         PINMUX_DATA_END,
  35
  36         PINMUX_FUNCTION_BEGIN,
  37         GP_ALL(FN),
  38
  39         /* GPSR0 */
  40         FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
  41         FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
  42         FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
  43         FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
  44         FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
  45         FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
  46         FN_IP2_17_16,
  47
  48         /* GPSR1 */
  49         FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
  50         FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
  51         FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
  52         FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
  53         FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
  54
  55         /* GPSR2 */
  56         FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
  57         FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
  58         FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
  59         FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
  60         FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
  61         FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
  62         FN_IP6_5_4, FN_IP6_7_6,
  63
  64         /* GPSR3 */
  65         FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
  66         FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
  67         FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
  68         FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  69         FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
  70         FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
  71         FN_IP8_22_20,
  72
  73         /* GPSR4 */
  74         FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
  75         FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
  76         FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
  77         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  78         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
  79         FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
  80         FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
  81
  82         /* GPSR5 */
  83         FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  84         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
  85         FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
  86         FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
  87         FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
  88         FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
  89
  90         /* GPSR6 */
  91         FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
  92         FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
  93         FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
  94         FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
  95         FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
  96
  97         /* IPSR0 */
  98         FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
  99         FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
 100         FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
 101         FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
 102         FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
 103         FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
 104         FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
 105         FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
 106
 107         /* IPSR1 */
 108         FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
 109         FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
 110         FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
 111         FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
 112         FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
 113         FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
 114         FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
 115         FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
 116         FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
 117         FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
 118         FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
 119         FN_A1, FN_SCIFB1_TXD,
 120         FN_A3, FN_SCIFB0_SCK,
 121         FN_A4, FN_SCIFB0_TXD,
 122         FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
 123         FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
 124
 125         /* IPSR2 */
 126         FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
 127         FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
 128         FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
 129         FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
 130         FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
 131         FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
 132         FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
 133         FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
 134         FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
 135         FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
 136         FN_TPUTO2_B,
 137         FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
 138         FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
 139         FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
 140         FN_A20, FN_SPCLK,
 141
 142         /* IPSR3 */
 143         FN_A21, FN_MOSI_IO0,
 144         FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
 145         FN_A23, FN_IO2, FN_ATAWR1_N,
 146         FN_A24, FN_IO3, FN_EX_WAIT2,
 147         FN_A25, FN_SSL, FN_ATARD1_N,
 148         FN_CS0_N, FN_VI1_DATA8,
 149         FN_CS1_N_A26, FN_VI1_DATA9,
 150         FN_EX_CS0_N, FN_VI1_DATA10,
 151         FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
 152         FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
 153         FN_SCIFB2_TXD,
 154         FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
 155         FN_SCIFB2_SCK,
 156         FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
 157         FN_SCIFB2_CTS_N,
 158         FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
 159         FN_SCIFB2_RTS_N,
 160         FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
 161         FN_RD_N, FN_ATACS11_N,
 162         FN_RD_WR_N, FN_ATAG1_N,
 163
 164         /* IPSR4 */
 165         FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
 166         FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
 167         FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
 168         FN_DU0_DR2, FN_LCDOUT18,
 169         FN_DU0_DR3, FN_LCDOUT19,
 170         FN_DU0_DR4, FN_LCDOUT20,
 171         FN_DU0_DR5, FN_LCDOUT21,
 172         FN_DU0_DR6, FN_LCDOUT22,
 173         FN_DU0_DR7, FN_LCDOUT23,
 174         FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
 175         FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
 176         FN_DU0_DG2, FN_LCDOUT10,
 177         FN_DU0_DG3, FN_LCDOUT11,
 178         FN_DU0_DG4, FN_LCDOUT12,
 179
 180         /* IPSR5 */
 181         FN_DU0_DG5, FN_LCDOUT13,
 182         FN_DU0_DG6, FN_LCDOUT14,
 183         FN_DU0_DG7, FN_LCDOUT15,
 184         FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
 185         FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
 186         FN_DU0_DB2, FN_LCDOUT2,
 187         FN_DU0_DB3, FN_LCDOUT3,
 188         FN_DU0_DB4, FN_LCDOUT4,
 189         FN_DU0_DB5, FN_LCDOUT5,
 190         FN_DU0_DB6, FN_LCDOUT6,
 191         FN_DU0_DB7, FN_LCDOUT7,
 192         FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
 193         FN_DU0_DOTCLKOUT0, FN_QCLK,
 194         FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
 195         FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
 196
 197         /* IPSR6 */
 198         FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
 199         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
 200         FN_DU0_DISP, FN_QPOLA,
 201         FN_DU0_CDE, FN_QPOLB,
 202         FN_VI0_CLK, FN_AVB_RX_CLK,
 203         FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
 204         FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
 205         FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
 206         FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
 207         FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
 208         FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
 209         FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
 210         FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
 211         FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
 212         FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
 213         FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
 214         FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
 215         FN_AVB_TX_EN,
 216         FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
 217         FN_ADIDATA,
 218
 219         /* IPSR7 */
 220         FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
 221         FN_ADICS_SAMP,
 222         FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
 223         FN_ADICLK,
 224         FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
 225         FN_ADICHS0,
 226         FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
 227         FN_ADICHS1,
 228         FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
 229         FN_ADICHS2,
 230         FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
 231         FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
 232         FN_SSI_WS5_B,
 233         FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
 234         FN_SSI_SDATA5_B,
 235         FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
 236         FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
 237         FN_SSI_WS6_B,
 238         FN_DREQ0_N, FN_SCIFB1_RXD,
 239
 240         /* IPSR8 */
 241         FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
 242         FN_SSI_SDATA6_B,
 243         FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
 244         FN_SSI_SCK78_B,
 245         FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
 246         FN_SSI_WS78_B,
 247         FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
 248         FN_AVB_MAGIC, FN_SSI_SDATA7_B,
 249         FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
 250         FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
 251         FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
 252         FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
 253         FN_CAN1_RX_D, FN_TPUTO0_B,
 254         FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
 255         FN_CAN1_TX_D,
 256         FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
 257         FN_TPUTO1_B,
 258         FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
 259         FN_BPFCLK_C,
 260         FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
 261         FN_FMCLK_C,
 262
 263         /* IPSR9 */
 264         FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
 265         FN_FMIN_C,
 266         FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
 267         FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
 268         FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
 269         FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
 270         FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
 271         FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
 272         FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
 273         FN_SPEEDIN_B,
 274         FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
 275         FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
 276         FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
 277
 278         /* IPSR10 */
 279         FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
 280         FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
 281         FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
 282         FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
 283         FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
 284         FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
 285         FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
 286         FN_SSI_SCK4_B,
 287         FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
 288         FN_SSI_WS4_B,
 289         FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
 290         FN_SSI_SDATA4_B,
 291         FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
 292         FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
 293
 294         /* IPSR11 */
 295         FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
 296         FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
 297         FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
 298         FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
 299         FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
 300         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
 301         FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
 302         FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
 303         FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
 304         FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
 305         FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
 306         FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
 307
 308         /* IPSR12 */
 309         FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
 310         FN_DREQ1_N_B,
 311         FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
 312         FN_CAN1_RX_C, FN_DACK1_B,
 313         FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
 314         FN_CAN1_TX_C, FN_DREQ2_N,
 315         FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
 316         FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
 317         FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
 318         FN_DACK2, FN_ETH_MDIO_B,
 319         FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
 320         FN_ETH_CRS_DV_B,
 321         FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
 322         FN_ETH_RX_ER_B,
 323         FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
 324         FN_ETH_RXD0_B,
 325         FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
 326
 327         /* IPSR13 */
 328         FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
 329         FN_ATACS00_N, FN_ETH_LINK_B,
 330         FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
 331         FN_ATACS10_N, FN_ETH_REFCLK_B,
 332         FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
 333         FN_ETH_TXD1_B,
 334         FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
 335         FN_ETH_TX_EN_B,
 336         FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
 337         FN_ATADIR0_N, FN_ETH_MAGIC_B,
 338         FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
 339         FN_TS_SDATA_C, FN_ETH_TXD0_B,
 340         FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
 341         FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
 342         FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
 343         FN_TS_SDEN_C, FN_FMCLK_E,
 344         FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
 345         FN_TS_SPSYNC_C, FN_FMIN_E,
 346
 347         /* MOD_SEL */
 348         FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
 349         FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
 350         FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
 351         FN_SEL_DARC_4,
 352         FN_SEL_ETH_0, FN_SEL_ETH_1,
 353         FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
 354         FN_SEL_I2C00_4,
 355         FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
 356         FN_SEL_I2C01_4,
 357         FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
 358         FN_SEL_I2C02_4,
 359         FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
 360         FN_SEL_I2C03_4,
 361         FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
 362         FN_SEL_I2C04_4,
 363         FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
 364
 365         /* MOD_SEL2 */
 366         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 367         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
 368         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
 369         FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
 370         FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
 371         FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
 372         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 373         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
 374         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
 375         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
 376         FN_SEL_TMU_0, FN_SEL_TMU_1,
 377         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 378         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 379         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 380         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 381
 382         /* MOD_SEL3 */
 383         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 384         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
 385         FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
 386         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 387         FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
 388         FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
 389         FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
 390         FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
 391         FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
 392         FN_SEL_SSI9_1,
 393         PINMUX_FUNCTION_END,
 394
 395         PINMUX_MARK_BEGIN,
 396         A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
 397
 398         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 399
 400         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
 401         SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 402
 403         SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
 404         SD1_DATA2_MARK, SD1_DATA3_MARK,
 405
 406         /* IPSR0 */
 407         SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
 408         MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
 409         SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
 410         SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
 411         MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
 412         CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
 413         CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
 414         SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
 415         SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
 416         SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
 417
 418         /* IPSR1 */
 419         D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
 420         D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
 421         D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
 422         D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
 423         D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
 424         D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
 425         D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
 426         D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
 427         D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
 428         D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
 429         A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
 430         A1_MARK, SCIFB1_TXD_MARK,
 431         A3_MARK, SCIFB0_SCK_MARK,
 432         A4_MARK, SCIFB0_TXD_MARK,
 433         A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
 434         A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
 435
 436         /* IPSR2 */
 437         A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
 438         A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
 439         A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
 440         A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
 441         A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
 442         A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
 443         A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
 444         A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
 445         A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
 446         A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
 447         CAN_CLK_C_MARK, TPUTO2_B_MARK,
 448         A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
 449         A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
 450         A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
 451         A20_MARK, SPCLK_MARK,
 452
 453         /* IPSR3 */
 454         A21_MARK, MOSI_IO0_MARK,
 455         A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
 456         A23_MARK, IO2_MARK, ATAWR1_N_MARK,
 457         A24_MARK, IO3_MARK, EX_WAIT2_MARK,
 458         A25_MARK, SSL_MARK, ATARD1_N_MARK,
 459         CS0_N_MARK, VI1_DATA8_MARK,
 460         CS1_N_A26_MARK, VI1_DATA9_MARK,
 461         EX_CS0_N_MARK, VI1_DATA10_MARK,
 462         EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
 463         EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
 464         TPUTO3_MARK, SCIFB2_TXD_MARK,
 465         EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
 466         BPFCLK_MARK, SCIFB2_SCK_MARK,
 467         EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
 468         FMCLK_MARK, SCIFB2_CTS_N_MARK,
 469         EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
 470         FMIN_MARK, SCIFB2_RTS_N_MARK,
 471         BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
 472         RD_N_MARK, ATACS11_N_MARK,
 473         RD_WR_N_MARK, ATAG1_N_MARK,
 474
 475         /* IPSR4 */
 476         EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
 477         DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
 478         DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
 479         DU0_DR2_MARK, LCDOUT18_MARK,
 480         DU0_DR3_MARK, LCDOUT19_MARK,
 481         DU0_DR4_MARK, LCDOUT20_MARK,
 482         DU0_DR5_MARK, LCDOUT21_MARK,
 483         DU0_DR6_MARK, LCDOUT22_MARK,
 484         DU0_DR7_MARK, LCDOUT23_MARK,
 485         DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
 486         DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
 487         DU0_DG2_MARK, LCDOUT10_MARK,
 488         DU0_DG3_MARK, LCDOUT11_MARK,
 489         DU0_DG4_MARK, LCDOUT12_MARK,
 490
 491         /* IPSR5 */
 492         DU0_DG5_MARK, LCDOUT13_MARK,
 493         DU0_DG6_MARK, LCDOUT14_MARK,
 494         DU0_DG7_MARK, LCDOUT15_MARK,
 495         DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
 496         CAN0_RX_C_MARK,
 497         DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
 498         CAN0_TX_C_MARK,
 499         DU0_DB2_MARK, LCDOUT2_MARK,
 500         DU0_DB3_MARK, LCDOUT3_MARK,
 501         DU0_DB4_MARK, LCDOUT4_MARK,
 502         DU0_DB5_MARK, LCDOUT5_MARK,
 503         DU0_DB6_MARK, LCDOUT6_MARK,
 504         DU0_DB7_MARK, LCDOUT7_MARK,
 505         DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 506         DU0_DOTCLKOUT0_MARK, QCLK_MARK,
 507         DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
 508         DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
 509
 510         /* IPSR6 */
 511         DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
 512         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 513         DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
 514         VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
 515         VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
 516         VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
 517         VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
 518         VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
 519         VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
 520         VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
 521         VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
 522         VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
 523         AVB_RXD7_MARK,
 524         VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
 525         AVB_RX_ER_MARK,
 526         VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
 527         AVB_COL_MARK,
 528         VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
 529         AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
 530         ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
 531         AVB_TX_CLK_MARK, ADIDATA_MARK,
 532
 533         /* IPSR7 */
 534         ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
 535         AVB_TXD0_MARK, ADICS_SAMP_MARK,
 536         ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
 537         AVB_TXD1_MARK, ADICLK_MARK,
 538         ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
 539         AVB_TXD2_MARK, ADICHS0_MARK,
 540         ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
 541         AVB_TXD3_MARK, ADICHS1_MARK,
 542         ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
 543         AVB_TXD4_MARK, ADICHS2_MARK,
 544         ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
 545         SSI_SCK5_B_MARK,
 546         ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
 547         AVB_TXD6_MARK, SSI_WS5_B_MARK,
 548         ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
 549         AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
 550         ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
 551         SSI_SCK6_B_MARK,
 552         ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
 553         AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
 554         DREQ0_N_MARK, SCIFB1_RXD_MARK,
 555
 556         /* IPSR8 */
 557         ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
 558         AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
 559         I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
 560         HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
 561         AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
 562         SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
 563         HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
 564         AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
 565         HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
 566         I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
 567         AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
 568         SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
 569         CAN1_TX_D_MARK,
 570         I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
 571         TS_SDATA_D_MARK, TPUTO1_B_MARK,
 572         I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
 573         BPFCLK_C_MARK,
 574         MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
 575         TS_SDEN_D_MARK, FMCLK_C_MARK,
 576
 577         /* IPSR9 */
 578         MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
 579         TS_SPSYNC_D_MARK, FMIN_C_MARK,
 580         MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
 581         MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
 582         MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
 583         FMCLK_B_MARK,
 584         MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
 585         FMIN_B_MARK,
 586         HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
 587         HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
 588         HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
 589         SPEEDIN_B_MARK,
 590         HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
 591         SSI_SCK1_B_MARK,
 592         HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
 593         SSI_WS1_B_MARK,
 594         SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
 595         CAN_TXCLK_MARK,
 596
 597         /* IPSR10 */
 598         SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
 599         SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
 600         SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
 601         SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
 602         SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
 603         SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
 604         SSI_SDATA9_B_MARK,
 605         SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
 606         AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
 607         SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
 608         AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
 609         I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
 610         SSI_SDATA4_B_MARK,
 611         I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
 612         SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
 613
 614         /* IPSR11 */
 615         SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
 616         SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
 617         SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 618         SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
 619         DU1_EXVSYNC_DU1_VSYNC_MARK,
 620         SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
 621         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 622         SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
 623         SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
 624         SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
 625         CAN_CLK_D_MARK,
 626         SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
 627         SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
 628         SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
 629
 630         /* IPSR12 */
 631         SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
 632         DREQ1_N_B_MARK,
 633         SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
 634         CAN1_RX_C_MARK, DACK1_B_MARK,
 635         SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
 636         CAN1_TX_C_MARK, DREQ2_N_MARK,
 637         SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
 638         SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
 639         SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
 640         SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
 641         DACK2_MARK, ETH_MDIO_B_MARK,
 642         SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
 643         CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
 644         SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
 645         CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
 646         SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
 647         ETH_RXD0_B_MARK,
 648         SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
 649         ETH_RXD1_B_MARK,
 650
 651         /* IPSR13 */
 652         SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
 653         ATACS00_N_MARK, ETH_LINK_B_MARK,
 654         SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
 655         VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
 656         SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
 657         EX_WAIT1_MARK, ETH_TXD1_B_MARK,
 658         SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
 659         ATARD0_N_MARK, ETH_TX_EN_B_MARK,
 660         SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
 661         ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
 662         AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
 663         TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
 664         AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
 665         TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
 666         AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
 667         TS_SDEN_C_MARK, FMCLK_E_MARK,
 668         AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
 669         TS_SPSYNC_C_MARK, FMIN_E_MARK,
 670         PINMUX_MARK_END,
 671 };
 672
 673 static const u16 pinmux_data[] = {
 674         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 675
 676         PINMUX_SINGLE(A2),
 677         PINMUX_SINGLE(WE0_N),
 678         PINMUX_SINGLE(WE1_N),
 679         PINMUX_SINGLE(DACK0),
 680         PINMUX_SINGLE(USB0_PWEN),
 681         PINMUX_SINGLE(USB0_OVC),
 682         PINMUX_SINGLE(USB1_PWEN),
 683         PINMUX_SINGLE(USB1_OVC),
 684         PINMUX_SINGLE(SD0_CLK),
 685         PINMUX_SINGLE(SD0_CMD),
 686         PINMUX_SINGLE(SD0_DATA0),
 687         PINMUX_SINGLE(SD0_DATA1),
 688         PINMUX_SINGLE(SD0_DATA2),
 689         PINMUX_SINGLE(SD0_DATA3),
 690         PINMUX_SINGLE(SD0_CD),
 691         PINMUX_SINGLE(SD0_WP),
 692         PINMUX_SINGLE(SD1_CLK),
 693         PINMUX_SINGLE(SD1_CMD),
 694         PINMUX_SINGLE(SD1_DATA0),
 695         PINMUX_SINGLE(SD1_DATA1),
 696         PINMUX_SINGLE(SD1_DATA2),
 697         PINMUX_SINGLE(SD1_DATA3),
 698
 699         /* IPSR0 */
 700         PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
 701         PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
 702         PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
 703         PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
 704         PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
 705         PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
 706         PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
 707         PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
 708         PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
 709         PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
 710         PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
 711         PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
 712         PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
 713         PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
 714         PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
 715         PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
 716         PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
 717         PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
 718         PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
 719         PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
 720         PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
 721         PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
 722         PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
 723         PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
 724         PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
 725         PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
 726         PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
 727         PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
 728         PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
 729         PINMUX_IPSR_GPSR(IP0_23_22, D0),
 730         PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
 731         PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
 732         PINMUX_IPSR_GPSR(IP0_24, D1),
 733         PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
 734         PINMUX_IPSR_GPSR(IP0_25, D2),
 735         PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
 736         PINMUX_IPSR_GPSR(IP0_27_26, D3),
 737         PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
 738         PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
 739         PINMUX_IPSR_GPSR(IP0_29_28, D4),
 740         PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
 741         PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
 742         PINMUX_IPSR_GPSR(IP0_31_30, D5),
 743         PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
 744         PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
 745
 746         /* IPSR1 */
 747         PINMUX_IPSR_GPSR(IP1_1_0, D6),
 748         PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
 749         PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
 750         PINMUX_IPSR_GPSR(IP1_3_2, D7),
 751         PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
 752         PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
 753         PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
 754         PINMUX_IPSR_GPSR(IP1_5_4, D8),
 755         PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
 756         PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
 757         PINMUX_IPSR_GPSR(IP1_7_6, D9),
 758         PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
 759         PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
 760         PINMUX_IPSR_GPSR(IP1_10_8, D10),
 761         PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
 762         PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
 763         PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
 764         PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
 765         PINMUX_IPSR_GPSR(IP1_12_11, D11),
 766         PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
 767         PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
 768         PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
 769         PINMUX_IPSR_GPSR(IP1_14_13, D12),
 770         PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
 771         PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
 772         PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
 773         PINMUX_IPSR_GPSR(IP1_17_15, D13),
 774         PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
 775         PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
 776         PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
 777         PINMUX_IPSR_GPSR(IP1_19_18, D14),
 778         PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
 779         PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
 780         PINMUX_IPSR_GPSR(IP1_21_20, D15),
 781         PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
 782         PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
 783         PINMUX_IPSR_GPSR(IP1_23_22, A0),
 784         PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
 785         PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
 786         PINMUX_IPSR_GPSR(IP1_24, A1),
 787         PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
 788         PINMUX_IPSR_GPSR(IP1_26, A3),
 789         PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
 790         PINMUX_IPSR_GPSR(IP1_27, A4),
 791         PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
 792         PINMUX_IPSR_GPSR(IP1_29_28, A5),
 793         PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
 794         PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
 795         PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
 796         PINMUX_IPSR_GPSR(IP1_31_30, A6),
 797         PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
 798         PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
 799         PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
 800
 801         /* IPSR2 */
 802         PINMUX_IPSR_GPSR(IP2_1_0, A7),
 803         PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
 804         PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
 805         PINMUX_IPSR_GPSR(IP2_3_2, A8),
 806         PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
 807         PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
 808         PINMUX_IPSR_GPSR(IP2_5_4, A9),
 809         PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
 810         PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
 811         PINMUX_IPSR_GPSR(IP2_7_6, A10),
 812         PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
 813         PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
 814         PINMUX_IPSR_GPSR(IP2_9_8, A11),
 815         PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
 816         PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
 817         PINMUX_IPSR_GPSR(IP2_11_10, A12),
 818         PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
 819         PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
 820         PINMUX_IPSR_GPSR(IP2_13_12, A13),
 821         PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
 822         PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
 823         PINMUX_IPSR_GPSR(IP2_15_14, A14),
 824         PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
 825         PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
 826         PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
 827         PINMUX_IPSR_GPSR(IP2_17_16, A15),
 828         PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
 829         PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
 830         PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
 831         PINMUX_IPSR_GPSR(IP2_20_18, A16),
 832         PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
 833         PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
 834         PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
 835         PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
 836         PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
 837         PINMUX_IPSR_GPSR(IP2_23_21, A17),
 838         PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
 839         PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
 840         PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
 841         PINMUX_IPSR_GPSR(IP2_26_24, A18),
 842         PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
 843         PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
 844         PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
 845         PINMUX_IPSR_GPSR(IP2_29_27, A19),
 846         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
 847         PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
 848         PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
 849         PINMUX_IPSR_GPSR(IP2_31_30, A20),
 850         PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
 851
 852         /* IPSR3 */
 853         PINMUX_IPSR_GPSR(IP3_1_0, A21),
 854         PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
 855         PINMUX_IPSR_GPSR(IP3_3_2, A22),
 856         PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
 857         PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
 858         PINMUX_IPSR_GPSR(IP3_5_4, A23),
 859         PINMUX_IPSR_GPSR(IP3_5_4, IO2),
 860         PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
 861         PINMUX_IPSR_GPSR(IP3_7_6, A24),
 862         PINMUX_IPSR_GPSR(IP3_7_6, IO3),
 863         PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
 864         PINMUX_IPSR_GPSR(IP3_9_8, A25),
 865         PINMUX_IPSR_GPSR(IP3_9_8, SSL),
 866         PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
 867         PINMUX_IPSR_GPSR(IP3_10, CS0_N),
 868         PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
 869         PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
 870         PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
 871         PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
 872         PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
 873         PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
 874         PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
 875         PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
 876         PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
 877         PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
 878         PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
 879         PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
 880         PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
 881         PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
 882         PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
 883         PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
 884         PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
 885         PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
 886         PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
 887         PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
 888         PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
 889         PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
 890         PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
 891         PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
 892         PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
 893         PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
 894         PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
 895         PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
 896         PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
 897         PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
 898         PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
 899         PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
 900         PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
 901         PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
 902         PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
 903         PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
 904         PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
 905         PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
 906         PINMUX_IPSR_GPSR(IP3_30, RD_N),
 907         PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
 908         PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
 909         PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
 910
 911         /* IPSR4 */
 912         PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
 913         PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
 914         PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
 915         PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
 916         PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
 917         PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
 918         PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
 919         PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
 920         PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
 921         PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
 922         PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
 923         PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
 924         PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
 925         PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
 926         PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
 927         PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
 928         PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
 929         PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
 930         PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
 931         PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
 932         PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
 933         PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
 934         PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
 935         PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
 936         PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
 937         PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
 938         PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
 939         PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
 940         PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
 941         PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
 942         PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
 943         PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
 944         PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
 945         PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
 946         PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
 947         PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
 948         PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
 949
 950         /* IPSR5 */
 951         PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
 952         PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
 953         PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
 954         PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
 955         PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
 956         PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
 957         PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
 958         PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
 959         PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
 960         PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
 961         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
 962         PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
 963         PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
 964         PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
 965         PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
 966         PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
 967         PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
 968         PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
 969         PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
 970         PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
 971         PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
 972         PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
 973         PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
 974         PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
 975         PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
 976         PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
 977         PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
 978         PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
 979         PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
 980         PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
 981         PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
 982         PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
 983         PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
 984         PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
 985         PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
 986         PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
 987
 988         /* IPSR6 */
 989         PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
 990         PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
 991         PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 992         PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
 993         PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
 994         PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
 995         PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
 996         PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
 997         PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
 998         PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
 999         PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
1000         PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
1001         PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
1002         PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
1003         PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
1004         PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
1005         PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
1006         PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
1007         PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
1008         PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
1009         PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
1010         PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
1011         PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
1012         PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
1013         PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
1014         PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
1015         PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
1016         PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
1017         PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
1018         PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
1019         PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
1020         PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
1021         PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1022         PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1023         PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1024         PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
1025         PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
1026         PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1027         PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1028         PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1029         PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
1030         PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
1031         PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1032         PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1033         PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1034         PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
1035         PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1036         PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
1037         PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1038         PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
1039         PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
1040         PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1041
1042         /* IPSR7 */
1043         PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1044         PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
1045         PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1046         PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
1047         PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
1048         PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1049         PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1050         PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
1051         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1052         PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1053         PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
1054         PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1055         PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1056         PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
1057         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1058         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1059         PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
1060         PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1061         PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1062         PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
1063         PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1064         PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1065         PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
1066         PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1067         PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1068         PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
1069         PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1070         PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1071         PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
1072         PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1073         PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1074         PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
1075         PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1076         PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
1077         PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1078         PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1079         PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
1080         PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1081         PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
1082         PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
1083         PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1084         PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1085         PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
1086         PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1087         PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
1088         PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
1089         PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1090         PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1091         PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
1092         PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1093         PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
1094         PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1095         PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1096         PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
1097         PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1098         PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1099         PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
1100         PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1101         PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
1102         PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
1103
1104         /* IPSR8 */
1105         PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1106         PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
1107         PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1108         PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1109         PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
1110         PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1111         PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1112         PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
1113         PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1114         PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1115         PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
1116         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1117         PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1118         PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
1119         PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1120         PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1121         PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
1122         PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1123         PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
1124         PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
1125         PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1126         PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1127         PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
1128         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1129         PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
1130         PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
1131         PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1132         PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1133         PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
1134         PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1135         PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1136         PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1137         PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
1138         PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1139         PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1140         PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1141         PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
1142         PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1143         PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
1144         PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1145         PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
1146         PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1147         PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1148         PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
1149         PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1150         PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
1151         PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1152         PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1153         PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1154         PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
1155         PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
1156         PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1157         PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
1158         PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1159         PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1160         PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
1161         PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
1162         PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1163         PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1164         PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
1165         PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1166         PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1167         PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
1168         PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1169         PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1170
1171         /* IPSR9 */
1172         PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
1173         PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1174         PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1175         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
1176         PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1177         PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1178         PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
1179         PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
1180         PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1181         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
1182         PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
1183         PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
1184         PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
1185         PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1186         PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
1187         PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1188         PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
1189         PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1190         PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1191         PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
1192         PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1193         PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
1194         PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1195         PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1196         PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
1197         PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1198         PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1199         PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1200         PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
1201         PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
1202         PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1203         PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1204         PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
1205         PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
1206         PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
1207         PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
1208         PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1209         PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
1210         PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1211         PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1212         PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1213         PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1214         PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1215         PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
1216         PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1217         PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1218         PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1219         PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1220         PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
1221         PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1222         PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1223         PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
1224         PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1225         PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
1226         PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1227
1228         /* IPSR10 */
1229         PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1230         PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
1231         PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
1232         PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1233         PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1234         PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
1235         PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
1236         PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1237         PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1238         PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
1239         PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
1240         PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1241         PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1242         PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
1243         PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
1244         PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1245         PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1246         PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
1247         PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
1248         PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1249         PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1250         PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
1251         PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1252         PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
1253         PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1254         PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1255         PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1256         PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1257         PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
1258         PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1259         PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1260         PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1261         PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1262         PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1263         PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
1264         PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1265         PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1266         PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1267         PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1268         PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
1269         PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1270         PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1271         PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1272         PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1273         PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
1274         PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1275         PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1276         PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1277         PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
1278
1279         /* IPSR11 */
1280         PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1281         PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1282         PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1283         PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
1284         PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1285         PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1286         PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1287         PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
1288         PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1289         PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1290         PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1291         PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1292         PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1293         PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1294         PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1295         PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1296         PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1297         PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1298         PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1299         PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1300         PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1301         PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
1302         PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
1303         PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1304         PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1305         PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
1306         PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
1307         PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1308         PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1309         PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
1310         PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1311         PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1312         PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
1313         PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1314         PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1315         PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1316         PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
1317         PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1318         PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1319         PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1320         PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
1321         PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1322         PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
1323         PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1324
1325         /* IPSR12 */
1326         PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
1327         PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1328         PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1329         PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1330         PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1331         PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
1332         PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1333         PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1334         PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1335         PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1336         PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1337         PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
1338         PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1339         PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1340         PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1341         PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1342         PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
1343         PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1344         PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
1345         PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1346         PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1347         PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
1348         PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1349         PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1350         PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
1351         PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1352         PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1353         PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1354         PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
1355         PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
1356         PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1357         PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
1358         PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1359         PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1360         PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1361         PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
1362         PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
1363         PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1364         PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1365         PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1366         PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1367         PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
1368         PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
1369         PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1370         PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1371         PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1372         PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1373         PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
1374         PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
1375         PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1376         PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1377         PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1378         PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
1379         PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
1380         PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1381
1382         /* IPSR13 */
1383         PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1384         PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1385         PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1386         PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
1387         PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
1388         PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1389         PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1390         PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1391         PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1392         PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
1393         PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
1394         PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1395         PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1396         PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1397         PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
1398         PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
1399         PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
1400         PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1401         PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1402         PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1403         PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1404         PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
1405         PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
1406         PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1407         PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1408         PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1409         PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1410         PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
1411         PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
1412         PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1413         PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1414         PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1415         PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1416         PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
1417         PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1418         PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1419         PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1420         PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1421         PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1422         PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
1423         PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1424         PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1425         PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1426         PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1427         PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1428         PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1429         PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
1430         PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1431         PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1432         PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1433         PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1434         PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1435         PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
1436         PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1437         PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1438 };
1439
1440 static const struct sh_pfc_pin pinmux_pins[] = {
1441         PINMUX_GPIO_GP_ALL(),
1442 };
1443
1444 /* - Audio Clock ------------------------------------------------------------ */
1445 static const unsigned int audio_clka_pins[] = {
1446         /* CLKA */
1447         RCAR_GP_PIN(5, 20),
1448 };
1449 static const unsigned int audio_clka_mux[] = {
1450         AUDIO_CLKA_MARK,
1451 };
1452 static const unsigned int audio_clka_b_pins[] = {
1453         /* CLKA */
1454         RCAR_GP_PIN(3, 25),
1455 };
1456 static const unsigned int audio_clka_b_mux[] = {
1457         AUDIO_CLKA_B_MARK,
1458 };
1459 static const unsigned int audio_clka_c_pins[] = {
1460         /* CLKA */
1461         RCAR_GP_PIN(4, 20),
1462 };
1463 static const unsigned int audio_clka_c_mux[] = {
1464         AUDIO_CLKA_C_MARK,
1465 };
1466 static const unsigned int audio_clka_d_pins[] = {
1467         /* CLKA */
1468         RCAR_GP_PIN(5, 0),
1469 };
1470 static const unsigned int audio_clka_d_mux[] = {
1471         AUDIO_CLKA_D_MARK,
1472 };
1473 static const unsigned int audio_clkb_pins[] = {
1474         /* CLKB */
1475         RCAR_GP_PIN(5, 21),
1476 };
1477 static const unsigned int audio_clkb_mux[] = {
1478         AUDIO_CLKB_MARK,
1479 };
1480 static const unsigned int audio_clkb_b_pins[] = {
1481         /* CLKB */
1482         RCAR_GP_PIN(3, 26),
1483 };
1484 static const unsigned int audio_clkb_b_mux[] = {
1485         AUDIO_CLKB_B_MARK,
1486 };
1487 static const unsigned int audio_clkb_c_pins[] = {
1488         /* CLKB */
1489         RCAR_GP_PIN(4, 21),
1490 };
1491 static const unsigned int audio_clkb_c_mux[] = {
1492         AUDIO_CLKB_C_MARK,
1493 };
1494 static const unsigned int audio_clkc_pins[] = {
1495         /* CLKC */
1496         RCAR_GP_PIN(5, 22),
1497 };
1498 static const unsigned int audio_clkc_mux[] = {
1499         AUDIO_CLKC_MARK,
1500 };
1501 static const unsigned int audio_clkc_b_pins[] = {
1502         /* CLKC */
1503         RCAR_GP_PIN(3, 29),
1504 };
1505 static const unsigned int audio_clkc_b_mux[] = {
1506         AUDIO_CLKC_B_MARK,
1507 };
1508 static const unsigned int audio_clkc_c_pins[] = {
1509         /* CLKC */
1510         RCAR_GP_PIN(4, 22),
1511 };
1512 static const unsigned int audio_clkc_c_mux[] = {
1513         AUDIO_CLKC_C_MARK,
1514 };
1515 static const unsigned int audio_clkout_pins[] = {
1516         /* CLKOUT */
1517         RCAR_GP_PIN(5, 23),
1518 };
1519 static const unsigned int audio_clkout_mux[] = {
1520         AUDIO_CLKOUT_MARK,
1521 };
1522 static const unsigned int audio_clkout_b_pins[] = {
1523         /* CLKOUT */
1524         RCAR_GP_PIN(3, 12),
1525 };
1526 static const unsigned int audio_clkout_b_mux[] = {
1527         AUDIO_CLKOUT_B_MARK,
1528 };
1529 static const unsigned int audio_clkout_c_pins[] = {
1530         /* CLKOUT */
1531         RCAR_GP_PIN(4, 23),
1532 };
1533 static const unsigned int audio_clkout_c_mux[] = {
1534         AUDIO_CLKOUT_C_MARK,
1535 };
1536 /* - AVB -------------------------------------------------------------------- */
1537 static const unsigned int avb_link_pins[] = {
1538         RCAR_GP_PIN(3, 26),
1539 };
1540 static const unsigned int avb_link_mux[] = {
1541         AVB_LINK_MARK,
1542 };
1543 static const unsigned int avb_magic_pins[] = {
1544         RCAR_GP_PIN(3, 27),
1545 };
1546 static const unsigned int avb_magic_mux[] = {
1547         AVB_MAGIC_MARK,
1548 };
1549 static const unsigned int avb_phy_int_pins[] = {
1550         RCAR_GP_PIN(3, 28),
1551 };
1552 static const unsigned int avb_phy_int_mux[] = {
1553         AVB_PHY_INT_MARK,
1554 };
1555 static const unsigned int avb_mdio_pins[] = {
1556         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
1557 };
1558 static const unsigned int avb_mdio_mux[] = {
1559         AVB_MDC_MARK, AVB_MDIO_MARK,
1560 };
1561 static const unsigned int avb_mii_pins[] = {
1562         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1563         RCAR_GP_PIN(3, 17),
1564
1565         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1566         RCAR_GP_PIN(3, 5),
1567
1568         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1569         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
1570         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
1571 };
1572 static const unsigned int avb_mii_mux[] = {
1573         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1574         AVB_TXD3_MARK,
1575
1576         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1577         AVB_RXD3_MARK,
1578
1579         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1580         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1581         AVB_TX_CLK_MARK, AVB_COL_MARK,
1582 };
1583 static const unsigned int avb_gmii_pins[] = {
1584         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1585         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1586         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1587
1588         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1589         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1590         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1591
1592         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1593         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
1594         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
1595         RCAR_GP_PIN(3, 11),
1596 };
1597 static const unsigned int avb_gmii_mux[] = {
1598         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1599         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1600         AVB_TXD6_MARK, AVB_TXD7_MARK,
1601
1602         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1603         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1604         AVB_RXD6_MARK, AVB_RXD7_MARK,
1605
1606         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1607         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1608         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1609         AVB_COL_MARK,
1610 };
1611
1612 /* - CAN -------------------------------------------------------------------- */
1613 static const unsigned int can0_data_pins[] = {
1614         /* TX, RX */
1615         RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1616 };
1617
1618 static const unsigned int can0_data_mux[] = {
1619         CAN0_TX_MARK, CAN0_RX_MARK,
1620 };
1621
1622 static const unsigned int can0_data_b_pins[] = {
1623         /* TX, RX */
1624         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1625 };
1626
1627 static const unsigned int can0_data_b_mux[] = {
1628         CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1629 };
1630
1631 static const unsigned int can0_data_c_pins[] = {
1632         /* TX, RX */
1633         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1634 };
1635
1636 static const unsigned int can0_data_c_mux[] = {
1637         CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1638 };
1639
1640 static const unsigned int can0_data_d_pins[] = {
1641         /* TX, RX */
1642         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1643 };
1644
1645 static const unsigned int can0_data_d_mux[] = {
1646         CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1647 };
1648
1649 static const unsigned int can1_data_pins[] = {
1650         /* TX, RX */
1651         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
1652 };
1653
1654 static const unsigned int can1_data_mux[] = {
1655         CAN1_TX_MARK, CAN1_RX_MARK,
1656 };
1657
1658 static const unsigned int can1_data_b_pins[] = {
1659         /* TX, RX */
1660         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1661 };
1662
1663 static const unsigned int can1_data_b_mux[] = {
1664         CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1665 };
1666
1667 static const unsigned int can1_data_c_pins[] = {
1668         /* TX, RX */
1669         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1670 };
1671
1672 static const unsigned int can1_data_c_mux[] = {
1673         CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1674 };
1675
1676 static const unsigned int can1_data_d_pins[] = {
1677         /* TX, RX */
1678         RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1679 };
1680
1681 static const unsigned int can1_data_d_mux[] = {
1682         CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1683 };
1684
1685 static const unsigned int can_clk_pins[] = {
1686         /* CLK */
1687         RCAR_GP_PIN(3, 31),
1688 };
1689
1690 static const unsigned int can_clk_mux[] = {
1691         CAN_CLK_MARK,
1692 };
1693
1694 static const unsigned int can_clk_b_pins[] = {
1695         /* CLK */
1696         RCAR_GP_PIN(1, 23),
1697 };
1698
1699 static const unsigned int can_clk_b_mux[] = {
1700         CAN_CLK_B_MARK,
1701 };
1702
1703 static const unsigned int can_clk_c_pins[] = {
1704         /* CLK */
1705         RCAR_GP_PIN(1, 0),
1706 };
1707
1708 static const unsigned int can_clk_c_mux[] = {
1709         CAN_CLK_C_MARK,
1710 };
1711
1712 static const unsigned int can_clk_d_pins[] = {
1713         /* CLK */
1714         RCAR_GP_PIN(5, 0),
1715 };
1716
1717 static const unsigned int can_clk_d_mux[] = {
1718         CAN_CLK_D_MARK,
1719 };
1720
1721 /* - DU --------------------------------------------------------------------- */
1722 static const unsigned int du0_rgb666_pins[] = {
1723         /* R[7:2], G[7:2], B[7:2] */
1724         RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1725         RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1726         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1727         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1728         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1729         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1730 };
1731 static const unsigned int du0_rgb666_mux[] = {
1732         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1733         DU0_DR3_MARK, DU0_DR2_MARK,
1734         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1735         DU0_DG3_MARK, DU0_DG2_MARK,
1736         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1737         DU0_DB3_MARK, DU0_DB2_MARK,
1738 };
1739 static const unsigned int du0_rgb888_pins[] = {
1740         /* R[7:0], G[7:0], B[7:0] */
1741         RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1742         RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1743         RCAR_GP_PIN(2, 1),  RCAR_GP_PIN(2, 0),
1744         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1745         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1746         RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 8),
1747         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1748         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1749         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1750 };
1751 static const unsigned int du0_rgb888_mux[] = {
1752         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1753         DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1754         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1755         DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1756         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1757         DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1758 };
1759 static const unsigned int du0_clk0_out_pins[] = {
1760         /* DOTCLKOUT0 */
1761         RCAR_GP_PIN(2, 25),
1762 };
1763 static const unsigned int du0_clk0_out_mux[] = {
1764         DU0_DOTCLKOUT0_MARK
1765 };
1766 static const unsigned int du0_clk1_out_pins[] = {
1767         /* DOTCLKOUT1 */
1768         RCAR_GP_PIN(2, 26),
1769 };
1770 static const unsigned int du0_clk1_out_mux[] = {
1771         DU0_DOTCLKOUT1_MARK
1772 };
1773 static const unsigned int du0_clk_in_pins[] = {
1774         /* CLKIN */
1775         RCAR_GP_PIN(2, 24),
1776 };
1777 static const unsigned int du0_clk_in_mux[] = {
1778         DU0_DOTCLKIN_MARK
1779 };
1780 static const unsigned int du0_sync_pins[] = {
1781         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1782         RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
1783 };
1784 static const unsigned int du0_sync_mux[] = {
1785         DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
1786 };
1787 static const unsigned int du0_oddf_pins[] = {
1788         /* EXODDF/ODDF/DISP/CDE */
1789         RCAR_GP_PIN(2, 29),
1790 };
1791 static const unsigned int du0_oddf_mux[] = {
1792         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
1793 };
1794 static const unsigned int du0_cde_pins[] = {
1795         /* CDE */
1796         RCAR_GP_PIN(2, 31),
1797 };
1798 static const unsigned int du0_cde_mux[] = {
1799         DU0_CDE_MARK,
1800 };
1801 static const unsigned int du0_disp_pins[] = {
1802         /* DISP */
1803         RCAR_GP_PIN(2, 30),
1804 };
1805 static const unsigned int du0_disp_mux[] = {
1806         DU0_DISP_MARK
1807 };
1808 static const unsigned int du1_rgb666_pins[] = {
1809         /* R[7:2], G[7:2], B[7:2] */
1810         RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
1811         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1812         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1813         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1814         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1815         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1816 };
1817 static const unsigned int du1_rgb666_mux[] = {
1818         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1819         DU1_DR3_MARK, DU1_DR2_MARK,
1820         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1821         DU1_DG3_MARK, DU1_DG2_MARK,
1822         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1823         DU1_DB3_MARK, DU1_DB2_MARK,
1824 };
1825 static const unsigned int du1_rgb888_pins[] = {
1826         /* R[7:0], G[7:0], B[7:0] */
1827         RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
1828         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1829         RCAR_GP_PIN(4, 1),  RCAR_GP_PIN(4, 0),
1830         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1831         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1832         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 8),
1833         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1834         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1835         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1836 };
1837 static const unsigned int du1_rgb888_mux[] = {
1838         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1839         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1840         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1841         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1842         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1843         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1844 };
1845 static const unsigned int du1_clk0_out_pins[] = {
1846         /* DOTCLKOUT0 */
1847         RCAR_GP_PIN(4, 25),
1848 };
1849 static const unsigned int du1_clk0_out_mux[] = {
1850         DU1_DOTCLKOUT0_MARK
1851 };
1852 static const unsigned int du1_clk1_out_pins[] = {
1853         /* DOTCLKOUT1 */
1854         RCAR_GP_PIN(4, 26),
1855 };
1856 static const unsigned int du1_clk1_out_mux[] = {
1857         DU1_DOTCLKOUT1_MARK
1858 };
1859 static const unsigned int du1_clk_in_pins[] = {
1860         /* DOTCLKIN */
1861         RCAR_GP_PIN(4, 24),
1862 };
1863 static const unsigned int du1_clk_in_mux[] = {
1864         DU1_DOTCLKIN_MARK
1865 };
1866 static const unsigned int du1_sync_pins[] = {
1867         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1868         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
1869 };
1870 static const unsigned int du1_sync_mux[] = {
1871         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1872 };
1873 static const unsigned int du1_oddf_pins[] = {
1874         /* EXODDF/ODDF/DISP/CDE */
1875         RCAR_GP_PIN(4, 29),
1876 };
1877 static const unsigned int du1_oddf_mux[] = {
1878         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1879 };
1880 static const unsigned int du1_cde_pins[] = {
1881         /* CDE */
1882         RCAR_GP_PIN(4, 31),
1883 };
1884 static const unsigned int du1_cde_mux[] = {
1885         DU1_CDE_MARK
1886 };
1887 static const unsigned int du1_disp_pins[] = {
1888         /* DISP */
1889         RCAR_GP_PIN(4, 30),
1890 };
1891 static const unsigned int du1_disp_mux[] = {
1892         DU1_DISP_MARK
1893 };
1894 /* - ETH -------------------------------------------------------------------- */
1895 static const unsigned int eth_link_pins[] = {
1896         /* LINK */
1897         RCAR_GP_PIN(3, 18),
1898 };
1899 static const unsigned int eth_link_mux[] = {
1900         ETH_LINK_MARK,
1901 };
1902 static const unsigned int eth_magic_pins[] = {
1903         /* MAGIC */
1904         RCAR_GP_PIN(3, 22),
1905 };
1906 static const unsigned int eth_magic_mux[] = {
1907         ETH_MAGIC_MARK,
1908 };
1909 static const unsigned int eth_mdio_pins[] = {
1910         /* MDC, MDIO */
1911         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1912 };
1913 static const unsigned int eth_mdio_mux[] = {
1914         ETH_MDC_MARK, ETH_MDIO_MARK,
1915 };
1916 static const unsigned int eth_rmii_pins[] = {
1917         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1918         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1919         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1920         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1921 };
1922 static const unsigned int eth_rmii_mux[] = {
1923         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1924         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1925 };
1926 static const unsigned int eth_link_b_pins[] = {
1927         /* LINK */
1928         RCAR_GP_PIN(5, 15),
1929 };
1930 static const unsigned int eth_link_b_mux[] = {
1931         ETH_LINK_B_MARK,
1932 };
1933 static const unsigned int eth_magic_b_pins[] = {
1934         /* MAGIC */
1935         RCAR_GP_PIN(5, 19),
1936 };
1937 static const unsigned int eth_magic_b_mux[] = {
1938         ETH_MAGIC_B_MARK,
1939 };
1940 static const unsigned int eth_mdio_b_pins[] = {
1941         /* MDC, MDIO */
1942         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1943 };
1944 static const unsigned int eth_mdio_b_mux[] = {
1945         ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1946 };
1947 static const unsigned int eth_rmii_b_pins[] = {
1948         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1949         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1950         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1951         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1952 };
1953 static const unsigned int eth_rmii_b_mux[] = {
1954         ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1955         ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1956 };
1957 /* - HSCIF0 ----------------------------------------------------------------- */
1958 static const unsigned int hscif0_data_pins[] = {
1959         /* RX, TX */
1960         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1961 };
1962 static const unsigned int hscif0_data_mux[] = {
1963         HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1964 };
1965 static const unsigned int hscif0_clk_pins[] = {
1966         /* SCK */
1967         RCAR_GP_PIN(3, 29),
1968 };
1969 static const unsigned int hscif0_clk_mux[] = {
1970         HSCIF0_HSCK_MARK,
1971 };
1972 static const unsigned int hscif0_ctrl_pins[] = {
1973         /* RTS, CTS */
1974         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1975 };
1976 static const unsigned int hscif0_ctrl_mux[] = {
1977         HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1978 };
1979 static const unsigned int hscif0_data_b_pins[] = {
1980         /* RX, TX */
1981         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1982 };
1983 static const unsigned int hscif0_data_b_mux[] = {
1984         HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1985 };
1986 static const unsigned int hscif0_clk_b_pins[] = {
1987         /* SCK */
1988         RCAR_GP_PIN(1, 0),
1989 };
1990 static const unsigned int hscif0_clk_b_mux[] = {
1991         HSCIF0_HSCK_B_MARK,
1992 };
1993 /* - HSCIF1 ----------------------------------------------------------------- */
1994 static const unsigned int hscif1_data_pins[] = {
1995         /* RX, TX */
1996         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1997 };
1998 static const unsigned int hscif1_data_mux[] = {
1999         HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
2000 };
2001 static const unsigned int hscif1_clk_pins[] = {
2002         /* SCK */
2003         RCAR_GP_PIN(4, 10),
2004 };
2005 static const unsigned int hscif1_clk_mux[] = {
2006         HSCIF1_HSCK_MARK,
2007 };
2008 static const unsigned int hscif1_ctrl_pins[] = {
2009         /* RTS, CTS */
2010         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2011 };
2012 static const unsigned int hscif1_ctrl_mux[] = {
2013         HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
2014 };
2015 static const unsigned int hscif1_data_b_pins[] = {
2016         /* RX, TX */
2017         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2018 };
2019 static const unsigned int hscif1_data_b_mux[] = {
2020         HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
2021 };
2022 static const unsigned int hscif1_ctrl_b_pins[] = {
2023         /* RTS, CTS */
2024         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2025 };
2026 static const unsigned int hscif1_ctrl_b_mux[] = {
2027         HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
2028 };
2029 /* - HSCIF2 ----------------------------------------------------------------- */
2030 static const unsigned int hscif2_data_pins[] = {
2031         /* RX, TX */
2032         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2033 };
2034 static const unsigned int hscif2_data_mux[] = {
2035         HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
2036 };
2037 static const unsigned int hscif2_clk_pins[] = {
2038         /* SCK */
2039         RCAR_GP_PIN(0, 10),
2040 };
2041 static const unsigned int hscif2_clk_mux[] = {
2042         HSCIF2_HSCK_MARK,
2043 };
2044 static const unsigned int hscif2_ctrl_pins[] = {
2045         /* RTS, CTS */
2046         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2047 };
2048 static const unsigned int hscif2_ctrl_mux[] = {
2049         HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
2050 };
2051 /* - I2C0 ------------------------------------------------------------------- */
2052 static const unsigned int i2c0_pins[] = {
2053         /* SCL, SDA */
2054         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2055 };
2056 static const unsigned int i2c0_mux[] = {
2057         I2C0_SCL_MARK, I2C0_SDA_MARK,
2058 };
2059 static const unsigned int i2c0_b_pins[] = {
2060         /* SCL, SDA */
2061         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2062 };
2063 static const unsigned int i2c0_b_mux[] = {
2064         I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2065 };
2066 static const unsigned int i2c0_c_pins[] = {
2067         /* SCL, SDA */
2068         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2069 };
2070 static const unsigned int i2c0_c_mux[] = {
2071         I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2072 };
2073 static const unsigned int i2c0_d_pins[] = {
2074         /* SCL, SDA */
2075         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2076 };
2077 static const unsigned int i2c0_d_mux[] = {
2078         I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
2079 };
2080 static const unsigned int i2c0_e_pins[] = {
2081         /* SCL, SDA */
2082         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2083 };
2084 static const unsigned int i2c0_e_mux[] = {
2085         I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
2086 };
2087 /* - I2C1 ------------------------------------------------------------------- */
2088 static const unsigned int i2c1_pins[] = {
2089         /* SCL, SDA */
2090         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2091 };
2092 static const unsigned int i2c1_mux[] = {
2093         I2C1_SCL_MARK, I2C1_SDA_MARK,
2094 };
2095 static const unsigned int i2c1_b_pins[] = {
2096         /* SCL, SDA */
2097         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2098 };
2099 static const unsigned int i2c1_b_mux[] = {
2100         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2101 };
2102 static const unsigned int i2c1_c_pins[] = {
2103         /* SCL, SDA */
2104         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2105 };
2106 static const unsigned int i2c1_c_mux[] = {
2107         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2108 };
2109 static const unsigned int i2c1_d_pins[] = {
2110         /* SCL, SDA */
2111         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2112 };
2113 static const unsigned int i2c1_d_mux[] = {
2114         I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2115 };
2116 static const unsigned int i2c1_e_pins[] = {
2117         /* SCL, SDA */
2118         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2119 };
2120 static const unsigned int i2c1_e_mux[] = {
2121         I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2122 };
2123 /* - I2C2 ------------------------------------------------------------------- */
2124 static const unsigned int i2c2_pins[] = {
2125         /* SCL, SDA */
2126         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2127 };
2128 static const unsigned int i2c2_mux[] = {
2129         I2C2_SCL_MARK, I2C2_SDA_MARK,
2130 };
2131 static const unsigned int i2c2_b_pins[] = {
2132         /* SCL, SDA */
2133         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2134 };
2135 static const unsigned int i2c2_b_mux[] = {
2136         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2137 };
2138 static const unsigned int i2c2_c_pins[] = {
2139         /* SCL, SDA */
2140         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2141 };
2142 static const unsigned int i2c2_c_mux[] = {
2143         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2144 };
2145 static const unsigned int i2c2_d_pins[] = {
2146         /* SCL, SDA */
2147         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2148 };
2149 static const unsigned int i2c2_d_mux[] = {
2150         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2151 };
2152 static const unsigned int i2c2_e_pins[] = {
2153         /* SCL, SDA */
2154         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2155 };
2156 static const unsigned int i2c2_e_mux[] = {
2157         I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2158 };
2159 /* - I2C3 ------------------------------------------------------------------- */
2160 static const unsigned int i2c3_pins[] = {
2161         /* SCL, SDA */
2162         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2163 };
2164 static const unsigned int i2c3_mux[] = {
2165         I2C3_SCL_MARK, I2C3_SDA_MARK,
2166 };
2167 static const unsigned int i2c3_b_pins[] = {
2168         /* SCL, SDA */
2169         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2170 };
2171 static const unsigned int i2c3_b_mux[] = {
2172         I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2173 };
2174 static const unsigned int i2c3_c_pins[] = {
2175         /* SCL, SDA */
2176         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2177 };
2178 static const unsigned int i2c3_c_mux[] = {
2179         I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2180 };
2181 static const unsigned int i2c3_d_pins[] = {
2182         /* SCL, SDA */
2183         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2184 };
2185 static const unsigned int i2c3_d_mux[] = {
2186         I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2187 };
2188 static const unsigned int i2c3_e_pins[] = {
2189         /* SCL, SDA */
2190         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2191 };
2192 static const unsigned int i2c3_e_mux[] = {
2193         I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
2194 };
2195 /* - I2C4 ------------------------------------------------------------------- */
2196 static const unsigned int i2c4_pins[] = {
2197         /* SCL, SDA */
2198         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
2199 };
2200 static const unsigned int i2c4_mux[] = {
2201         I2C4_SCL_MARK, I2C4_SDA_MARK,
2202 };
2203 static const unsigned int i2c4_b_pins[] = {
2204         /* SCL, SDA */
2205         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2206 };
2207 static const unsigned int i2c4_b_mux[] = {
2208         I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2209 };
2210 static const unsigned int i2c4_c_pins[] = {
2211         /* SCL, SDA */
2212         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2213 };
2214 static const unsigned int i2c4_c_mux[] = {
2215         I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2216 };
2217 static const unsigned int i2c4_d_pins[] = {
2218         /* SCL, SDA */
2219         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2220 };
2221 static const unsigned int i2c4_d_mux[] = {
2222         I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
2223 };
2224 static const unsigned int i2c4_e_pins[] = {
2225         /* SCL, SDA */
2226         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2227 };
2228 static const unsigned int i2c4_e_mux[] = {
2229         I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
2230 };
2231 /* - I2C5 ------------------------------------------------------------------- */
2232 static const unsigned int i2c5_pins[] = {
2233         /* SCL, SDA */
2234         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2235 };
2236 static const unsigned int i2c5_mux[] = {
2237         I2C5_SCL_MARK, I2C5_SDA_MARK,
2238 };
2239 static const unsigned int i2c5_b_pins[] = {
2240         /* SCL, SDA */
2241         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2242 };
2243 static const unsigned int i2c5_b_mux[] = {
2244         I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
2245 };
2246 static const unsigned int i2c5_c_pins[] = {
2247         /* SCL, SDA */
2248         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2249 };
2250 static const unsigned int i2c5_c_mux[] = {
2251         I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
2252 };
2253 static const unsigned int i2c5_d_pins[] = {
2254         /* SCL, SDA */
2255         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2256 };
2257 static const unsigned int i2c5_d_mux[] = {
2258         I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
2259 };
2260 /* - INTC ------------------------------------------------------------------- */
2261 static const unsigned int intc_irq0_pins[] = {
2262         /* IRQ0 */
2263         RCAR_GP_PIN(4, 4),
2264 };
2265 static const unsigned int intc_irq0_mux[] = {
2266         IRQ0_MARK,
2267 };
2268 static const unsigned int intc_irq1_pins[] = {
2269         /* IRQ1 */
2270         RCAR_GP_PIN(4, 18),
2271 };
2272 static const unsigned int intc_irq1_mux[] = {
2273         IRQ1_MARK,
2274 };
2275 static const unsigned int intc_irq2_pins[] = {
2276         /* IRQ2 */
2277         RCAR_GP_PIN(4, 19),
2278 };
2279 static const unsigned int intc_irq2_mux[] = {
2280         IRQ2_MARK,
2281 };
2282 static const unsigned int intc_irq3_pins[] = {
2283         /* IRQ3 */
2284         RCAR_GP_PIN(0, 7),
2285 };
2286 static const unsigned int intc_irq3_mux[] = {
2287         IRQ3_MARK,
2288 };
2289 static const unsigned int intc_irq4_pins[] = {
2290         /* IRQ4 */
2291         RCAR_GP_PIN(0, 0),
2292 };
2293 static const unsigned int intc_irq4_mux[] = {
2294         IRQ4_MARK,
2295 };
2296 static const unsigned int intc_irq5_pins[] = {
2297         /* IRQ5 */
2298         RCAR_GP_PIN(4, 1),
2299 };
2300 static const unsigned int intc_irq5_mux[] = {
2301         IRQ5_MARK,
2302 };
2303 static const unsigned int intc_irq6_pins[] = {
2304         /* IRQ6 */
2305         RCAR_GP_PIN(0, 10),
2306 };
2307 static const unsigned int intc_irq6_mux[] = {
2308         IRQ6_MARK,
2309 };
2310 static const unsigned int intc_irq7_pins[] = {
2311         /* IRQ7 */
2312         RCAR_GP_PIN(6, 15),
2313 };
2314 static const unsigned int intc_irq7_mux[] = {
2315         IRQ7_MARK,
2316 };
2317 static const unsigned int intc_irq8_pins[] = {
2318         /* IRQ8 */
2319         RCAR_GP_PIN(5, 0),
2320 };
2321 static const unsigned int intc_irq8_mux[] = {
2322         IRQ8_MARK,
2323 };
2324 static const unsigned int intc_irq9_pins[] = {
2325         /* IRQ9 */
2326         RCAR_GP_PIN(5, 10),
2327 };
2328 static const unsigned int intc_irq9_mux[] = {
2329         IRQ9_MARK,
2330 };
2331 /* - MMCIF ------------------------------------------------------------------ */
2332 static const unsigned int mmc_data1_pins[] = {
2333         /* D[0] */
2334         RCAR_GP_PIN(6, 18),
2335 };
2336 static const unsigned int mmc_data1_mux[] = {
2337         MMC_D0_MARK,
2338 };
2339 static const unsigned int mmc_data4_pins[] = {
2340         /* D[0:3] */
2341         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2342         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2343 };
2344 static const unsigned int mmc_data4_mux[] = {
2345         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2346 };
2347 static const unsigned int mmc_data8_pins[] = {
2348         /* D[0:7] */
2349         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2350         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2351         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2352         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2353 };
2354 static const unsigned int mmc_data8_mux[] = {
2355         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2356         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2357 };
2358 static const unsigned int mmc_ctrl_pins[] = {
2359         /* CLK, CMD */
2360         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2361 };
2362 static const unsigned int mmc_ctrl_mux[] = {
2363         MMC_CLK_MARK, MMC_CMD_MARK,
2364 };
2365 /* - MSIOF0 ----------------------------------------------------------------- */
2366 static const unsigned int msiof0_clk_pins[] = {
2367         /* SCK */
2368         RCAR_GP_PIN(4, 4),
2369 };
2370 static const unsigned int msiof0_clk_mux[] = {
2371         MSIOF0_SCK_MARK,
2372 };
2373 static const unsigned int msiof0_sync_pins[] = {
2374         /* SYNC */
2375         RCAR_GP_PIN(4, 5),
2376 };
2377 static const unsigned int msiof0_sync_mux[] = {
2378         MSIOF0_SYNC_MARK,
2379 };
2380 static const unsigned int msiof0_ss1_pins[] = {
2381         /* SS1 */
2382         RCAR_GP_PIN(4, 6),
2383 };
2384 static const unsigned int msiof0_ss1_mux[] = {
2385         MSIOF0_SS1_MARK,
2386 };
2387 static const unsigned int msiof0_ss2_pins[] = {
2388         /* SS2 */
2389         RCAR_GP_PIN(4, 7),
2390 };
2391 static const unsigned int msiof0_ss2_mux[] = {
2392         MSIOF0_SS2_MARK,
2393 };
2394 static const unsigned int msiof0_rx_pins[] = {
2395         /* RXD */
2396         RCAR_GP_PIN(4, 2),
2397 };
2398 static const unsigned int msiof0_rx_mux[] = {
2399         MSIOF0_RXD_MARK,
2400 };
2401 static const unsigned int msiof0_tx_pins[] = {
2402         /* TXD */
2403         RCAR_GP_PIN(4, 3),
2404 };
2405 static const unsigned int msiof0_tx_mux[] = {
2406         MSIOF0_TXD_MARK,
2407 };
2408 /* - MSIOF1 ----------------------------------------------------------------- */
2409 static const unsigned int msiof1_clk_pins[] = {
2410         /* SCK */
2411         RCAR_GP_PIN(0, 26),
2412 };
2413 static const unsigned int msiof1_clk_mux[] = {
2414         MSIOF1_SCK_MARK,
2415 };
2416 static const unsigned int msiof1_sync_pins[] = {
2417         /* SYNC */
2418         RCAR_GP_PIN(0, 27),
2419 };
2420 static const unsigned int msiof1_sync_mux[] = {
2421         MSIOF1_SYNC_MARK,
2422 };
2423 static const unsigned int msiof1_ss1_pins[] = {
2424         /* SS1 */
2425         RCAR_GP_PIN(0, 28),
2426 };
2427 static const unsigned int msiof1_ss1_mux[] = {
2428         MSIOF1_SS1_MARK,
2429 };
2430 static const unsigned int msiof1_ss2_pins[] = {
2431         /* SS2 */
2432         RCAR_GP_PIN(0, 29),
2433 };
2434 static const unsigned int msiof1_ss2_mux[] = {
2435         MSIOF1_SS2_MARK,
2436 };
2437 static const unsigned int msiof1_rx_pins[] = {
2438         /* RXD */
2439         RCAR_GP_PIN(0, 24),
2440 };
2441 static const unsigned int msiof1_rx_mux[] = {
2442         MSIOF1_RXD_MARK,
2443 };
2444 static const unsigned int msiof1_tx_pins[] = {
2445         /* TXD */
2446         RCAR_GP_PIN(0, 25),
2447 };
2448 static const unsigned int msiof1_tx_mux[] = {
2449         MSIOF1_TXD_MARK,
2450 };
2451 static const unsigned int msiof1_clk_b_pins[] = {
2452         /* SCK */
2453         RCAR_GP_PIN(5, 3),
2454 };
2455 static const unsigned int msiof1_clk_b_mux[] = {
2456         MSIOF1_SCK_B_MARK,
2457 };
2458 static const unsigned int msiof1_sync_b_pins[] = {
2459         /* SYNC */
2460         RCAR_GP_PIN(5, 4),
2461 };
2462 static const unsigned int msiof1_sync_b_mux[] = {
2463         MSIOF1_SYNC_B_MARK,
2464 };
2465 static const unsigned int msiof1_ss1_b_pins[] = {
2466         /* SS1 */
2467         RCAR_GP_PIN(5, 5),
2468 };
2469 static const unsigned int msiof1_ss1_b_mux[] = {
2470         MSIOF1_SS1_B_MARK,
2471 };
2472 static const unsigned int msiof1_ss2_b_pins[] = {
2473         /* SS2 */
2474         RCAR_GP_PIN(5, 6),
2475 };
2476 static const unsigned int msiof1_ss2_b_mux[] = {
2477         MSIOF1_SS2_B_MARK,
2478 };
2479 static const unsigned int msiof1_rx_b_pins[] = {
2480         /* RXD */
2481         RCAR_GP_PIN(5, 1),
2482 };
2483 static const unsigned int msiof1_rx_b_mux[] = {
2484         MSIOF1_RXD_B_MARK,
2485 };
2486 static const unsigned int msiof1_tx_b_pins[] = {
2487         /* TXD */
2488         RCAR_GP_PIN(5, 2),
2489 };
2490 static const unsigned int msiof1_tx_b_mux[] = {
2491         MSIOF1_TXD_B_MARK,
2492 };
2493 /* - MSIOF2 ----------------------------------------------------------------- */
2494 static const unsigned int msiof2_clk_pins[] = {
2495         /* SCK */
2496         RCAR_GP_PIN(1, 0),
2497 };
2498 static const unsigned int msiof2_clk_mux[] = {
2499         MSIOF2_SCK_MARK,
2500 };
2501 static const unsigned int msiof2_sync_pins[] = {
2502         /* SYNC */
2503         RCAR_GP_PIN(1, 1),
2504 };
2505 static const unsigned int msiof2_sync_mux[] = {
2506         MSIOF2_SYNC_MARK,
2507 };
2508 static const unsigned int msiof2_ss1_pins[] = {
2509         /* SS1 */
2510         RCAR_GP_PIN(1, 2),
2511 };
2512 static const unsigned int msiof2_ss1_mux[] = {
2513         MSIOF2_SS1_MARK,
2514 };
2515 static const unsigned int msiof2_ss2_pins[] = {
2516         /* SS2 */
2517         RCAR_GP_PIN(1, 3),
2518 };
2519 static const unsigned int msiof2_ss2_mux[] = {
2520         MSIOF2_SS2_MARK,
2521 };
2522 static const unsigned int msiof2_rx_pins[] = {
2523         /* RXD */
2524         RCAR_GP_PIN(0, 30),
2525 };
2526 static const unsigned int msiof2_rx_mux[] = {
2527         MSIOF2_RXD_MARK,
2528 };
2529 static const unsigned int msiof2_tx_pins[] = {
2530         /* TXD */
2531         RCAR_GP_PIN(0, 31),
2532 };
2533 static const unsigned int msiof2_tx_mux[] = {
2534         MSIOF2_TXD_MARK,
2535 };
2536 static const unsigned int msiof2_clk_b_pins[] = {
2537         /* SCK */
2538         RCAR_GP_PIN(3, 15),
2539 };
2540 static const unsigned int msiof2_clk_b_mux[] = {
2541         MSIOF2_SCK_B_MARK,
2542 };
2543 static const unsigned int msiof2_sync_b_pins[] = {
2544         /* SYNC */
2545         RCAR_GP_PIN(3, 16),
2546 };
2547 static const unsigned int msiof2_sync_b_mux[] = {
2548         MSIOF2_SYNC_B_MARK,
2549 };
2550 static const unsigned int msiof2_ss1_b_pins[] = {
2551         /* SS1 */
2552         RCAR_GP_PIN(3, 17),
2553 };
2554 static const unsigned int msiof2_ss1_b_mux[] = {
2555         MSIOF2_SS1_B_MARK,
2556 };
2557 static const unsigned int msiof2_ss2_b_pins[] = {
2558         /* SS2 */
2559         RCAR_GP_PIN(3, 18),
2560 };
2561 static const unsigned int msiof2_ss2_b_mux[] = {
2562         MSIOF2_SS2_B_MARK,
2563 };
2564 static const unsigned int msiof2_rx_b_pins[] = {
2565         /* RXD */
2566         RCAR_GP_PIN(3, 13),
2567 };
2568 static const unsigned int msiof2_rx_b_mux[] = {
2569         MSIOF2_RXD_B_MARK,
2570 };
2571 static const unsigned int msiof2_tx_b_pins[] = {
2572         /* TXD */
2573         RCAR_GP_PIN(3, 14),
2574 };
2575 static const unsigned int msiof2_tx_b_mux[] = {
2576         MSIOF2_TXD_B_MARK,
2577 };
2578 /* - PWM -------------------------------------------------------------------- */
2579 static const unsigned int pwm0_pins[] = {
2580         RCAR_GP_PIN(1, 14),
2581 };
2582 static const unsigned int pwm0_mux[] = {
2583         PWM0_MARK,
2584 };
2585 static const unsigned int pwm0_b_pins[] = {
2586         RCAR_GP_PIN(5, 3),
2587 };
2588 static const unsigned int pwm0_b_mux[] = {
2589         PWM0_B_MARK,
2590 };
2591 static const unsigned int pwm1_pins[] = {
2592         RCAR_GP_PIN(4, 5),
2593 };
2594 static const unsigned int pwm1_mux[] = {
2595         PWM1_MARK,
2596 };
2597 static const unsigned int pwm1_b_pins[] = {
2598         RCAR_GP_PIN(5, 10),
2599 };
2600 static const unsigned int pwm1_b_mux[] = {
2601         PWM1_B_MARK,
2602 };
2603 static const unsigned int pwm1_c_pins[] = {
2604         RCAR_GP_PIN(1, 18),
2605 };
2606 static const unsigned int pwm1_c_mux[] = {
2607         PWM1_C_MARK,
2608 };
2609 static const unsigned int pwm2_pins[] = {
2610         RCAR_GP_PIN(4, 10),
2611 };
2612 static const unsigned int pwm2_mux[] = {
2613         PWM2_MARK,
2614 };
2615 static const unsigned int pwm2_b_pins[] = {
2616         RCAR_GP_PIN(5, 17),
2617 };
2618 static const unsigned int pwm2_b_mux[] = {
2619         PWM2_B_MARK,
2620 };
2621 static const unsigned int pwm2_c_pins[] = {
2622         RCAR_GP_PIN(0, 13),
2623 };
2624 static const unsigned int pwm2_c_mux[] = {
2625         PWM2_C_MARK,
2626 };
2627 static const unsigned int pwm3_pins[] = {
2628         RCAR_GP_PIN(4, 13),
2629 };
2630 static const unsigned int pwm3_mux[] = {
2631         PWM3_MARK,
2632 };
2633 static const unsigned int pwm3_b_pins[] = {
2634         RCAR_GP_PIN(0, 16),
2635 };
2636 static const unsigned int pwm3_b_mux[] = {
2637         PWM3_B_MARK,
2638 };
2639 static const unsigned int pwm4_pins[] = {
2640         RCAR_GP_PIN(1, 3),
2641 };
2642 static const unsigned int pwm4_mux[] = {
2643         PWM4_MARK,
2644 };
2645 static const unsigned int pwm4_b_pins[] = {
2646         RCAR_GP_PIN(0, 21),
2647 };
2648 static const unsigned int pwm4_b_mux[] = {
2649         PWM4_B_MARK,
2650 };
2651 static const unsigned int pwm5_pins[] = {
2652         RCAR_GP_PIN(3, 30),
2653 };
2654 static const unsigned int pwm5_mux[] = {
2655         PWM5_MARK,
2656 };
2657 static const unsigned int pwm5_b_pins[] = {
2658         RCAR_GP_PIN(4, 0),
2659 };
2660 static const unsigned int pwm5_b_mux[] = {
2661         PWM5_B_MARK,
2662 };
2663 static const unsigned int pwm5_c_pins[] = {
2664         RCAR_GP_PIN(0, 10),
2665 };
2666 static const unsigned int pwm5_c_mux[] = {
2667         PWM5_C_MARK,
2668 };
2669 static const unsigned int pwm6_pins[] = {
2670         RCAR_GP_PIN(4, 8),
2671 };
2672 static const unsigned int pwm6_mux[] = {
2673         PWM6_MARK,
2674 };
2675 static const unsigned int pwm6_b_pins[] = {
2676         RCAR_GP_PIN(0, 7),
2677 };
2678 static const unsigned int pwm6_b_mux[] = {
2679         PWM6_B_MARK,
2680 };
2681 /* - QSPI ------------------------------------------------------------------- */
2682 static const unsigned int qspi_ctrl_pins[] = {
2683         /* SPCLK, SSL */
2684         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2685 };
2686 static const unsigned int qspi_ctrl_mux[] = {
2687         SPCLK_MARK, SSL_MARK,
2688 };
2689 static const unsigned int qspi_data2_pins[] = {
2690         /* MOSI_IO0, MISO_IO1 */
2691         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2692 };
2693 static const unsigned int qspi_data2_mux[] = {
2694         MOSI_IO0_MARK, MISO_IO1_MARK,
2695 };
2696 static const unsigned int qspi_data4_pins[] = {
2697         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2698         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2699         RCAR_GP_PIN(1, 8),
2700 };
2701 static const unsigned int qspi_data4_mux[] = {
2702         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2703 };
2704 /* - SCIF0 ------------------------------------------------------------------ */
2705 static const unsigned int scif0_data_pins[] = {
2706         /* RX, TX */
2707         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2708 };
2709 static const unsigned int scif0_data_mux[] = {
2710         SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2711 };
2712 static const unsigned int scif0_data_b_pins[] = {
2713         /* RX, TX */
2714         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2715 };
2716 static const unsigned int scif0_data_b_mux[] = {
2717         SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2718 };
2719 static const unsigned int scif0_data_c_pins[] = {
2720         /* RX, TX */
2721         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2722 };
2723 static const unsigned int scif0_data_c_mux[] = {
2724         SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2725 };
2726 static const unsigned int scif0_data_d_pins[] = {
2727         /* RX, TX */
2728         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2729 };
2730 static const unsigned int scif0_data_d_mux[] = {
2731         SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2732 };
2733 /* - SCIF1 ------------------------------------------------------------------ */
2734 static const unsigned int scif1_data_pins[] = {
2735         /* RX, TX */
2736         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2737 };
2738 static const unsigned int scif1_data_mux[] = {
2739         SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2740 };
2741 static const unsigned int scif1_clk_pins[] = {
2742         /* SCK */
2743         RCAR_GP_PIN(4, 13),
2744 };
2745 static const unsigned int scif1_clk_mux[] = {
2746         SCIF1_SCK_MARK,
2747 };
2748 static const unsigned int scif1_data_b_pins[] = {
2749         /* RX, TX */
2750         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2751 };
2752 static const unsigned int scif1_data_b_mux[] = {
2753         SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2754 };
2755 static const unsigned int scif1_clk_b_pins[] = {
2756         /* SCK */
2757         RCAR_GP_PIN(5, 10),
2758 };
2759 static const unsigned int scif1_clk_b_mux[] = {
2760         SCIF1_SCK_B_MARK,
2761 };
2762 static const unsigned int scif1_data_c_pins[] = {
2763         /* RX, TX */
2764         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2765 };
2766 static const unsigned int scif1_data_c_mux[] = {
2767         SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2768 };
2769 static const unsigned int scif1_clk_c_pins[] = {
2770         /* SCK */
2771         RCAR_GP_PIN(0, 10),
2772 };
2773 static const unsigned int scif1_clk_c_mux[] = {
2774         SCIF1_SCK_C_MARK,
2775 };
2776 /* - SCIF2 ------------------------------------------------------------------ */
2777 static const unsigned int scif2_data_pins[] = {
2778         /* RX, TX */
2779         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2780 };
2781 static const unsigned int scif2_data_mux[] = {
2782         SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2783 };
2784 static const unsigned int scif2_clk_pins[] = {
2785         /* SCK */
2786         RCAR_GP_PIN(4, 18),
2787 };
2788 static const unsigned int scif2_clk_mux[] = {
2789         SCIF2_SCK_MARK,
2790 };
2791 static const unsigned int scif2_data_b_pins[] = {
2792         /* RX, TX */
2793         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2794 };
2795 static const unsigned int scif2_data_b_mux[] = {
2796         SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2797 };
2798 static const unsigned int scif2_clk_b_pins[] = {
2799         /* SCK */
2800         RCAR_GP_PIN(5, 17),
2801 };
2802 static const unsigned int scif2_clk_b_mux[] = {
2803         SCIF2_SCK_B_MARK,
2804 };
2805 static const unsigned int scif2_data_c_pins[] = {
2806         /* RX, TX */
2807         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2808 };
2809 static const unsigned int scif2_data_c_mux[] = {
2810         SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2811 };
2812 static const unsigned int scif2_clk_c_pins[] = {
2813         /* SCK */
2814         RCAR_GP_PIN(3, 19),
2815 };
2816 static const unsigned int scif2_clk_c_mux[] = {
2817         SCIF2_SCK_C_MARK,
2818 };
2819 /* - SCIF3 ------------------------------------------------------------------ */
2820 static const unsigned int scif3_data_pins[] = {
2821         /* RX, TX */
2822         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2823 };
2824 static const unsigned int scif3_data_mux[] = {
2825         SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2826 };
2827 static const unsigned int scif3_clk_pins[] = {
2828         /* SCK */
2829         RCAR_GP_PIN(4, 19),
2830 };
2831 static const unsigned int scif3_clk_mux[] = {
2832         SCIF3_SCK_MARK,
2833 };
2834 static const unsigned int scif3_data_b_pins[] = {
2835         /* RX, TX */
2836         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2837 };
2838 static const unsigned int scif3_data_b_mux[] = {
2839         SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2840 };
2841 static const unsigned int scif3_clk_b_pins[] = {
2842         /* SCK */
2843         RCAR_GP_PIN(3, 22),
2844 };
2845 static const unsigned int scif3_clk_b_mux[] = {
2846         SCIF3_SCK_B_MARK,
2847 };
2848 /* - SCIF4 ------------------------------------------------------------------ */
2849 static const unsigned int scif4_data_pins[] = {
2850         /* RX, TX */
2851         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2852 };
2853 static const unsigned int scif4_data_mux[] = {
2854         SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2855 };
2856 static const unsigned int scif4_data_b_pins[] = {
2857         /* RX, TX */
2858         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2859 };
2860 static const unsigned int scif4_data_b_mux[] = {
2861         SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2862 };
2863 static const unsigned int scif4_data_c_pins[] = {
2864         /* RX, TX */
2865         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2866 };
2867 static const unsigned int scif4_data_c_mux[] = {
2868         SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2869 };
2870 static const unsigned int scif4_data_d_pins[] = {
2871         /* RX, TX */
2872         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2873 };
2874 static const unsigned int scif4_data_d_mux[] = {
2875         SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2876 };
2877 static const unsigned int scif4_data_e_pins[] = {
2878         /* RX, TX */
2879         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2880 };
2881 static const unsigned int scif4_data_e_mux[] = {
2882         SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2883 };
2884 /* - SCIF5 ------------------------------------------------------------------ */
2885 static const unsigned int scif5_data_pins[] = {
2886         /* RX, TX */
2887         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2888 };
2889 static const unsigned int scif5_data_mux[] = {
2890         SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2891 };
2892 static const unsigned int scif5_data_b_pins[] = {
2893         /* RX, TX */
2894         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2895 };
2896 static const unsigned int scif5_data_b_mux[] = {
2897         SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2898 };
2899 static const unsigned int scif5_data_c_pins[] = {
2900         /* RX, TX */
2901         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2902 };
2903 static const unsigned int scif5_data_c_mux[] = {
2904         SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2905 };
2906 static const unsigned int scif5_data_d_pins[] = {
2907         /* RX, TX */
2908         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2909 };
2910 static const unsigned int scif5_data_d_mux[] = {
2911         SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2912 };
2913 /* - SCIFA0 ----------------------------------------------------------------- */
2914 static const unsigned int scifa0_data_pins[] = {
2915         /* RXD, TXD */
2916         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2917 };
2918 static const unsigned int scifa0_data_mux[] = {
2919         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2920 };
2921 static const unsigned int scifa0_data_b_pins[] = {
2922         /* RXD, TXD */
2923         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2924 };
2925 static const unsigned int scifa0_data_b_mux[] = {
2926         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2927 };
2928 static const unsigned int scifa0_data_c_pins[] = {
2929         /* RXD, TXD */
2930         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2931 };
2932 static const unsigned int scifa0_data_c_mux[] = {
2933         SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2934 };
2935 static const unsigned int scifa0_data_d_pins[] = {
2936         /* RXD, TXD */
2937         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2938 };
2939 static const unsigned int scifa0_data_d_mux[] = {
2940         SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2941 };
2942 /* - SCIFA1 ----------------------------------------------------------------- */
2943 static const unsigned int scifa1_data_pins[] = {
2944         /* RXD, TXD */
2945         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2946 };
2947 static const unsigned int scifa1_data_mux[] = {
2948         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2949 };
2950 static const unsigned int scifa1_clk_pins[] = {
2951         /* SCK */
2952         RCAR_GP_PIN(0, 13),
2953 };
2954 static const unsigned int scifa1_clk_mux[] = {
2955         SCIFA1_SCK_MARK,
2956 };
2957 static const unsigned int scifa1_data_b_pins[] = {
2958         /* RXD, TXD */
2959         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2960 };
2961 static const unsigned int scifa1_data_b_mux[] = {
2962         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2963 };
2964 static const unsigned int scifa1_clk_b_pins[] = {
2965         /* SCK */
2966         RCAR_GP_PIN(4, 27),
2967 };
2968 static const unsigned int scifa1_clk_b_mux[] = {
2969         SCIFA1_SCK_B_MARK,
2970 };
2971 static const unsigned int scifa1_data_c_pins[] = {
2972         /* RXD, TXD */
2973         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2974 };
2975 static const unsigned int scifa1_data_c_mux[] = {
2976         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2977 };
2978 static const unsigned int scifa1_clk_c_pins[] = {
2979         /* SCK */
2980         RCAR_GP_PIN(5, 4),
2981 };
2982 static const unsigned int scifa1_clk_c_mux[] = {
2983         SCIFA1_SCK_C_MARK,
2984 };
2985 /* - SCIFA2 ----------------------------------------------------------------- */
2986 static const unsigned int scifa2_data_pins[] = {
2987         /* RXD, TXD */
2988         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2989 };
2990 static const unsigned int scifa2_data_mux[] = {
2991         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2992 };
2993 static const unsigned int scifa2_clk_pins[] = {
2994         /* SCK */
2995         RCAR_GP_PIN(1, 15),
2996 };
2997 static const unsigned int scifa2_clk_mux[] = {
2998         SCIFA2_SCK_MARK,
2999 };
3000 static const unsigned int scifa2_data_b_pins[] = {
3001         /* RXD, TXD */
3002         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
3003 };
3004 static const unsigned int scifa2_data_b_mux[] = {
3005         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3006 };
3007 static const unsigned int scifa2_clk_b_pins[] = {
3008         /* SCK */
3009         RCAR_GP_PIN(4, 30),
3010 };
3011 static const unsigned int scifa2_clk_b_mux[] = {
3012         SCIFA2_SCK_B_MARK,
3013 };
3014 /* - SCIFA3 ----------------------------------------------------------------- */
3015 static const unsigned int scifa3_data_pins[] = {
3016         /* RXD, TXD */
3017         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3018 };
3019 static const unsigned int scifa3_data_mux[] = {
3020         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3021 };
3022 static const unsigned int scifa3_clk_pins[] = {
3023         /* SCK */
3024         RCAR_GP_PIN(4, 24),
3025 };
3026 static const unsigned int scifa3_clk_mux[] = {
3027         SCIFA3_SCK_MARK,
3028 };
3029 static const unsigned int scifa3_data_b_pins[] = {
3030         /* RXD, TXD */
3031         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
3032 };
3033 static const unsigned int scifa3_data_b_mux[] = {
3034         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3035 };
3036 static const unsigned int scifa3_clk_b_pins[] = {
3037         /* SCK */
3038         RCAR_GP_PIN(0, 0),
3039 };
3040 static const unsigned int scifa3_clk_b_mux[] = {
3041         SCIFA3_SCK_B_MARK,
3042 };
3043 /* - SCIFA4 ----------------------------------------------------------------- */
3044 static const unsigned int scifa4_data_pins[] = {
3045         /* RXD, TXD */
3046         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
3047 };
3048 static const unsigned int scifa4_data_mux[] = {
3049         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3050 };
3051 static const unsigned int scifa4_data_b_pins[] = {
3052         /* RXD, TXD */
3053         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
3054 };
3055 static const unsigned int scifa4_data_b_mux[] = {
3056         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3057 };
3058 static const unsigned int scifa4_data_c_pins[] = {
3059         /* RXD, TXD */
3060         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3061 };
3062 static const unsigned int scifa4_data_c_mux[] = {
3063         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3064 };
3065 static const unsigned int scifa4_data_d_pins[] = {
3066         /* RXD, TXD */
3067         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3068 };
3069 static const unsigned int scifa4_data_d_mux[] = {
3070         SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
3071 };
3072 /* - SCIFA5 ----------------------------------------------------------------- */
3073 static const unsigned int scifa5_data_pins[] = {
3074         /* RXD, TXD */
3075         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3076 };
3077 static const unsigned int scifa5_data_mux[] = {
3078         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3079 };
3080 static const unsigned int scifa5_data_b_pins[] = {
3081         /* RXD, TXD */
3082         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
3083 };
3084 static const unsigned int scifa5_data_b_mux[] = {
3085         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3086 };
3087 static const unsigned int scifa5_data_c_pins[] = {
3088         /* RXD, TXD */
3089         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
3090 };
3091 static const unsigned int scifa5_data_c_mux[] = {
3092         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3093 };
3094 static const unsigned int scifa5_data_d_pins[] = {
3095         /* RXD, TXD */
3096         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3097 };
3098 static const unsigned int scifa5_data_d_mux[] = {
3099         SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
3100 };
3101 /* - SCIFB0 ----------------------------------------------------------------- */
3102 static const unsigned int scifb0_data_pins[] = {
3103         /* RXD, TXD */
3104         RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
3105 };
3106 static const unsigned int scifb0_data_mux[] = {
3107         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3108 };
3109 static const unsigned int scifb0_clk_pins[] = {
3110         /* SCK */
3111         RCAR_GP_PIN(0, 19),
3112 };
3113 static const unsigned int scifb0_clk_mux[] = {
3114         SCIFB0_SCK_MARK,
3115 };
3116 static const unsigned int scifb0_ctrl_pins[] = {
3117         /* RTS, CTS */
3118         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
3119 };
3120 static const unsigned int scifb0_ctrl_mux[] = {
3121         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3122 };
3123 /* - SCIFB1 ----------------------------------------------------------------- */
3124 static const unsigned int scifb1_data_pins[] = {
3125         /* RXD, TXD */
3126         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
3127 };
3128 static const unsigned int scifb1_data_mux[] = {
3129         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3130 };
3131 static const unsigned int scifb1_clk_pins[] = {
3132         /* SCK */
3133         RCAR_GP_PIN(0, 16),
3134 };
3135 static const unsigned int scifb1_clk_mux[] = {
3136         SCIFB1_SCK_MARK,
3137 };
3138 /* - SCIFB2 ----------------------------------------------------------------- */
3139 static const unsigned int scifb2_data_pins[] = {
3140         /* RXD, TXD */
3141         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3142 };
3143 static const unsigned int scifb2_data_mux[] = {
3144         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3145 };
3146 static const unsigned int scifb2_clk_pins[] = {
3147         /* SCK */
3148         RCAR_GP_PIN(1, 15),
3149 };
3150 static const unsigned int scifb2_clk_mux[] = {
3151         SCIFB2_SCK_MARK,
3152 };
3153 static const unsigned int scifb2_ctrl_pins[] = {
3154         /* RTS, CTS */
3155         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
3156 };
3157 static const unsigned int scifb2_ctrl_mux[] = {
3158         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3159 };
3160 /* - SCIF Clock ------------------------------------------------------------- */
3161 static const unsigned int scif_clk_pins[] = {
3162         /* SCIF_CLK */
3163         RCAR_GP_PIN(1, 23),
3164 };
3165 static const unsigned int scif_clk_mux[] = {
3166         SCIF_CLK_MARK,
3167 };
3168 static const unsigned int scif_clk_b_pins[] = {
3169         /* SCIF_CLK */
3170         RCAR_GP_PIN(3, 29),
3171 };
3172 static const unsigned int scif_clk_b_mux[] = {
3173         SCIF_CLK_B_MARK,
3174 };
3175 /* - SDHI0 ------------------------------------------------------------------ */
3176 static const unsigned int sdhi0_data1_pins[] = {
3177         /* D0 */
3178         RCAR_GP_PIN(6, 2),
3179 };
3180 static const unsigned int sdhi0_data1_mux[] = {
3181         SD0_DATA0_MARK,
3182 };
3183 static const unsigned int sdhi0_data4_pins[] = {
3184         /* D[0:3] */
3185         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3186         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3187 };
3188 static const unsigned int sdhi0_data4_mux[] = {
3189         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3190 };
3191 static const unsigned int sdhi0_ctrl_pins[] = {
3192         /* CLK, CMD */
3193         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3194 };
3195 static const unsigned int sdhi0_ctrl_mux[] = {
3196         SD0_CLK_MARK, SD0_CMD_MARK,
3197 };
3198 static const unsigned int sdhi0_cd_pins[] = {
3199         /* CD */
3200         RCAR_GP_PIN(6, 6),
3201 };
3202 static const unsigned int sdhi0_cd_mux[] = {
3203         SD0_CD_MARK,
3204 };
3205 static const unsigned int sdhi0_wp_pins[] = {
3206         /* WP */
3207         RCAR_GP_PIN(6, 7),
3208 };
3209 static const unsigned int sdhi0_wp_mux[] = {
3210         SD0_WP_MARK,
3211 };
3212 /* - SDHI1 ------------------------------------------------------------------ */
3213 static const unsigned int sdhi1_data1_pins[] = {
3214         /* D0 */
3215         RCAR_GP_PIN(6, 10),
3216 };
3217 static const unsigned int sdhi1_data1_mux[] = {
3218         SD1_DATA0_MARK,
3219 };
3220 static const unsigned int sdhi1_data4_pins[] = {
3221         /* D[0:3] */
3222         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3223         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3224 };
3225 static const unsigned int sdhi1_data4_mux[] = {
3226         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3227 };
3228 static const unsigned int sdhi1_ctrl_pins[] = {
3229         /* CLK, CMD */
3230         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3231 };
3232 static const unsigned int sdhi1_ctrl_mux[] = {
3233         SD1_CLK_MARK, SD1_CMD_MARK,
3234 };
3235 static const unsigned int sdhi1_cd_pins[] = {
3236         /* CD */
3237         RCAR_GP_PIN(6, 14),
3238 };
3239 static const unsigned int sdhi1_cd_mux[] = {
3240         SD1_CD_MARK,
3241 };
3242 static const unsigned int sdhi1_wp_pins[] = {
3243         /* WP */
3244         RCAR_GP_PIN(6, 15),
3245 };
3246 static const unsigned int sdhi1_wp_mux[] = {
3247         SD1_WP_MARK,
3248 };
3249 /* - SDHI2 ------------------------------------------------------------------ */
3250 static const unsigned int sdhi2_data1_pins[] = {
3251         /* D0 */
3252         RCAR_GP_PIN(6, 18),
3253 };
3254 static const unsigned int sdhi2_data1_mux[] = {
3255         SD2_DATA0_MARK,
3256 };
3257 static const unsigned int sdhi2_data4_pins[] = {
3258         /* D[0:3] */
3259         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3260         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3261 };
3262 static const unsigned int sdhi2_data4_mux[] = {
3263         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3264 };
3265 static const unsigned int sdhi2_ctrl_pins[] = {
3266         /* CLK, CMD */
3267         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3268 };
3269 static const unsigned int sdhi2_ctrl_mux[] = {
3270         SD2_CLK_MARK, SD2_CMD_MARK,
3271 };
3272 static const unsigned int sdhi2_cd_pins[] = {
3273         /* CD */
3274         RCAR_GP_PIN(6, 22),
3275 };
3276 static const unsigned int sdhi2_cd_mux[] = {
3277         SD2_CD_MARK,
3278 };
3279 static const unsigned int sdhi2_wp_pins[] = {
3280         /* WP */
3281         RCAR_GP_PIN(6, 23),
3282 };
3283 static const unsigned int sdhi2_wp_mux[] = {
3284         SD2_WP_MARK,
3285 };
3286 /* - SSI -------------------------------------------------------------------- */
3287 static const unsigned int ssi0_data_pins[] = {
3288         /* SDATA0 */
3289         RCAR_GP_PIN(5, 3),
3290 };
3291 static const unsigned int ssi0_data_mux[] = {
3292         SSI_SDATA0_MARK,
3293 };
3294 static const unsigned int ssi0129_ctrl_pins[] = {
3295         /* SCK0129, WS0129 */
3296         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3297 };
3298 static const unsigned int ssi0129_ctrl_mux[] = {
3299         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3300 };
3301 static const unsigned int ssi1_data_pins[] = {
3302         /* SDATA1 */
3303         RCAR_GP_PIN(5, 13),
3304 };
3305 static const unsigned int ssi1_data_mux[] = {
3306         SSI_SDATA1_MARK,
3307 };
3308 static const unsigned int ssi1_ctrl_pins[] = {
3309         /* SCK1, WS1 */
3310         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3311 };
3312 static const unsigned int ssi1_ctrl_mux[] = {
3313         SSI_SCK1_MARK, SSI_WS1_MARK,
3314 };
3315 static const unsigned int ssi1_data_b_pins[] = {
3316         /* SDATA1 */
3317         RCAR_GP_PIN(4, 13),
3318 };
3319 static const unsigned int ssi1_data_b_mux[] = {
3320         SSI_SDATA1_B_MARK,
3321 };
3322 static const unsigned int ssi1_ctrl_b_pins[] = {
3323         /* SCK1, WS1 */
3324         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3325 };
3326 static const unsigned int ssi1_ctrl_b_mux[] = {
3327         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3328 };
3329 static const unsigned int ssi2_data_pins[] = {
3330         /* SDATA2 */
3331         RCAR_GP_PIN(5, 16),
3332 };
3333 static const unsigned int ssi2_data_mux[] = {
3334         SSI_SDATA2_MARK,
3335 };
3336 static const unsigned int ssi2_ctrl_pins[] = {
3337         /* SCK2, WS2 */
3338         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3339 };
3340 static const unsigned int ssi2_ctrl_mux[] = {
3341         SSI_SCK2_MARK, SSI_WS2_MARK,
3342 };
3343 static const unsigned int ssi2_data_b_pins[] = {
3344         /* SDATA2 */
3345         RCAR_GP_PIN(4, 16),
3346 };
3347 static const unsigned int ssi2_data_b_mux[] = {
3348         SSI_SDATA2_B_MARK,
3349 };
3350 static const unsigned int ssi2_ctrl_b_pins[] = {
3351         /* SCK2, WS2 */
3352         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3353 };
3354 static const unsigned int ssi2_ctrl_b_mux[] = {
3355         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3356 };
3357 static const unsigned int ssi3_data_pins[] = {
3358         /* SDATA3 */
3359         RCAR_GP_PIN(5, 6),
3360 };
3361 static const unsigned int ssi3_data_mux[] = {
3362         SSI_SDATA3_MARK
3363 };
3364 static const unsigned int ssi34_ctrl_pins[] = {
3365         /* SCK34, WS34 */
3366         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
3367 };
3368 static const unsigned int ssi34_ctrl_mux[] = {
3369         SSI_SCK34_MARK, SSI_WS34_MARK,
3370 };
3371 static const unsigned int ssi4_data_pins[] = {
3372         /* SDATA4 */
3373         RCAR_GP_PIN(5, 9),
3374 };
3375 static const unsigned int ssi4_data_mux[] = {
3376         SSI_SDATA4_MARK,
3377 };
3378 static const unsigned int ssi4_ctrl_pins[] = {
3379         /* SCK4, WS4 */
3380         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3381 };
3382 static const unsigned int ssi4_ctrl_mux[] = {
3383         SSI_SCK4_MARK, SSI_WS4_MARK,
3384 };
3385 static const unsigned int ssi4_data_b_pins[] = {
3386         /* SDATA4 */
3387         RCAR_GP_PIN(4, 22),
3388 };
3389 static const unsigned int ssi4_data_b_mux[] = {
3390         SSI_SDATA4_B_MARK,
3391 };
3392 static const unsigned int ssi4_ctrl_b_pins[] = {
3393         /* SCK4, WS4 */
3394         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3395 };
3396 static const unsigned int ssi4_ctrl_b_mux[] = {
3397         SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
3398 };
3399 static const unsigned int ssi5_data_pins[] = {
3400         /* SDATA5 */
3401         RCAR_GP_PIN(4, 26),
3402 };
3403 static const unsigned int ssi5_data_mux[] = {
3404         SSI_SDATA5_MARK,
3405 };
3406 static const unsigned int ssi5_ctrl_pins[] = {
3407         /* SCK5, WS5 */
3408         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3409 };
3410 static const unsigned int ssi5_ctrl_mux[] = {
3411         SSI_SCK5_MARK, SSI_WS5_MARK,
3412 };
3413 static const unsigned int ssi5_data_b_pins[] = {
3414         /* SDATA5 */
3415         RCAR_GP_PIN(3, 21),
3416 };
3417 static const unsigned int ssi5_data_b_mux[] = {
3418         SSI_SDATA5_B_MARK,
3419 };
3420 static const unsigned int ssi5_ctrl_b_pins[] = {
3421         /* SCK5, WS5 */
3422         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3423 };
3424 static const unsigned int ssi5_ctrl_b_mux[] = {
3425         SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
3426 };
3427 static const unsigned int ssi6_data_pins[] = {
3428         /* SDATA6 */
3429         RCAR_GP_PIN(4, 29),
3430 };
3431 static const unsigned int ssi6_data_mux[] = {
3432         SSI_SDATA6_MARK,
3433 };
3434 static const unsigned int ssi6_ctrl_pins[] = {
3435         /* SCK6, WS6 */
3436         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3437 };
3438 static const unsigned int ssi6_ctrl_mux[] = {
3439         SSI_SCK6_MARK, SSI_WS6_MARK,
3440 };
3441 static const unsigned int ssi6_data_b_pins[] = {
3442         /* SDATA6 */
3443         RCAR_GP_PIN(3, 24),
3444 };
3445 static const unsigned int ssi6_data_b_mux[] = {
3446         SSI_SDATA6_B_MARK,
3447 };
3448 static const unsigned int ssi6_ctrl_b_pins[] = {
3449         /* SCK6, WS6 */
3450         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
3451 };
3452 static const unsigned int ssi6_ctrl_b_mux[] = {
3453         SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3454 };
3455 static const unsigned int ssi7_data_pins[] = {
3456         /* SDATA7 */
3457         RCAR_GP_PIN(5, 0),
3458 };
3459 static const unsigned int ssi7_data_mux[] = {
3460         SSI_SDATA7_MARK,
3461 };
3462 static const unsigned int ssi78_ctrl_pins[] = {
3463         /* SCK78, WS78 */
3464         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
3465 };
3466 static const unsigned int ssi78_ctrl_mux[] = {
3467         SSI_SCK78_MARK, SSI_WS78_MARK,
3468 };
3469 static const unsigned int ssi7_data_b_pins[] = {
3470         /* SDATA7 */
3471         RCAR_GP_PIN(3, 27),
3472 };
3473 static const unsigned int ssi7_data_b_mux[] = {
3474         SSI_SDATA7_B_MARK,
3475 };
3476 static const unsigned int ssi78_ctrl_b_pins[] = {
3477         /* SCK78, WS78 */
3478         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3479 };
3480 static const unsigned int ssi78_ctrl_b_mux[] = {
3481         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3482 };
3483 static const unsigned int ssi8_data_pins[] = {
3484         /* SDATA8 */
3485         RCAR_GP_PIN(5, 10),
3486 };
3487 static const unsigned int ssi8_data_mux[] = {
3488         SSI_SDATA8_MARK,
3489 };
3490 static const unsigned int ssi8_data_b_pins[] = {
3491         /* SDATA8 */
3492         RCAR_GP_PIN(3, 28),
3493 };
3494 static const unsigned int ssi8_data_b_mux[] = {
3495         SSI_SDATA8_B_MARK,
3496 };
3497 static const unsigned int ssi9_data_pins[] = {
3498         /* SDATA9 */
3499         RCAR_GP_PIN(5, 19),
3500 };
3501 static const unsigned int ssi9_data_mux[] = {
3502         SSI_SDATA9_MARK,
3503 };
3504 static const unsigned int ssi9_ctrl_pins[] = {
3505         /* SCK9, WS9 */
3506         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
3507 };
3508 static const unsigned int ssi9_ctrl_mux[] = {
3509         SSI_SCK9_MARK, SSI_WS9_MARK,
3510 };
3511 static const unsigned int ssi9_data_b_pins[] = {
3512         /* SDATA9 */
3513         RCAR_GP_PIN(4, 19),
3514 };
3515 static const unsigned int ssi9_data_b_mux[] = {
3516         SSI_SDATA9_B_MARK,
3517 };
3518 static const unsigned int ssi9_ctrl_b_pins[] = {
3519         /* SCK9, WS9 */
3520         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3521 };
3522 static const unsigned int ssi9_ctrl_b_mux[] = {
3523         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3524 };
3525 /* - TPU -------------------------------------------------------------------- */
3526 static const unsigned int tpu_to0_pins[] = {
3527         RCAR_GP_PIN(3, 31),
3528 };
3529 static const unsigned int tpu_to0_mux[] = {
3530         TPUTO0_MARK,
3531 };
3532 static const unsigned int tpu_to0_b_pins[] = {
3533         RCAR_GP_PIN(3, 30),
3534 };
3535 static const unsigned int tpu_to0_b_mux[] = {
3536         TPUTO0_B_MARK,
3537 };
3538 static const unsigned int tpu_to0_c_pins[] = {
3539         RCAR_GP_PIN(1, 18),
3540 };
3541 static const unsigned int tpu_to0_c_mux[] = {
3542         TPUTO0_C_MARK,
3543 };
3544 static const unsigned int tpu_to1_pins[] = {
3545         RCAR_GP_PIN(4, 9),
3546 };
3547 static const unsigned int tpu_to1_mux[] = {
3548         TPUTO1_MARK,
3549 };
3550 static const unsigned int tpu_to1_b_pins[] = {
3551         RCAR_GP_PIN(4, 0),
3552 };
3553 static const unsigned int tpu_to1_b_mux[] = {
3554         TPUTO1_B_MARK,
3555 };
3556 static const unsigned int tpu_to1_c_pins[] = {
3557         RCAR_GP_PIN(4, 4),
3558 };
3559 static const unsigned int tpu_to1_c_mux[] = {
3560         TPUTO1_C_MARK,
3561 };
3562 static const unsigned int tpu_to2_pins[] = {
3563         RCAR_GP_PIN(1, 3),
3564 };
3565 static const unsigned int tpu_to2_mux[] = {
3566         TPUTO2_MARK,
3567 };
3568 static const unsigned int tpu_to2_b_pins[] = {
3569         RCAR_GP_PIN(1, 0),
3570 };
3571 static const unsigned int tpu_to2_b_mux[] = {
3572         TPUTO2_B_MARK,
3573 };
3574 static const unsigned int tpu_to2_c_pins[] = {
3575         RCAR_GP_PIN(0, 22),
3576 };
3577 static const unsigned int tpu_to2_c_mux[] = {
3578         TPUTO2_C_MARK,
3579 };
3580 static const unsigned int tpu_to3_pins[] = {
3581         RCAR_GP_PIN(1, 14),
3582 };
3583 static const unsigned int tpu_to3_mux[] = {
3584         TPUTO3_MARK,
3585 };
3586 static const unsigned int tpu_to3_b_pins[] = {
3587         RCAR_GP_PIN(1, 13),
3588 };
3589 static const unsigned int tpu_to3_b_mux[] = {
3590         TPUTO3_B_MARK,
3591 };
3592 static const unsigned int tpu_to3_c_pins[] = {
3593         RCAR_GP_PIN(0, 21),
3594 };
3595 static const unsigned int tpu_to3_c_mux[] = {
3596         TPUTO3_C_MARK,
3597 };
3598 /* - USB0 ------------------------------------------------------------------- */
3599 static const unsigned int usb0_pins[] = {
3600         RCAR_GP_PIN(5, 24), /* PWEN */
3601         RCAR_GP_PIN(5, 25), /* OVC */
3602 };
3603 static const unsigned int usb0_mux[] = {
3604         USB0_PWEN_MARK,
3605         USB0_OVC_MARK,
3606 };
3607 /* - USB1 ------------------------------------------------------------------- */
3608 static const unsigned int usb1_pins[] = {
3609         RCAR_GP_PIN(5, 26), /* PWEN */
3610         RCAR_GP_PIN(5, 27), /* OVC */
3611 };
3612 static const unsigned int usb1_mux[] = {
3613         USB1_PWEN_MARK,
3614         USB1_OVC_MARK,
3615 };
3616 /* - VIN0 ------------------------------------------------------------------- */
3617 static const union vin_data vin0_data_pins = {
3618         .data24 = {
3619                 /* B */
3620                 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3621                 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3622                 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3623                 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3624                 /* G */
3625                 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3626                 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3627                 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3628                 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3629                 /* R */
3630                 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3631                 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3632                 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3633                 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3634         },
3635 };
3636 static const union vin_data vin0_data_mux = {
3637         .data24 = {
3638                 /* B */
3639                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3640                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3641                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3642                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3643                 /* G */
3644                 VI0_G0_MARK, VI0_G1_MARK,
3645                 VI0_G2_MARK, VI0_G3_MARK,
3646                 VI0_G4_MARK, VI0_G5_MARK,
3647                 VI0_G6_MARK, VI0_G7_MARK,
3648                 /* R */
3649                 VI0_R0_MARK, VI0_R1_MARK,
3650                 VI0_R2_MARK, VI0_R3_MARK,
3651                 VI0_R4_MARK, VI0_R5_MARK,
3652                 VI0_R6_MARK, VI0_R7_MARK,
3653         },
3654 };
3655 static const unsigned int vin0_data18_pins[] = {
3656         /* B */
3657         RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3658         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3659         RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3660         /* G */
3661         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3662         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3663         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3664         /* R */
3665         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3666         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3667         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3668 };
3669 static const unsigned int vin0_data18_mux[] = {
3670         /* B */
3671         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3672         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3673         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3674         /* G */
3675         VI0_G2_MARK, VI0_G3_MARK,
3676         VI0_G4_MARK, VI0_G5_MARK,
3677         VI0_G6_MARK, VI0_G7_MARK,
3678         /* R */
3679         VI0_R2_MARK, VI0_R3_MARK,
3680         VI0_R4_MARK, VI0_R5_MARK,
3681         VI0_R6_MARK, VI0_R7_MARK,
3682 };
3683 static const unsigned int vin0_sync_pins[] = {
3684         RCAR_GP_PIN(3, 11), /* HSYNC */
3685         RCAR_GP_PIN(3, 12), /* VSYNC */
3686 };
3687 static const unsigned int vin0_sync_mux[] = {
3688         VI0_HSYNC_N_MARK,
3689         VI0_VSYNC_N_MARK,
3690 };
3691 static const unsigned int vin0_field_pins[] = {
3692         RCAR_GP_PIN(3, 10),
3693 };
3694 static const unsigned int vin0_field_mux[] = {
3695         VI0_FIELD_MARK,
3696 };
3697 static const unsigned int vin0_clkenb_pins[] = {
3698         RCAR_GP_PIN(3, 9),
3699 };
3700 static const unsigned int vin0_clkenb_mux[] = {
3701         VI0_CLKENB_MARK,
3702 };
3703 static const unsigned int vin0_clk_pins[] = {
3704         RCAR_GP_PIN(3, 0),
3705 };
3706 static const unsigned int vin0_clk_mux[] = {
3707         VI0_CLK_MARK,
3708 };
3709 /* - VIN1 ------------------------------------------------------------------- */
3710 static const union vin_data12 vin1_data_pins = {
3711         .data12 = {
3712                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3713                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3714                 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3715                 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3716                 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3717                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3718         },
3719 };
3720 static const union vin_data12 vin1_data_mux = {
3721         .data12 = {
3722                 VI1_DATA0_MARK, VI1_DATA1_MARK,
3723                 VI1_DATA2_MARK, VI1_DATA3_MARK,
3724                 VI1_DATA4_MARK, VI1_DATA5_MARK,
3725                 VI1_DATA6_MARK, VI1_DATA7_MARK,
3726                 VI1_DATA8_MARK, VI1_DATA9_MARK,
3727                 VI1_DATA10_MARK, VI1_DATA11_MARK,
3728         },
3729 };
3730 static const unsigned int vin1_sync_pins[] = {
3731         RCAR_GP_PIN(5, 22), /* HSYNC */
3732         RCAR_GP_PIN(5, 23), /* VSYNC */
3733 };
3734 static const unsigned int vin1_sync_mux[] = {
3735         VI1_HSYNC_N_MARK,
3736         VI1_VSYNC_N_MARK,
3737 };
3738 static const unsigned int vin1_field_pins[] = {
3739         RCAR_GP_PIN(5, 21),
3740 };
3741 static const unsigned int vin1_field_mux[] = {
3742         VI1_FIELD_MARK,
3743 };
3744 static const unsigned int vin1_clkenb_pins[] = {
3745         RCAR_GP_PIN(5, 20),
3746 };
3747 static const unsigned int vin1_clkenb_mux[] = {
3748         VI1_CLKENB_MARK,
3749 };
3750 static const unsigned int vin1_clk_pins[] = {
3751         RCAR_GP_PIN(5, 11),
3752 };
3753 static const unsigned int vin1_clk_mux[] = {
3754         VI1_CLK_MARK,
3755 };
3756
3757 static const struct sh_pfc_pin_group pinmux_groups[] = {
3758         SH_PFC_PIN_GROUP(audio_clka),
3759         SH_PFC_PIN_GROUP(audio_clka_b),
3760         SH_PFC_PIN_GROUP(audio_clka_c),
3761         SH_PFC_PIN_GROUP(audio_clka_d),
3762         SH_PFC_PIN_GROUP(audio_clkb),
3763         SH_PFC_PIN_GROUP(audio_clkb_b),
3764         SH_PFC_PIN_GROUP(audio_clkb_c),
3765         SH_PFC_PIN_GROUP(audio_clkc),
3766         SH_PFC_PIN_GROUP(audio_clkc_b),
3767         SH_PFC_PIN_GROUP(audio_clkc_c),
3768         SH_PFC_PIN_GROUP(audio_clkout),
3769         SH_PFC_PIN_GROUP(audio_clkout_b),
3770         SH_PFC_PIN_GROUP(audio_clkout_c),
3771         SH_PFC_PIN_GROUP(avb_link),
3772         SH_PFC_PIN_GROUP(avb_magic),
3773         SH_PFC_PIN_GROUP(avb_phy_int),
3774         SH_PFC_PIN_GROUP(avb_mdio),
3775         SH_PFC_PIN_GROUP(avb_mii),
3776         SH_PFC_PIN_GROUP(avb_gmii),
3777         SH_PFC_PIN_GROUP(can0_data),
3778         SH_PFC_PIN_GROUP(can0_data_b),
3779         SH_PFC_PIN_GROUP(can0_data_c),
3780         SH_PFC_PIN_GROUP(can0_data_d),
3781         SH_PFC_PIN_GROUP(can1_data),
3782         SH_PFC_PIN_GROUP(can1_data_b),
3783         SH_PFC_PIN_GROUP(can1_data_c),
3784         SH_PFC_PIN_GROUP(can1_data_d),
3785         SH_PFC_PIN_GROUP(can_clk),
3786         SH_PFC_PIN_GROUP(can_clk_b),
3787         SH_PFC_PIN_GROUP(can_clk_c),
3788         SH_PFC_PIN_GROUP(can_clk_d),
3789         SH_PFC_PIN_GROUP(du0_rgb666),
3790         SH_PFC_PIN_GROUP(du0_rgb888),
3791         SH_PFC_PIN_GROUP(du0_clk0_out),
3792         SH_PFC_PIN_GROUP(du0_clk1_out),
3793         SH_PFC_PIN_GROUP(du0_clk_in),
3794         SH_PFC_PIN_GROUP(du0_sync),
3795         SH_PFC_PIN_GROUP(du0_oddf),
3796         SH_PFC_PIN_GROUP(du0_cde),
3797         SH_PFC_PIN_GROUP(du0_disp),
3798         SH_PFC_PIN_GROUP(du1_rgb666),
3799         SH_PFC_PIN_GROUP(du1_rgb888),
3800         SH_PFC_PIN_GROUP(du1_clk0_out),
3801         SH_PFC_PIN_GROUP(du1_clk1_out),
3802         SH_PFC_PIN_GROUP(du1_clk_in),
3803         SH_PFC_PIN_GROUP(du1_sync),
3804         SH_PFC_PIN_GROUP(du1_oddf),
3805         SH_PFC_PIN_GROUP(du1_cde),
3806         SH_PFC_PIN_GROUP(du1_disp),
3807         SH_PFC_PIN_GROUP(eth_link),
3808         SH_PFC_PIN_GROUP(eth_magic),
3809         SH_PFC_PIN_GROUP(eth_mdio),
3810         SH_PFC_PIN_GROUP(eth_rmii),
3811         SH_PFC_PIN_GROUP(eth_link_b),
3812         SH_PFC_PIN_GROUP(eth_magic_b),
3813         SH_PFC_PIN_GROUP(eth_mdio_b),
3814         SH_PFC_PIN_GROUP(eth_rmii_b),
3815         SH_PFC_PIN_GROUP(hscif0_data),
3816         SH_PFC_PIN_GROUP(hscif0_clk),
3817         SH_PFC_PIN_GROUP(hscif0_ctrl),
3818         SH_PFC_PIN_GROUP(hscif0_data_b),
3819         SH_PFC_PIN_GROUP(hscif0_clk_b),
3820         SH_PFC_PIN_GROUP(hscif1_data),
3821         SH_PFC_PIN_GROUP(hscif1_clk),
3822         SH_PFC_PIN_GROUP(hscif1_ctrl),
3823         SH_PFC_PIN_GROUP(hscif1_data_b),
3824         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3825         SH_PFC_PIN_GROUP(hscif2_data),
3826         SH_PFC_PIN_GROUP(hscif2_clk),
3827         SH_PFC_PIN_GROUP(hscif2_ctrl),
3828         SH_PFC_PIN_GROUP(i2c0),
3829         SH_PFC_PIN_GROUP(i2c0_b),
3830         SH_PFC_PIN_GROUP(i2c0_c),
3831         SH_PFC_PIN_GROUP(i2c0_d),
3832         SH_PFC_PIN_GROUP(i2c0_e),
3833         SH_PFC_PIN_GROUP(i2c1),
3834         SH_PFC_PIN_GROUP(i2c1_b),
3835         SH_PFC_PIN_GROUP(i2c1_c),
3836         SH_PFC_PIN_GROUP(i2c1_d),
3837         SH_PFC_PIN_GROUP(i2c1_e),
3838         SH_PFC_PIN_GROUP(i2c2),
3839         SH_PFC_PIN_GROUP(i2c2_b),
3840         SH_PFC_PIN_GROUP(i2c2_c),
3841         SH_PFC_PIN_GROUP(i2c2_d),
3842         SH_PFC_PIN_GROUP(i2c2_e),
3843         SH_PFC_PIN_GROUP(i2c3),
3844         SH_PFC_PIN_GROUP(i2c3_b),
3845         SH_PFC_PIN_GROUP(i2c3_c),
3846         SH_PFC_PIN_GROUP(i2c3_d),
3847         SH_PFC_PIN_GROUP(i2c3_e),
3848         SH_PFC_PIN_GROUP(i2c4),
3849         SH_PFC_PIN_GROUP(i2c4_b),
3850         SH_PFC_PIN_GROUP(i2c4_c),
3851         SH_PFC_PIN_GROUP(i2c4_d),
3852         SH_PFC_PIN_GROUP(i2c4_e),
3853         SH_PFC_PIN_GROUP(i2c5),
3854         SH_PFC_PIN_GROUP(i2c5_b),
3855         SH_PFC_PIN_GROUP(i2c5_c),
3856         SH_PFC_PIN_GROUP(i2c5_d),
3857         SH_PFC_PIN_GROUP(intc_irq0),
3858         SH_PFC_PIN_GROUP(intc_irq1),
3859         SH_PFC_PIN_GROUP(intc_irq2),
3860         SH_PFC_PIN_GROUP(intc_irq3),
3861         SH_PFC_PIN_GROUP(intc_irq4),
3862         SH_PFC_PIN_GROUP(intc_irq5),
3863         SH_PFC_PIN_GROUP(intc_irq6),
3864         SH_PFC_PIN_GROUP(intc_irq7),
3865         SH_PFC_PIN_GROUP(intc_irq8),
3866         SH_PFC_PIN_GROUP(intc_irq9),
3867         SH_PFC_PIN_GROUP(mmc_data1),
3868         SH_PFC_PIN_GROUP(mmc_data4),
3869         SH_PFC_PIN_GROUP(mmc_data8),
3870         SH_PFC_PIN_GROUP(mmc_ctrl),
3871         SH_PFC_PIN_GROUP(msiof0_clk),
3872         SH_PFC_PIN_GROUP(msiof0_sync),
3873         SH_PFC_PIN_GROUP(msiof0_ss1),
3874         SH_PFC_PIN_GROUP(msiof0_ss2),
3875         SH_PFC_PIN_GROUP(msiof0_rx),
3876         SH_PFC_PIN_GROUP(msiof0_tx),
3877         SH_PFC_PIN_GROUP(msiof1_clk),
3878         SH_PFC_PIN_GROUP(msiof1_sync),
3879         SH_PFC_PIN_GROUP(msiof1_ss1),
3880         SH_PFC_PIN_GROUP(msiof1_ss2),
3881         SH_PFC_PIN_GROUP(msiof1_rx),
3882         SH_PFC_PIN_GROUP(msiof1_tx),
3883         SH_PFC_PIN_GROUP(msiof1_clk_b),
3884         SH_PFC_PIN_GROUP(msiof1_sync_b),
3885         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3886         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3887         SH_PFC_PIN_GROUP(msiof1_rx_b),
3888         SH_PFC_PIN_GROUP(msiof1_tx_b),
3889         SH_PFC_PIN_GROUP(msiof2_clk),
3890         SH_PFC_PIN_GROUP(msiof2_sync),
3891         SH_PFC_PIN_GROUP(msiof2_ss1),
3892         SH_PFC_PIN_GROUP(msiof2_ss2),
3893         SH_PFC_PIN_GROUP(msiof2_rx),
3894         SH_PFC_PIN_GROUP(msiof2_tx),
3895         SH_PFC_PIN_GROUP(msiof2_clk_b),
3896         SH_PFC_PIN_GROUP(msiof2_sync_b),
3897         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3898         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3899         SH_PFC_PIN_GROUP(msiof2_rx_b),
3900         SH_PFC_PIN_GROUP(msiof2_tx_b),
3901         SH_PFC_PIN_GROUP(pwm0),
3902         SH_PFC_PIN_GROUP(pwm0_b),
3903         SH_PFC_PIN_GROUP(pwm1),
3904         SH_PFC_PIN_GROUP(pwm1_b),
3905         SH_PFC_PIN_GROUP(pwm1_c),
3906         SH_PFC_PIN_GROUP(pwm2),
3907         SH_PFC_PIN_GROUP(pwm2_b),
3908         SH_PFC_PIN_GROUP(pwm2_c),
3909         SH_PFC_PIN_GROUP(pwm3),
3910         SH_PFC_PIN_GROUP(pwm3_b),
3911         SH_PFC_PIN_GROUP(pwm4),
3912         SH_PFC_PIN_GROUP(pwm4_b),
3913         SH_PFC_PIN_GROUP(pwm5),
3914         SH_PFC_PIN_GROUP(pwm5_b),
3915         SH_PFC_PIN_GROUP(pwm5_c),
3916         SH_PFC_PIN_GROUP(pwm6),
3917         SH_PFC_PIN_GROUP(pwm6_b),
3918         SH_PFC_PIN_GROUP(qspi_ctrl),
3919         SH_PFC_PIN_GROUP(qspi_data2),
3920         SH_PFC_PIN_GROUP(qspi_data4),
3921         SH_PFC_PIN_GROUP(scif0_data),
3922         SH_PFC_PIN_GROUP(scif0_data_b),
3923         SH_PFC_PIN_GROUP(scif0_data_c),
3924         SH_PFC_PIN_GROUP(scif0_data_d),
3925         SH_PFC_PIN_GROUP(scif1_data),
3926         SH_PFC_PIN_GROUP(scif1_clk),
3927         SH_PFC_PIN_GROUP(scif1_data_b),
3928         SH_PFC_PIN_GROUP(scif1_clk_b),
3929         SH_PFC_PIN_GROUP(scif1_data_c),
3930         SH_PFC_PIN_GROUP(scif1_clk_c),
3931         SH_PFC_PIN_GROUP(scif2_data),
3932         SH_PFC_PIN_GROUP(scif2_clk),
3933         SH_PFC_PIN_GROUP(scif2_data_b),
3934         SH_PFC_PIN_GROUP(scif2_clk_b),
3935         SH_PFC_PIN_GROUP(scif2_data_c),
3936         SH_PFC_PIN_GROUP(scif2_clk_c),
3937         SH_PFC_PIN_GROUP(scif3_data),
3938         SH_PFC_PIN_GROUP(scif3_clk),
3939         SH_PFC_PIN_GROUP(scif3_data_b),
3940         SH_PFC_PIN_GROUP(scif3_clk_b),
3941         SH_PFC_PIN_GROUP(scif4_data),
3942         SH_PFC_PIN_GROUP(scif4_data_b),
3943         SH_PFC_PIN_GROUP(scif4_data_c),
3944         SH_PFC_PIN_GROUP(scif4_data_d),
3945         SH_PFC_PIN_GROUP(scif4_data_e),
3946         SH_PFC_PIN_GROUP(scif5_data),
3947         SH_PFC_PIN_GROUP(scif5_data_b),
3948         SH_PFC_PIN_GROUP(scif5_data_c),
3949         SH_PFC_PIN_GROUP(scif5_data_d),
3950         SH_PFC_PIN_GROUP(scifa0_data),
3951         SH_PFC_PIN_GROUP(scifa0_data_b),
3952         SH_PFC_PIN_GROUP(scifa0_data_c),
3953         SH_PFC_PIN_GROUP(scifa0_data_d),
3954         SH_PFC_PIN_GROUP(scifa1_data),
3955         SH_PFC_PIN_GROUP(scifa1_clk),
3956         SH_PFC_PIN_GROUP(scifa1_data_b),
3957         SH_PFC_PIN_GROUP(scifa1_clk_b),
3958         SH_PFC_PIN_GROUP(scifa1_data_c),
3959         SH_PFC_PIN_GROUP(scifa1_clk_c),
3960         SH_PFC_PIN_GROUP(scifa2_data),
3961         SH_PFC_PIN_GROUP(scifa2_clk),
3962         SH_PFC_PIN_GROUP(scifa2_data_b),
3963         SH_PFC_PIN_GROUP(scifa2_clk_b),
3964         SH_PFC_PIN_GROUP(scifa3_data),
3965         SH_PFC_PIN_GROUP(scifa3_clk),
3966         SH_PFC_PIN_GROUP(scifa3_data_b),
3967         SH_PFC_PIN_GROUP(scifa3_clk_b),
3968         SH_PFC_PIN_GROUP(scifa4_data),
3969         SH_PFC_PIN_GROUP(scifa4_data_b),
3970         SH_PFC_PIN_GROUP(scifa4_data_c),
3971         SH_PFC_PIN_GROUP(scifa4_data_d),
3972         SH_PFC_PIN_GROUP(scifa5_data),
3973         SH_PFC_PIN_GROUP(scifa5_data_b),
3974         SH_PFC_PIN_GROUP(scifa5_data_c),
3975         SH_PFC_PIN_GROUP(scifa5_data_d),
3976         SH_PFC_PIN_GROUP(scifb0_data),
3977         SH_PFC_PIN_GROUP(scifb0_clk),
3978         SH_PFC_PIN_GROUP(scifb0_ctrl),
3979         SH_PFC_PIN_GROUP(scifb1_data),
3980         SH_PFC_PIN_GROUP(scifb1_clk),
3981         SH_PFC_PIN_GROUP(scifb2_data),
3982         SH_PFC_PIN_GROUP(scifb2_clk),
3983         SH_PFC_PIN_GROUP(scifb2_ctrl),
3984         SH_PFC_PIN_GROUP(scif_clk),
3985         SH_PFC_PIN_GROUP(scif_clk_b),
3986         SH_PFC_PIN_GROUP(sdhi0_data1),
3987         SH_PFC_PIN_GROUP(sdhi0_data4),
3988         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3989         SH_PFC_PIN_GROUP(sdhi0_cd),
3990         SH_PFC_PIN_GROUP(sdhi0_wp),
3991         SH_PFC_PIN_GROUP(sdhi1_data1),
3992         SH_PFC_PIN_GROUP(sdhi1_data4),
3993         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3994         SH_PFC_PIN_GROUP(sdhi1_cd),
3995         SH_PFC_PIN_GROUP(sdhi1_wp),
3996         SH_PFC_PIN_GROUP(sdhi2_data1),
3997         SH_PFC_PIN_GROUP(sdhi2_data4),
3998         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3999         SH_PFC_PIN_GROUP(sdhi2_cd),
4000         SH_PFC_PIN_GROUP(sdhi2_wp),
4001         SH_PFC_PIN_GROUP(ssi0_data),
4002         SH_PFC_PIN_GROUP(ssi0129_ctrl),
4003         SH_PFC_PIN_GROUP(ssi1_data),
4004         SH_PFC_PIN_GROUP(ssi1_ctrl),
4005         SH_PFC_PIN_GROUP(ssi1_data_b),
4006         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4007         SH_PFC_PIN_GROUP(ssi2_data),
4008         SH_PFC_PIN_GROUP(ssi2_ctrl),
4009         SH_PFC_PIN_GROUP(ssi2_data_b),
4010         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4011         SH_PFC_PIN_GROUP(ssi3_data),
4012         SH_PFC_PIN_GROUP(ssi34_ctrl),
4013         SH_PFC_PIN_GROUP(ssi4_data),
4014         SH_PFC_PIN_GROUP(ssi4_ctrl),
4015         SH_PFC_PIN_GROUP(ssi4_data_b),
4016         SH_PFC_PIN_GROUP(ssi4_ctrl_b),
4017         SH_PFC_PIN_GROUP(ssi5_data),
4018         SH_PFC_PIN_GROUP(ssi5_ctrl),
4019         SH_PFC_PIN_GROUP(ssi5_data_b),
4020         SH_PFC_PIN_GROUP(ssi5_ctrl_b),
4021         SH_PFC_PIN_GROUP(ssi6_data),
4022         SH_PFC_PIN_GROUP(ssi6_ctrl),
4023         SH_PFC_PIN_GROUP(ssi6_data_b),
4024         SH_PFC_PIN_GROUP(ssi6_ctrl_b),
4025         SH_PFC_PIN_GROUP(ssi7_data),
4026         SH_PFC_PIN_GROUP(ssi78_ctrl),
4027         SH_PFC_PIN_GROUP(ssi7_data_b),
4028         SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4029         SH_PFC_PIN_GROUP(ssi8_data),
4030         SH_PFC_PIN_GROUP(ssi8_data_b),
4031         SH_PFC_PIN_GROUP(ssi9_data),
4032         SH_PFC_PIN_GROUP(ssi9_ctrl),
4033         SH_PFC_PIN_GROUP(ssi9_data_b),
4034         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4035         SH_PFC_PIN_GROUP(tpu_to0),
4036         SH_PFC_PIN_GROUP(tpu_to0_b),
4037         SH_PFC_PIN_GROUP(tpu_to0_c),
4038         SH_PFC_PIN_GROUP(tpu_to1),
4039         SH_PFC_PIN_GROUP(tpu_to1_b),
4040         SH_PFC_PIN_GROUP(tpu_to1_c),
4041         SH_PFC_PIN_GROUP(tpu_to2),
4042         SH_PFC_PIN_GROUP(tpu_to2_b),
4043         SH_PFC_PIN_GROUP(tpu_to2_c),
4044         SH_PFC_PIN_GROUP(tpu_to3),
4045         SH_PFC_PIN_GROUP(tpu_to3_b),
4046         SH_PFC_PIN_GROUP(tpu_to3_c),
4047         SH_PFC_PIN_GROUP(usb0),
4048         SH_PFC_PIN_GROUP(usb1),
4049         VIN_DATA_PIN_GROUP(vin0_data, 24),
4050         VIN_DATA_PIN_GROUP(vin0_data, 20),
4051         SH_PFC_PIN_GROUP(vin0_data18),
4052         VIN_DATA_PIN_GROUP(vin0_data, 16),
4053         VIN_DATA_PIN_GROUP(vin0_data, 12),
4054         VIN_DATA_PIN_GROUP(vin0_data, 10),
4055         VIN_DATA_PIN_GROUP(vin0_data, 8),
4056         SH_PFC_PIN_GROUP(vin0_sync),
4057         SH_PFC_PIN_GROUP(vin0_field),
4058         SH_PFC_PIN_GROUP(vin0_clkenb),
4059         SH_PFC_PIN_GROUP(vin0_clk),
4060         VIN_DATA_PIN_GROUP(vin1_data, 12),
4061         VIN_DATA_PIN_GROUP(vin1_data, 10),
4062         VIN_DATA_PIN_GROUP(vin1_data, 8),
4063         SH_PFC_PIN_GROUP(vin1_sync),
4064         SH_PFC_PIN_GROUP(vin1_field),
4065         SH_PFC_PIN_GROUP(vin1_clkenb),
4066         SH_PFC_PIN_GROUP(vin1_clk),
4067 };
4068
4069 static const char * const audio_clk_groups[] = {
4070         "audio_clka",
4071         "audio_clka_b",
4072         "audio_clka_c",
4073         "audio_clka_d",
4074         "audio_clkb",
4075         "audio_clkb_b",
4076         "audio_clkb_c",
4077         "audio_clkc",
4078         "audio_clkc_b",
4079         "audio_clkc_c",
4080         "audio_clkout",
4081         "audio_clkout_b",
4082         "audio_clkout_c",
4083 };
4084
4085 static const char * const avb_groups[] = {
4086         "avb_link",
4087         "avb_magic",
4088         "avb_phy_int",
4089         "avb_mdio",
4090         "avb_mii",
4091         "avb_gmii",
4092 };
4093
4094 static const char * const can0_groups[] = {
4095         "can0_data",
4096         "can0_data_b",
4097         "can0_data_c",
4098         "can0_data_d",
4099         /*
4100          * Retained for backwards compatibility, use can_clk_groups in new
4101          * designs.
4102          */
4103         "can_clk",
4104         "can_clk_b",
4105         "can_clk_c",
4106         "can_clk_d",
4107 };
4108
4109 static const char * const can1_groups[] = {
4110         "can1_data",
4111         "can1_data_b",
4112         "can1_data_c",
4113         "can1_data_d",
4114         /*
4115          * Retained for backwards compatibility, use can_clk_groups in new
4116          * designs.
4117          */
4118         "can_clk",
4119         "can_clk_b",
4120         "can_clk_c",
4121         "can_clk_d",
4122 };
4123
4124 /*
4125  * can_clk_groups allows for independent configuration, use can_clk function
4126  * in new designs.
4127  */
4128 static const char * const can_clk_groups[] = {
4129         "can_clk",
4130         "can_clk_b",
4131         "can_clk_c",
4132         "can_clk_d",
4133 };
4134
4135 static const char * const du0_groups[] = {
4136         "du0_rgb666",
4137         "du0_rgb888",
4138         "du0_clk0_out",
4139         "du0_clk1_out",
4140         "du0_clk_in",
4141         "du0_sync",
4142         "du0_oddf",
4143         "du0_cde",
4144         "du0_disp",
4145 };
4146
4147 static const char * const du1_groups[] = {
4148         "du1_rgb666",
4149         "du1_rgb888",
4150         "du1_clk0_out",
4151         "du1_clk1_out",
4152         "du1_clk_in",
4153         "du1_sync",
4154         "du1_oddf",
4155         "du1_cde",
4156         "du1_disp",
4157 };
4158
4159 static const char * const eth_groups[] = {
4160         "eth_link",
4161         "eth_magic",
4162         "eth_mdio",
4163         "eth_rmii",
4164         "eth_link_b",
4165         "eth_magic_b",
4166         "eth_mdio_b",
4167         "eth_rmii_b",
4168 };
4169
4170 static const char * const hscif0_groups[] = {
4171         "hscif0_data",
4172         "hscif0_clk",
4173         "hscif0_ctrl",
4174         "hscif0_data_b",
4175         "hscif0_clk_b",
4176 };
4177
4178 static const char * const hscif1_groups[] = {
4179         "hscif1_data",
4180         "hscif1_clk",
4181         "hscif1_ctrl",
4182         "hscif1_data_b",
4183         "hscif1_ctrl_b",
4184 };
4185
4186 static const char * const hscif2_groups[] = {
4187         "hscif2_data",
4188         "hscif2_clk",
4189         "hscif2_ctrl",
4190 };
4191
4192 static const char * const i2c0_groups[] = {
4193         "i2c0",
4194         "i2c0_b",
4195         "i2c0_c",
4196         "i2c0_d",
4197         "i2c0_e",
4198 };
4199
4200 static const char * const i2c1_groups[] = {
4201         "i2c1",
4202         "i2c1_b",
4203         "i2c1_c",
4204         "i2c1_d",
4205         "i2c1_e",
4206 };
4207
4208 static const char * const i2c2_groups[] = {
4209         "i2c2",
4210         "i2c2_b",
4211         "i2c2_c",
4212         "i2c2_d",
4213         "i2c2_e",
4214 };
4215
4216 static const char * const i2c3_groups[] = {
4217         "i2c3",
4218         "i2c3_b",
4219         "i2c3_c",
4220         "i2c3_d",
4221         "i2c3_e",
4222 };
4223
4224 static const char * const i2c4_groups[] = {
4225         "i2c4",
4226         "i2c4_b",
4227         "i2c4_c",
4228         "i2c4_d",
4229         "i2c4_e",
4230 };
4231
4232 static const char * const i2c5_groups[] = {
4233         "i2c5",
4234         "i2c5_b",
4235         "i2c5_c",
4236         "i2c5_d",
4237 };
4238
4239 static const char * const intc_groups[] = {
4240         "intc_irq0",
4241         "intc_irq1",
4242         "intc_irq2",
4243         "intc_irq3",
4244         "intc_irq4",
4245         "intc_irq5",
4246         "intc_irq6",
4247         "intc_irq7",
4248         "intc_irq8",
4249         "intc_irq9",
4250 };
4251
4252 static const char * const mmc_groups[] = {
4253         "mmc_data1",
4254         "mmc_data4",
4255         "mmc_data8",
4256         "mmc_ctrl",
4257 };
4258
4259 static const char * const msiof0_groups[] = {
4260         "msiof0_clk",
4261         "msiof0_sync",
4262         "msiof0_ss1",
4263         "msiof0_ss2",
4264         "msiof0_rx",
4265         "msiof0_tx",
4266 };
4267
4268 static const char * const msiof1_groups[] = {
4269         "msiof1_clk",
4270         "msiof1_sync",
4271         "msiof1_ss1",
4272         "msiof1_ss2",
4273         "msiof1_rx",
4274         "msiof1_tx",
4275         "msiof1_clk_b",
4276         "msiof1_sync_b",
4277         "msiof1_ss1_b",
4278         "msiof1_ss2_b",
4279         "msiof1_rx_b",
4280         "msiof1_tx_b",
4281 };
4282
4283 static const char * const msiof2_groups[] = {
4284         "msiof2_clk",
4285         "msiof2_sync",
4286         "msiof2_ss1",
4287         "msiof2_ss2",
4288         "msiof2_rx",
4289         "msiof2_tx",
4290         "msiof2_clk_b",
4291         "msiof2_sync_b",
4292         "msiof2_ss1_b",
4293         "msiof2_ss2_b",
4294         "msiof2_rx_b",
4295         "msiof2_tx_b",
4296 };
4297
4298 static const char * const pwm0_groups[] = {
4299         "pwm0",
4300         "pwm0_b",
4301 };
4302
4303 static const char * const pwm1_groups[] = {
4304         "pwm1",
4305         "pwm1_b",
4306         "pwm1_c",
4307 };
4308
4309 static const char * const pwm2_groups[] = {
4310         "pwm2",
4311         "pwm2_b",
4312         "pwm2_c",
4313 };
4314
4315 static const char * const pwm3_groups[] = {
4316         "pwm3",
4317         "pwm3_b",
4318 };
4319
4320 static const char * const pwm4_groups[] = {
4321         "pwm4",
4322         "pwm4_b",
4323 };
4324
4325 static const char * const pwm5_groups[] = {
4326         "pwm5",
4327         "pwm5_b",
4328         "pwm5_c",
4329 };
4330
4331 static const char * const pwm6_groups[] = {
4332         "pwm6",
4333         "pwm6_b",
4334 };
4335
4336 static const char * const qspi_groups[] = {
4337         "qspi_ctrl",
4338         "qspi_data2",
4339         "qspi_data4",
4340 };
4341
4342 static const char * const scif0_groups[] = {
4343         "scif0_data",
4344         "scif0_data_b",
4345         "scif0_data_c",
4346         "scif0_data_d",
4347 };
4348
4349 static const char * const scif1_groups[] = {
4350         "scif1_data",
4351         "scif1_clk",
4352         "scif1_data_b",
4353         "scif1_clk_b",
4354         "scif1_data_c",
4355         "scif1_clk_c",
4356 };
4357
4358 static const char * const scif2_groups[] = {
4359         "scif2_data",
4360         "scif2_clk",
4361         "scif2_data_b",
4362         "scif2_clk_b",
4363         "scif2_data_c",
4364         "scif2_clk_c",
4365 };
4366
4367 static const char * const scif3_groups[] = {
4368         "scif3_data",
4369         "scif3_clk",
4370         "scif3_data_b",
4371         "scif3_clk_b",
4372 };
4373
4374 static const char * const scif4_groups[] = {
4375         "scif4_data",
4376         "scif4_data_b",
4377         "scif4_data_c",
4378         "scif4_data_d",
4379         "scif4_data_e",
4380 };
4381
4382 static const char * const scif5_groups[] = {
4383         "scif5_data",
4384         "scif5_data_b",
4385         "scif5_data_c",
4386         "scif5_data_d",
4387 };
4388
4389 static const char * const scifa0_groups[] = {
4390         "scifa0_data",
4391         "scifa0_data_b",
4392         "scifa0_data_c",
4393         "scifa0_data_d",
4394 };
4395
4396 static const char * const scifa1_groups[] = {
4397         "scifa1_data",
4398         "scifa1_clk",
4399         "scifa1_data_b",
4400         "scifa1_clk_b",
4401         "scifa1_data_c",
4402         "scifa1_clk_c",
4403 };
4404
4405 static const char * const scifa2_groups[] = {
4406         "scifa2_data",
4407         "scifa2_clk",
4408         "scifa2_data_b",
4409         "scifa2_clk_b",
4410 };
4411
4412 static const char * const scifa3_groups[] = {
4413         "scifa3_data",
4414         "scifa3_clk",
4415         "scifa3_data_b",
4416         "scifa3_clk_b",
4417 };
4418
4419 static const char * const scifa4_groups[] = {
4420         "scifa4_data",
4421         "scifa4_data_b",
4422         "scifa4_data_c",
4423         "scifa4_data_d",
4424 };
4425
4426 static const char * const scifa5_groups[] = {
4427         "scifa5_data",
4428         "scifa5_data_b",
4429         "scifa5_data_c",
4430         "scifa5_data_d",
4431 };
4432
4433 static const char * const scifb0_groups[] = {
4434         "scifb0_data",
4435         "scifb0_clk",
4436         "scifb0_ctrl",
4437 };
4438
4439 static const char * const scifb1_groups[] = {
4440         "scifb1_data",
4441         "scifb1_clk",
4442 };
4443
4444 static const char * const scifb2_groups[] = {
4445         "scifb2_data",
4446         "scifb2_clk",
4447         "scifb2_ctrl",
4448 };
4449
4450 static const char * const scif_clk_groups[] = {
4451         "scif_clk",
4452         "scif_clk_b",
4453 };
4454
4455 static const char * const sdhi0_groups[] = {
4456         "sdhi0_data1",
4457         "sdhi0_data4",
4458         "sdhi0_ctrl",
4459         "sdhi0_cd",
4460         "sdhi0_wp",
4461 };
4462
4463 static const char * const sdhi1_groups[] = {
4464         "sdhi1_data1",
4465         "sdhi1_data4",
4466         "sdhi1_ctrl",
4467         "sdhi1_cd",
4468         "sdhi1_wp",
4469 };
4470
4471 static const char * const sdhi2_groups[] = {
4472         "sdhi2_data1",
4473         "sdhi2_data4",
4474         "sdhi2_ctrl",
4475         "sdhi2_cd",
4476         "sdhi2_wp",
4477 };
4478
4479 static const char * const ssi_groups[] = {
4480         "ssi0_data",
4481         "ssi0129_ctrl",
4482         "ssi1_data",
4483         "ssi1_ctrl",
4484         "ssi1_data_b",
4485         "ssi1_ctrl_b",
4486         "ssi2_data",
4487         "ssi2_ctrl",
4488         "ssi2_data_b",
4489         "ssi2_ctrl_b",
4490         "ssi3_data",
4491         "ssi34_ctrl",
4492         "ssi4_data",
4493         "ssi4_ctrl",
4494         "ssi4_data_b",
4495         "ssi4_ctrl_b",
4496         "ssi5_data",
4497         "ssi5_ctrl",
4498         "ssi5_data_b",
4499         "ssi5_ctrl_b",
4500         "ssi6_data",
4501         "ssi6_ctrl",
4502         "ssi6_data_b",
4503         "ssi6_ctrl_b",
4504         "ssi7_data",
4505         "ssi78_ctrl",
4506         "ssi7_data_b",
4507         "ssi78_ctrl_b",
4508         "ssi8_data",
4509         "ssi8_data_b",
4510         "ssi9_data",
4511         "ssi9_ctrl",
4512         "ssi9_data_b",
4513         "ssi9_ctrl_b",
4514 };
4515
4516 static const char * const tpu_groups[] = {
4517         "tpu_to0",
4518         "tpu_to0_b",
4519         "tpu_to0_c",
4520         "tpu_to1",
4521         "tpu_to1_b",
4522         "tpu_to1_c",
4523         "tpu_to2",
4524         "tpu_to2_b",
4525         "tpu_to2_c",
4526         "tpu_to3",
4527         "tpu_to3_b",
4528         "tpu_to3_c",
4529 };
4530
4531 static const char * const usb0_groups[] = {
4532         "usb0",
4533 };
4534
4535 static const char * const usb1_groups[] = {
4536         "usb1",
4537 };
4538
4539 static const char * const vin0_groups[] = {
4540         "vin0_data24",
4541         "vin0_data20",
4542         "vin0_data18",
4543         "vin0_data16",
4544         "vin0_data12",
4545         "vin0_data10",
4546         "vin0_data8",
4547         "vin0_sync",
4548         "vin0_field",
4549         "vin0_clkenb",
4550         "vin0_clk",
4551 };
4552
4553 static const char * const vin1_groups[] = {
4554         "vin1_data12",
4555         "vin1_data10",
4556         "vin1_data8",
4557         "vin1_sync",
4558         "vin1_field",
4559         "vin1_clkenb",
4560         "vin1_clk",
4561 };
4562
4563 static const struct sh_pfc_function pinmux_functions[] = {
4564         SH_PFC_FUNCTION(audio_clk),
4565         SH_PFC_FUNCTION(avb),
4566         SH_PFC_FUNCTION(can0),
4567         SH_PFC_FUNCTION(can1),
4568         SH_PFC_FUNCTION(can_clk),
4569         SH_PFC_FUNCTION(du0),
4570         SH_PFC_FUNCTION(du1),
4571         SH_PFC_FUNCTION(eth),
4572         SH_PFC_FUNCTION(hscif0),
4573         SH_PFC_FUNCTION(hscif1),
4574         SH_PFC_FUNCTION(hscif2),
4575         SH_PFC_FUNCTION(i2c0),
4576         SH_PFC_FUNCTION(i2c1),
4577         SH_PFC_FUNCTION(i2c2),
4578         SH_PFC_FUNCTION(i2c3),
4579         SH_PFC_FUNCTION(i2c4),
4580         SH_PFC_FUNCTION(i2c5),
4581         SH_PFC_FUNCTION(intc),
4582         SH_PFC_FUNCTION(mmc),
4583         SH_PFC_FUNCTION(msiof0),
4584         SH_PFC_FUNCTION(msiof1),
4585         SH_PFC_FUNCTION(msiof2),
4586         SH_PFC_FUNCTION(pwm0),
4587         SH_PFC_FUNCTION(pwm1),
4588         SH_PFC_FUNCTION(pwm2),
4589         SH_PFC_FUNCTION(pwm3),
4590         SH_PFC_FUNCTION(pwm4),
4591         SH_PFC_FUNCTION(pwm5),
4592         SH_PFC_FUNCTION(pwm6),
4593         SH_PFC_FUNCTION(qspi),
4594         SH_PFC_FUNCTION(scif0),
4595         SH_PFC_FUNCTION(scif1),
4596         SH_PFC_FUNCTION(scif2),
4597         SH_PFC_FUNCTION(scif3),
4598         SH_PFC_FUNCTION(scif4),
4599         SH_PFC_FUNCTION(scif5),
4600         SH_PFC_FUNCTION(scifa0),
4601         SH_PFC_FUNCTION(scifa1),
4602         SH_PFC_FUNCTION(scifa2),
4603         SH_PFC_FUNCTION(scifa3),
4604         SH_PFC_FUNCTION(scifa4),
4605         SH_PFC_FUNCTION(scifa5),
4606         SH_PFC_FUNCTION(scifb0),
4607         SH_PFC_FUNCTION(scifb1),
4608         SH_PFC_FUNCTION(scifb2),
4609         SH_PFC_FUNCTION(scif_clk),
4610         SH_PFC_FUNCTION(sdhi0),
4611         SH_PFC_FUNCTION(sdhi1),
4612         SH_PFC_FUNCTION(sdhi2),
4613         SH_PFC_FUNCTION(ssi),
4614         SH_PFC_FUNCTION(tpu),
4615         SH_PFC_FUNCTION(usb0),
4616         SH_PFC_FUNCTION(usb1),
4617         SH_PFC_FUNCTION(vin0),
4618         SH_PFC_FUNCTION(vin1),
4619 };
4620
4621 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4622         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4623                 GP_0_31_FN, FN_IP2_17_16,
4624                 GP_0_30_FN, FN_IP2_15_14,
4625                 GP_0_29_FN, FN_IP2_13_12,
4626                 GP_0_28_FN, FN_IP2_11_10,
4627                 GP_0_27_FN, FN_IP2_9_8,
4628                 GP_0_26_FN, FN_IP2_7_6,
4629                 GP_0_25_FN, FN_IP2_5_4,
4630                 GP_0_24_FN, FN_IP2_3_2,
4631                 GP_0_23_FN, FN_IP2_1_0,
4632                 GP_0_22_FN, FN_IP1_31_30,
4633                 GP_0_21_FN, FN_IP1_29_28,
4634                 GP_0_20_FN, FN_IP1_27,
4635                 GP_0_19_FN, FN_IP1_26,
4636                 GP_0_18_FN, FN_A2,
4637                 GP_0_17_FN, FN_IP1_24,
4638                 GP_0_16_FN, FN_IP1_23_22,
4639                 GP_0_15_FN, FN_IP1_21_20,
4640                 GP_0_14_FN, FN_IP1_19_18,
4641                 GP_0_13_FN, FN_IP1_17_15,
4642                 GP_0_12_FN, FN_IP1_14_13,
4643                 GP_0_11_FN, FN_IP1_12_11,
4644                 GP_0_10_FN, FN_IP1_10_8,
4645                 GP_0_9_FN, FN_IP1_7_6,
4646                 GP_0_8_FN, FN_IP1_5_4,
4647                 GP_0_7_FN, FN_IP1_3_2,
4648                 GP_0_6_FN, FN_IP1_1_0,
4649                 GP_0_5_FN, FN_IP0_31_30,
4650                 GP_0_4_FN, FN_IP0_29_28,
4651                 GP_0_3_FN, FN_IP0_27_26,
4652                 GP_0_2_FN, FN_IP0_25,
4653                 GP_0_1_FN, FN_IP0_24,
4654                 GP_0_0_FN, FN_IP0_23_22, ))
4655         },
4656         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4657                 0, 0,
4658                 0, 0,
4659                 0, 0,
4660                 0, 0,
4661                 0, 0,
4662                 0, 0,
4663                 GP_1_25_FN, FN_DACK0,
4664                 GP_1_24_FN, FN_IP7_31,
4665                 GP_1_23_FN, FN_IP4_1_0,
4666                 GP_1_22_FN, FN_WE1_N,
4667                 GP_1_21_FN, FN_WE0_N,
4668                 GP_1_20_FN, FN_IP3_31,
4669                 GP_1_19_FN, FN_IP3_30,
4670                 GP_1_18_FN, FN_IP3_29_27,
4671                 GP_1_17_FN, FN_IP3_26_24,
4672                 GP_1_16_FN, FN_IP3_23_21,
4673                 GP_1_15_FN, FN_IP3_20_18,
4674                 GP_1_14_FN, FN_IP3_17_15,
4675                 GP_1_13_FN, FN_IP3_14_13,
4676                 GP_1_12_FN, FN_IP3_12,
4677                 GP_1_11_FN, FN_IP3_11,
4678                 GP_1_10_FN, FN_IP3_10,
4679                 GP_1_9_FN, FN_IP3_9_8,
4680                 GP_1_8_FN, FN_IP3_7_6,
4681                 GP_1_7_FN, FN_IP3_5_4,
4682                 GP_1_6_FN, FN_IP3_3_2,
4683                 GP_1_5_FN, FN_IP3_1_0,
4684                 GP_1_4_FN, FN_IP2_31_30,
4685                 GP_1_3_FN, FN_IP2_29_27,
4686                 GP_1_2_FN, FN_IP2_26_24,
4687                 GP_1_1_FN, FN_IP2_23_21,
4688                 GP_1_0_FN, FN_IP2_20_18, ))
4689         },
4690         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4691                 GP_2_31_FN, FN_IP6_7_6,
4692                 GP_2_30_FN, FN_IP6_5_4,
4693                 GP_2_29_FN, FN_IP6_3_2,
4694                 GP_2_28_FN, FN_IP6_1_0,
4695                 GP_2_27_FN, FN_IP5_31_30,
4696                 GP_2_26_FN, FN_IP5_29_28,
4697                 GP_2_25_FN, FN_IP5_27_26,
4698                 GP_2_24_FN, FN_IP5_25_24,
4699                 GP_2_23_FN, FN_IP5_23_22,
4700                 GP_2_22_FN, FN_IP5_21_20,
4701                 GP_2_21_FN, FN_IP5_19_18,
4702                 GP_2_20_FN, FN_IP5_17_16,
4703                 GP_2_19_FN, FN_IP5_15_14,
4704                 GP_2_18_FN, FN_IP5_13_12,
4705                 GP_2_17_FN, FN_IP5_11_9,
4706                 GP_2_16_FN, FN_IP5_8_6,
4707                 GP_2_15_FN, FN_IP5_5_4,
4708                 GP_2_14_FN, FN_IP5_3_2,
4709                 GP_2_13_FN, FN_IP5_1_0,
4710                 GP_2_12_FN, FN_IP4_31_30,
4711                 GP_2_11_FN, FN_IP4_29_28,
4712                 GP_2_10_FN, FN_IP4_27_26,
4713                 GP_2_9_FN, FN_IP4_25_23,
4714                 GP_2_8_FN, FN_IP4_22_20,
4715                 GP_2_7_FN, FN_IP4_19_18,
4716                 GP_2_6_FN, FN_IP4_17_16,
4717                 GP_2_5_FN, FN_IP4_15_14,
4718                 GP_2_4_FN, FN_IP4_13_12,
4719                 GP_2_3_FN, FN_IP4_11_10,
4720                 GP_2_2_FN, FN_IP4_9_8,
4721                 GP_2_1_FN, FN_IP4_7_5,
4722                 GP_2_0_FN, FN_IP4_4_2 ))
4723         },
4724         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
4725                 GP_3_31_FN, FN_IP8_22_20,
4726                 GP_3_30_FN, FN_IP8_19_17,
4727                 GP_3_29_FN, FN_IP8_16_15,
4728                 GP_3_28_FN, FN_IP8_14_12,
4729                 GP_3_27_FN, FN_IP8_11_9,
4730                 GP_3_26_FN, FN_IP8_8_6,
4731                 GP_3_25_FN, FN_IP8_5_3,
4732                 GP_3_24_FN, FN_IP8_2_0,
4733                 GP_3_23_FN, FN_IP7_29_27,
4734                 GP_3_22_FN, FN_IP7_26_24,
4735                 GP_3_21_FN, FN_IP7_23_21,
4736                 GP_3_20_FN, FN_IP7_20_18,
4737                 GP_3_19_FN, FN_IP7_17_15,
4738                 GP_3_18_FN, FN_IP7_14_12,
4739                 GP_3_17_FN, FN_IP7_11_9,
4740                 GP_3_16_FN, FN_IP7_8_6,
4741                 GP_3_15_FN, FN_IP7_5_3,
4742                 GP_3_14_FN, FN_IP7_2_0,
4743                 GP_3_13_FN, FN_IP6_31_29,
4744                 GP_3_12_FN, FN_IP6_28_26,
4745                 GP_3_11_FN, FN_IP6_25_23,
4746                 GP_3_10_FN, FN_IP6_22_20,
4747                 GP_3_9_FN, FN_IP6_19_17,
4748                 GP_3_8_FN, FN_IP6_16,
4749                 GP_3_7_FN, FN_IP6_15,
4750                 GP_3_6_FN, FN_IP6_14,
4751                 GP_3_5_FN, FN_IP6_13,
4752                 GP_3_4_FN, FN_IP6_12,
4753                 GP_3_3_FN, FN_IP6_11,
4754                 GP_3_2_FN, FN_IP6_10,
4755                 GP_3_1_FN, FN_IP6_9,
4756                 GP_3_0_FN, FN_IP6_8 ))
4757         },
4758         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
4759                 GP_4_31_FN, FN_IP11_17_16,
4760                 GP_4_30_FN, FN_IP11_15_14,
4761                 GP_4_29_FN, FN_IP11_13_11,
4762                 GP_4_28_FN, FN_IP11_10_8,
4763                 GP_4_27_FN, FN_IP11_7_6,
4764                 GP_4_26_FN, FN_IP11_5_3,
4765                 GP_4_25_FN, FN_IP11_2_0,
4766                 GP_4_24_FN, FN_IP10_31_30,
4767                 GP_4_23_FN, FN_IP10_29_27,
4768                 GP_4_22_FN, FN_IP10_26_24,
4769                 GP_4_21_FN, FN_IP10_23_21,
4770                 GP_4_20_FN, FN_IP10_20_18,
4771                 GP_4_19_FN, FN_IP10_17_15,
4772                 GP_4_18_FN, FN_IP10_14_12,
4773                 GP_4_17_FN, FN_IP10_11_9,
4774                 GP_4_16_FN, FN_IP10_8_6,
4775                 GP_4_15_FN, FN_IP10_5_3,
4776                 GP_4_14_FN, FN_IP10_2_0,
4777                 GP_4_13_FN, FN_IP9_30_28,
4778                 GP_4_12_FN, FN_IP9_27_25,
4779                 GP_4_11_FN, FN_IP9_24_22,
4780                 GP_4_10_FN, FN_IP9_21_19,
4781                 GP_4_9_FN, FN_IP9_18_17,
4782                 GP_4_8_FN, FN_IP9_16_15,
4783                 GP_4_7_FN, FN_IP9_14_12,
4784                 GP_4_6_FN, FN_IP9_11_9,
4785                 GP_4_5_FN, FN_IP9_8_6,
4786                 GP_4_4_FN, FN_IP9_5_3,
4787                 GP_4_3_FN, FN_IP9_2_0,
4788                 GP_4_2_FN, FN_IP8_31_29,
4789                 GP_4_1_FN, FN_IP8_28_26,
4790                 GP_4_0_FN, FN_IP8_25_23 ))
4791         },
4792         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
4793                 0, 0,
4794                 0, 0,
4795                 0, 0,
4796                 0, 0,
4797                 GP_5_27_FN, FN_USB1_OVC,
4798                 GP_5_26_FN, FN_USB1_PWEN,
4799                 GP_5_25_FN, FN_USB0_OVC,
4800                 GP_5_24_FN, FN_USB0_PWEN,
4801                 GP_5_23_FN, FN_IP13_26_24,
4802                 GP_5_22_FN, FN_IP13_23_21,
4803                 GP_5_21_FN, FN_IP13_20_18,
4804                 GP_5_20_FN, FN_IP13_17_15,
4805                 GP_5_19_FN, FN_IP13_14_12,
4806                 GP_5_18_FN, FN_IP13_11_9,
4807                 GP_5_17_FN, FN_IP13_8_6,
4808                 GP_5_16_FN, FN_IP13_5_3,
4809                 GP_5_15_FN, FN_IP13_2_0,
4810                 GP_5_14_FN, FN_IP12_29_27,
4811                 GP_5_13_FN, FN_IP12_26_24,
4812                 GP_5_12_FN, FN_IP12_23_21,
4813                 GP_5_11_FN, FN_IP12_20_18,
4814                 GP_5_10_FN, FN_IP12_17_15,
4815                 GP_5_9_FN, FN_IP12_14_13,
4816                 GP_5_8_FN, FN_IP12_12_11,
4817                 GP_5_7_FN, FN_IP12_10_9,
4818                 GP_5_6_FN, FN_IP12_8_6,
4819                 GP_5_5_FN, FN_IP12_5_3,
4820                 GP_5_4_FN, FN_IP12_2_0,
4821                 GP_5_3_FN, FN_IP11_29_27,
4822                 GP_5_2_FN, FN_IP11_26_24,
4823                 GP_5_1_FN, FN_IP11_23_21,
4824                 GP_5_0_FN, FN_IP11_20_18 ))
4825         },
4826         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
4827                 0, 0,
4828                 0, 0,
4829                 0, 0,
4830                 0, 0,
4831                 0, 0,
4832                 0, 0,
4833                 GP_6_25_FN, FN_IP0_21_20,
4834                 GP_6_24_FN, FN_IP0_19_18,
4835                 GP_6_23_FN, FN_IP0_17,
4836                 GP_6_22_FN, FN_IP0_16,
4837                 GP_6_21_FN, FN_IP0_15,
4838                 GP_6_20_FN, FN_IP0_14,
4839                 GP_6_19_FN, FN_IP0_13,
4840                 GP_6_18_FN, FN_IP0_12,
4841                 GP_6_17_FN, FN_IP0_11,
4842                 GP_6_16_FN, FN_IP0_10,
4843                 GP_6_15_FN, FN_IP0_9_8,
4844                 GP_6_14_FN, FN_IP0_0,
4845                 GP_6_13_FN, FN_SD1_DATA3,
4846                 GP_6_12_FN, FN_SD1_DATA2,
4847                 GP_6_11_FN, FN_SD1_DATA1,
4848                 GP_6_10_FN, FN_SD1_DATA0,
4849                 GP_6_9_FN, FN_SD1_CMD,
4850                 GP_6_8_FN, FN_SD1_CLK,
4851                 GP_6_7_FN, FN_SD0_WP,
4852                 GP_6_6_FN, FN_SD0_CD,
4853                 GP_6_5_FN, FN_SD0_DATA3,
4854                 GP_6_4_FN, FN_SD0_DATA2,
4855                 GP_6_3_FN, FN_SD0_DATA1,
4856                 GP_6_2_FN, FN_SD0_DATA0,
4857                 GP_6_1_FN, FN_SD0_CMD,
4858                 GP_6_0_FN, FN_SD0_CLK ))
4859         },
4860         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4861                              GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
4862                                    1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
4863                              GROUP(
4864                 /* IP0_31_30 [2] */
4865                 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4866                 /* IP0_29_28 [2] */
4867                 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
4868                 /* IP0_27_26 [2] */
4869                 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
4870                 /* IP0_25 [1] */
4871                 FN_D2, FN_SCIFA3_TXD_B,
4872                 /* IP0_24 [1] */
4873                 FN_D1, FN_SCIFA3_RXD_B,
4874                 /* IP0_23_22 [2] */
4875                 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
4876                 /* IP0_21_20 [2] */
4877                 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
4878                 /* IP0_19_18 [2] */
4879                 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
4880                 /* IP0_17 [1] */
4881                 FN_MMC_D5, FN_SD2_WP,
4882                 /* IP0_16 [1] */
4883                 FN_MMC_D4, FN_SD2_CD,
4884                 /* IP0_15 [1] */
4885                 FN_MMC_D3, FN_SD2_DATA3,
4886                 /* IP0_14 [1] */
4887                 FN_MMC_D2, FN_SD2_DATA2,
4888                 /* IP0_13 [1] */
4889                 FN_MMC_D1, FN_SD2_DATA1,
4890                 /* IP0_12 [1] */
4891                 FN_MMC_D0, FN_SD2_DATA0,
4892                 /* IP0_11 [1] */
4893                 FN_MMC_CMD, FN_SD2_CMD,
4894                 /* IP0_10 [1] */
4895                 FN_MMC_CLK, FN_SD2_CLK,
4896                 /* IP0_9_8 [2] */
4897                 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
4898                 /* IP0_7 [1] */
4899                 0, 0,
4900                 /* IP0_6 [1] */
4901                 0, 0,
4902                 /* IP0_5 [1] */
4903                 0, 0,
4904                 /* IP0_4 [1] */
4905                 0, 0,
4906                 /* IP0_3 [1] */
4907                 0, 0,
4908                 /* IP0_2 [1] */
4909                 0, 0,
4910                 /* IP0_1 [1] */
4911                 0, 0,
4912                 /* IP0_0 [1] */
4913                 FN_SD1_CD, FN_CAN0_RX, ))
4914         },
4915         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4916                              GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
4917                                    3, 2, 2, 2, 2),
4918                              GROUP(
4919                 /* IP1_31_30 [2] */
4920                 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
4921                 /* IP1_29_28 [2] */
4922                 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
4923                 /* IP1_27 [1] */
4924                 FN_A4, FN_SCIFB0_TXD,
4925                 /* IP1_26 [1] */
4926                 FN_A3, FN_SCIFB0_SCK,
4927                 /* IP1_25 [1] */
4928                 0, 0,
4929                 /* IP1_24 [1] */
4930                 FN_A1, FN_SCIFB1_TXD,
4931                 /* IP1_23_22 [2] */
4932                 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
4933                 /* IP1_21_20 [2] */
4934                 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
4935                 /* IP1_19_18 [2] */
4936                 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
4937                 /* IP1_17_15 [3] */
4938                 FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
4939                 0, 0, 0,
4940                 /* IP1_14_13 [2] */
4941                 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
4942                 /* IP1_12_11 [2] */
4943                 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
4944                 /* IP1_10_8 [3] */
4945                 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
4946                 0, 0, 0,
4947                 /* IP1_7_6 [2] */
4948                 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
4949                 /* IP1_5_4 [2] */
4950                 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
4951                 /* IP1_3_2 [2] */
4952                 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
4953                 /* IP1_1_0 [2] */
4954                 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
4955         },
4956         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4957                              GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
4958                              GROUP(
4959                 /* IP2_31_30 [2] */
4960                 FN_A20, FN_SPCLK, 0, 0,
4961                 /* IP2_29_27 [3] */
4962                 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
4963                 0, 0, 0, 0,
4964                 /* IP2_26_24 [3] */
4965                 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
4966                 0, 0, 0, 0,
4967                 /* IP2_23_21 [3] */
4968                 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
4969                 0, 0, 0, 0,
4970                 /* IP2_20_18 [3] */
4971                 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
4972                 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4973                 /* IP2_17_16 [2] */
4974                 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
4975                 /* IP2_15_14 [2] */
4976                 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
4977                 /* IP2_13_12 [2] */
4978                 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
4979                 /* IP2_11_10 [2] */
4980                 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
4981                 /* IP2_9_8 [2] */
4982                 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
4983                 /* IP2_7_6 [2] */
4984                 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
4985                 /* IP2_5_4 [2] */
4986                 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
4987                 /* IP2_3_2 [2] */
4988                 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4989                 /* IP2_1_0 [2] */
4990                 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
4991         },
4992         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4993                              GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
4994                                    2, 2, 2, 2),
4995                              GROUP(
4996                 /* IP3_31 [1] */
4997                 FN_RD_WR_N, FN_ATAG1_N,
4998                 /* IP3_30 [1] */
4999                 FN_RD_N, FN_ATACS11_N,
5000                 /* IP3_29_27 [3] */
5001                 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
5002                 0, 0, 0,
5003                 /* IP3_26_24 [3] */
5004                 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
5005                 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
5006                 /* IP3_23_21 [3] */
5007                 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
5008                 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
5009                 /* IP3_20_18 [3] */
5010                 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
5011                 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
5012                 /* IP3_17_15 [3] */
5013                 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
5014                 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
5015                 /* IP3_14_13 [2] */
5016                 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
5017                 /* IP3_12 [1] */
5018                 FN_EX_CS0_N, FN_VI1_DATA10,
5019                 /* IP3_11 [1] */
5020                 FN_CS1_N_A26, FN_VI1_DATA9,
5021                 /* IP3_10 [1] */
5022                 FN_CS0_N, FN_VI1_DATA8,
5023                 /* IP3_9_8 [2] */
5024                 FN_A25, FN_SSL, FN_ATARD1_N, 0,
5025                 /* IP3_7_6 [2] */
5026                 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
5027                 /* IP3_5_4 [2] */
5028                 FN_A23, FN_IO2, 0, FN_ATAWR1_N,
5029                 /* IP3_3_2 [2] */
5030                 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
5031                 /* IP3_1_0 [2] */
5032                 FN_A21, FN_MOSI_IO0, 0, 0, ))
5033         },
5034         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5035                              GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
5036                              GROUP(
5037                 /* IP4_31_30 [2] */
5038                 FN_DU0_DG4, FN_LCDOUT12, 0, 0,
5039                 /* IP4_29_28 [2] */
5040                 FN_DU0_DG3, FN_LCDOUT11, 0, 0,
5041                 /* IP4_27_26 [2] */
5042                 FN_DU0_DG2, FN_LCDOUT10, 0, 0,
5043                 /* IP4_25_23 [3] */
5044                 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
5045                 0, 0, 0, 0,
5046                 /* IP4_22_20 [3] */
5047                 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
5048                 0, 0, 0, 0,
5049                 /* IP4_19_18 [2] */
5050                 FN_DU0_DR7, FN_LCDOUT23, 0, 0,
5051                 /* IP4_17_16 [2] */
5052                 FN_DU0_DR6, FN_LCDOUT22, 0, 0,
5053                 /* IP4_15_14 [2] */
5054                 FN_DU0_DR5, FN_LCDOUT21, 0, 0,
5055                 /* IP4_13_12 [2] */
5056                 FN_DU0_DR4, FN_LCDOUT20, 0, 0,
5057                 /* IP4_11_10 [2] */
5058                 FN_DU0_DR3, FN_LCDOUT19, 0, 0,
5059                 /* IP4_9_8 [2] */
5060                 FN_DU0_DR2, FN_LCDOUT18, 0, 0,
5061                 /* IP4_7_5 [3] */
5062                 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
5063                 0, 0, 0, 0,
5064                 /* IP4_4_2 [3] */
5065                 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
5066                 0, 0, 0, 0,
5067                 /* IP4_1_0 [2] */
5068                 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
5069         },
5070         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5071                              GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
5072                                    2, 2, 2),
5073                              GROUP(
5074                 /* IP5_31_30 [2] */
5075                 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
5076                 /* IP5_29_28 [2] */
5077                 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
5078                 /* IP5_27_26 [2] */
5079                 FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
5080                 /* IP5_25_24 [2] */
5081                 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
5082                 /* IP5_23_22 [2] */
5083                 FN_DU0_DB7, FN_LCDOUT7, 0, 0,
5084                 /* IP5_21_20 [2] */
5085                 FN_DU0_DB6, FN_LCDOUT6, 0, 0,
5086                 /* IP5_19_18 [2] */
5087                 FN_DU0_DB5, FN_LCDOUT5, 0, 0,
5088                 /* IP5_17_16 [2] */
5089                 FN_DU0_DB4, FN_LCDOUT4, 0, 0,
5090                 /* IP5_15_14 [2] */
5091                 FN_DU0_DB3, FN_LCDOUT3, 0, 0,
5092                 /* IP5_13_12 [2] */
5093                 FN_DU0_DB2, FN_LCDOUT2, 0, 0,
5094                 /* IP5_11_9 [3] */
5095                 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
5096                 FN_CAN0_TX_C, 0, 0, 0,
5097                 /* IP5_8_6 [3] */
5098                 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
5099                 FN_CAN0_RX_C, 0, 0, 0,
5100                 /* IP5_5_4 [2] */
5101                 FN_DU0_DG7, FN_LCDOUT15, 0, 0,
5102                 /* IP5_3_2 [2] */
5103                 FN_DU0_DG6, FN_LCDOUT14, 0, 0,
5104                 /* IP5_1_0 [2] */
5105                 FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
5106         },
5107         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5108                              GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
5109                                    1, 1, 2, 2, 2, 2),
5110                              GROUP(
5111                 /* IP6_31_29 [3] */
5112                 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
5113                 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
5114                 /* IP6_28_26 [3] */
5115                 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
5116                 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
5117                 /* IP6_25_23 [3] */
5118                 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
5119                 FN_AVB_COL, 0, 0, 0,
5120                 /* IP6_22_20 [3] */
5121                 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
5122                 FN_AVB_RX_ER, 0, 0, 0,
5123                 /* IP6_19_17 [3] */
5124                 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
5125                 FN_AVB_RXD7, 0, 0, 0,
5126                 /* IP6_16 [1] */
5127                 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
5128                 /* IP6_15 [1] */
5129                 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
5130                 /* IP6_14 [1] */
5131                 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
5132                 /* IP6_13 [1] */
5133                 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
5134                 /* IP6_12 [1] */
5135                 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
5136                 /* IP6_11 [1] */
5137                 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
5138                 /* IP6_10 [1] */
5139                 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
5140                 /* IP6_9 [1] */
5141                 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
5142                 /* IP6_8 [1] */
5143                 FN_VI0_CLK, FN_AVB_RX_CLK,
5144                 /* IP6_7_6 [2] */
5145                 FN_DU0_CDE, FN_QPOLB, 0, 0,
5146                 /* IP6_5_4 [2] */
5147                 FN_DU0_DISP, FN_QPOLA, 0, 0,
5148                 /* IP6_3_2 [2] */
5149                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
5150                 0,
5151                 /* IP6_1_0 [2] */
5152                 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
5153         },
5154         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5155                              GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5156                              GROUP(
5157                 /* IP7_31 [1] */
5158                 FN_DREQ0_N, FN_SCIFB1_RXD,
5159                 /* IP7_30 [1] */
5160                 0, 0,
5161                 /* IP7_29_27 [3] */
5162                 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
5163                 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
5164                 /* IP7_26_24 [3] */
5165                 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
5166                 FN_SSI_SCK6_B, 0, 0, 0,
5167                 /* IP7_23_21 [3] */
5168                 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
5169                 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
5170                 /* IP7_20_18 [3] */
5171                 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
5172                 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
5173                 /* IP7_17_15 [3] */
5174                 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
5175                 FN_SSI_SCK5_B, 0, 0, 0,
5176                 /* IP7_14_12 [3] */
5177                 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
5178                 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
5179                 /* IP7_11_9 [3] */
5180                 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
5181                 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
5182                 /* IP7_8_6 [3] */
5183                 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
5184                 FN_AVB_TXD2, FN_ADICHS0, 0, 0,
5185                 /* IP7_5_3 [3] */
5186                 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
5187                 FN_AVB_TXD1, FN_ADICLK, 0, 0,
5188                 /* IP7_2_0 [3] */
5189                 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
5190                 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
5191         },
5192         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5193                              GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
5194                              GROUP(
5195                 /* IP8_31_29 [3] */
5196                 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
5197                 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
5198                 /* IP8_28_26 [3] */
5199                 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
5200                 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
5201                 /* IP8_25_23 [3] */
5202                 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
5203                 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
5204                 /* IP8_22_20 [3] */
5205                 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
5206                 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
5207                 /* IP8_19_17 [3] */
5208                 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
5209                 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
5210                 /* IP8_16_15 [2] */
5211                 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
5212                 /* IP8_14_12 [3] */
5213                 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
5214                 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
5215                 /* IP8_11_9 [3] */
5216                 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
5217                 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
5218                 /* IP8_8_6 [3] */
5219                 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
5220                 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
5221                 /* IP8_5_3 [3] */
5222                 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
5223                 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
5224                 /* IP8_2_0 [3] */
5225                 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
5226                 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
5227         },
5228         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5229                              GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
5230                              GROUP(
5231                 /* IP9_31 [1] */
5232                 0, 0,
5233                 /* IP9_30_28 [3] */
5234                 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
5235                 FN_SSI_SDATA1_B, 0, 0, 0,
5236                 /* IP9_27_25 [3] */
5237                 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
5238                 FN_SSI_WS1_B, 0, 0, 0,
5239                 /* IP9_24_22 [3] */
5240                 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
5241                 FN_SSI_SCK1_B, 0, 0, 0,
5242                 /* IP9_21_19 [3] */
5243                 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
5244                 FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
5245                 /* IP9_18_17 [2] */
5246                 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
5247                 /* IP9_16_15 [2] */
5248                 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
5249                 /* IP9_14_12 [3] */
5250                 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
5251                 0, FN_FMIN_B, 0, 0,
5252                 /* IP9_11_9 [3] */
5253                 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
5254                 0, FN_FMCLK_B, 0, 0,
5255                 /* IP9_8_6 [3] */
5256                 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
5257                 0, FN_BPFCLK_B, 0, 0,
5258                 /* IP9_5_3 [3] */
5259                 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
5260                 0, FN_TPUTO1_C, 0, 0,
5261                 /* IP9_2_0 [3] */
5262                 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
5263                 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
5264         },
5265         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5266                              GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5267                              GROUP(
5268                 /* IP10_31_30 [2] */
5269                 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
5270                 /* IP10_29_27 [3] */
5271                 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
5272                 0, 0, 0, 0,
5273                 /* IP10_26_24 [3] */
5274                 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
5275                 FN_SSI_SDATA4_B, 0, 0, 0,
5276                 /* IP10_23_21 [3] */
5277                 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
5278                 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
5279                 /* IP10_20_18 [3] */
5280                 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
5281                 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
5282                 /* IP10_17_15 [3] */
5283                 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
5284                 FN_SSI_SDATA9_B, 0, 0, 0,
5285                 /* IP10_14_12 [3] */
5286                 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
5287                 0, 0, 0, 0,
5288                 /* IP10_11_9 [3] */
5289                 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
5290                 0, 0, 0, 0,
5291                 /* IP10_8_6 [3] */
5292                 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
5293                 0, 0, 0, 0,
5294                 /* IP10_5_3 [3] */
5295                 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
5296                 0, 0, 0, 0,
5297                 /* IP10_2_0 [3] */
5298                 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
5299                 0, 0, 0, 0, ))
5300         },
5301         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5302                              GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
5303                              GROUP(
5304                 /* IP11_31_30 [2] */
5305                 0, 0, 0, 0,
5306                 /* IP11_29_27 [3] */
5307                 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
5308                 0, 0, 0, 0,
5309                 /* IP11_26_24 [3] */
5310                 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
5311                 0, 0, 0, 0,
5312                 /* IP11_23_21 [3] */
5313                 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
5314                 0, 0, 0, 0,
5315                 /* IP11_20_18 [3] */
5316                 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
5317                 FN_CAN_CLK_D, 0, 0, 0,
5318                 /* IP11_17_16 [2] */
5319                 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
5320                 /* IP11_15_14 [2] */
5321                 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
5322                 /* IP11_13_11 [3] */
5323                 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
5324                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
5325                 /* IP11_10_8 [3] */
5326                 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
5327                 FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
5328                 /* IP11_7_6 [2] */
5329                 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
5330                 /* IP11_5_3 [3] */
5331                 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
5332                 0, 0, 0, 0,
5333                 /* IP11_2_0 [3] */
5334                 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
5335                 0, 0, 0, 0, ))
5336         },
5337         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5338                              GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
5339                              GROUP(
5340                 /* IP12_31_30 [2] */
5341                 0, 0, 0, 0,
5342                 /* IP12_29_27 [3] */
5343                 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
5344                 FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
5345                 /* IP12_26_24 [3] */
5346                 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
5347                 FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
5348                 /* IP12_23_21 [3] */
5349                 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
5350                 FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
5351                 /* IP12_20_18 [3] */
5352                 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
5353                 FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
5354                 /* IP12_17_15 [3] */
5355                 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
5356                 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
5357                 /* IP12_14_13 [2] */
5358                 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
5359                 /* IP12_12_11 [2] */
5360                 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
5361                 /* IP12_10_9 [2] */
5362                 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
5363                 /* IP12_8_6 [3] */
5364                 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
5365                 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
5366                 /* IP12_5_3 [3] */
5367                 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
5368                 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
5369                 /* IP12_2_0 [3] */
5370                 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
5371                 0, FN_DREQ1_N_B, 0, 0, ))
5372         },
5373         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5374                              GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5375                              GROUP(
5376                 /* IP13_31 [1] */
5377                 0, 0,
5378                 /* IP13_30 [1] */
5379                 0, 0,
5380                 /* IP13_29 [1] */
5381                 0, 0,
5382                 /* IP13_28 [1] */
5383                 0, 0,
5384                 /* IP13_27 [1] */
5385                 0, 0,
5386                 /* IP13_26_24 [3] */
5387                 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
5388                 FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
5389                 /* IP13_23_21 [3] */
5390                 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
5391                 FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
5392                 /* IP13_20_18 [3] */
5393                 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
5394                 FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
5395                 /* IP13_17_15 [3] */
5396                 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
5397                 FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
5398                 /* IP13_14_12 [3] */
5399                 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
5400                 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
5401                 /* IP13_11_9 [3] */
5402                 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
5403                 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
5404                 /* IP13_8_6 [3] */
5405                 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
5406                 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
5407                 /* IP13_5_3 [2] */
5408                 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
5409                 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
5410                 /* IP13_2_0 [3] */
5411                 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
5412                 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
5413         },
5414         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5415                              GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
5416                              GROUP(
5417                 /* SEL_ADG [2] */
5418                 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
5419                 /* RESERVED [1] */
5420                 0, 0,
5421                 /* SEL_CAN [2] */
5422                 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
5423                 /* SEL_DARC [3] */
5424                 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
5425                 FN_SEL_DARC_4, 0, 0, 0,
5426                 /* RESERVED [4] */
5427                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5428                 /* SEL_ETH [1] */
5429                 FN_SEL_ETH_0, FN_SEL_ETH_1,
5430                 /* RESERVED [1] */
5431                 0, 0,
5432                 /* SEL_IC200 [3] */
5433                 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
5434                 FN_SEL_I2C00_4, 0, 0, 0,
5435                 /* SEL_I2C01 [3] */
5436                 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
5437                 FN_SEL_I2C01_4, 0, 0, 0,
5438                 /* SEL_I2C02 [3] */
5439                 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
5440                 FN_SEL_I2C02_4, 0, 0, 0,
5441                 /* SEL_I2C03 [3] */
5442                 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
5443                 FN_SEL_I2C03_4, 0, 0, 0,
5444                 /* SEL_I2C04 [3] */
5445                 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
5446                 FN_SEL_I2C04_4, 0, 0, 0,
5447                 /* SEL_I2C05 [2] */
5448                 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
5449                 /* RESERVED [1] */
5450                 0, 0, ))
5451         },
5452         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5453                              GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
5454                                    2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
5455                              GROUP(
5456                 /* SEL_IEB [2] */
5457                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5458                 /* SEL_IIC0 [2] */
5459                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
5460                 /* SEL_LBS [1] */
5461                 FN_SEL_LBS_0, FN_SEL_LBS_1,
5462                 /* SEL_MSI1 [1] */
5463                 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
5464                 /* SEL_MSI2 [1] */
5465                 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
5466                 /* SEL_RAD [1] */
5467                 FN_SEL_RAD_0, FN_SEL_RAD_1,
5468                 /* SEL_RCN [1] */
5469                 FN_SEL_RCN_0, FN_SEL_RCN_1,
5470                 /* SEL_RSP [1] */
5471                 FN_SEL_RSP_0, FN_SEL_RSP_1,
5472                 /* SEL_SCIFA0 [2] */
5473                 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
5474                 FN_SEL_SCIFA0_3,
5475                 /* SEL_SCIFA1 [2] */
5476                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5477                 /* SEL_SCIFA2 [1] */
5478                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
5479                 /* SEL_SCIFA3 [1] */
5480                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
5481                 /* SEL_SCIFA4 [2] */
5482                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
5483                 FN_SEL_SCIFA4_3,
5484                 /* SEL_SCIFA5 [2] */
5485                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
5486                 FN_SEL_SCIFA5_3,
5487                 /* RESERVED [1] */
5488                 0, 0,
5489                 /* SEL_TMU [1] */
5490                 FN_SEL_TMU_0, FN_SEL_TMU_1,
5491                 /* SEL_TSIF0 [2] */
5492                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5493                 /* SEL_CAN0 [2] */
5494                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5495                 /* SEL_CAN1 [2] */
5496                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5497                 /* SEL_HSCIF0 [1] */
5498                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
5499                 /* SEL_HSCIF1 [1] */
5500                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5501                 /* RESERVED [2] */
5502                 0, 0, 0, 0, ))
5503         },
5504         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5505                              GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
5506                                    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
5507                              GROUP(
5508                 /* SEL_SCIF0 [2] */
5509                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
5510                 /* SEL_SCIF1 [2] */
5511                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
5512                 /* SEL_SCIF2 [2] */
5513                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
5514                 /* SEL_SCIF3 [1] */
5515                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
5516                 /* SEL_SCIF4 [3] */
5517                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
5518                 FN_SEL_SCIF4_4, 0, 0, 0,
5519                 /* SEL_SCIF5 [2] */
5520                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
5521                 /* SEL_SSI1 [1] */
5522                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5523                 /* SEL_SSI2 [1] */
5524                 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
5525                 /* SEL_SSI4 [1] */
5526                 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
5527                 /* SEL_SSI5 [1] */
5528                 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
5529                 /* SEL_SSI6 [1] */
5530                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5531                 /* SEL_SSI7 [1] */
5532                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5533                 /* SEL_SSI8 [1] */
5534                 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
5535                 /* SEL_SSI9 [1] */
5536                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5537                 /* RESERVED [1] */
5538                 0, 0,
5539                 /* RESERVED [1] */
5540                 0, 0,
5541                 /* RESERVED [1] */
5542                 0, 0,
5543                 /* RESERVED [1] */
5544                 0, 0,
5545                 /* RESERVED [1] */
5546                 0, 0,
5547                 /* RESERVED [1] */
5548                 0, 0,
5549                 /* RESERVED [1] */
5550                 0, 0,
5551                 /* RESERVED [1] */
5552                 0, 0,
5553                 /* RESERVED [1] */
5554                 0, 0,
5555                 /* RESERVED [1] */
5556                 0, 0,
5557                 /* RESERVED [1] */
5558                 0, 0,
5559                 /* RESERVED [1] */
5560                 0, 0, ))
5561         },
5562         { },
5563 };
5564
5565 static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5566 {
5567         *pocctrl = 0xe606006c;
5568
5569         switch (pin & 0x1f) {
5570         case 6: return 23;
5571         case 7: return 16;
5572         case 14: return 15;
5573         case 15: return 8;
5574         case 0 ... 5:
5575         case 8 ... 13:
5576                 return 22 - (pin & 0x1f);
5577         case 16 ... 23:
5578                 return 47 - (pin & 0x1f);
5579         }
5580
5581         return -EINVAL;
5582 }
5583
5584 static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
5585 {
5586         /* Initialize TDSEL on old revisions */
5587         if ((rmobile_get_cpu_rev_integer() == 1) &&
5588             (rmobile_get_cpu_rev_fraction() == 0))
5589                 sh_pfc_write(pfc, 0xe6060068, 0x55555500);
5590
5591         return 0;
5592 }
5593
5594 static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
5595         .init = r8a7794_pinmux_soc_init,
5596         .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
5597 };
5598
5599 #ifdef CONFIG_PINCTRL_PFC_R8A7745
5600 const struct sh_pfc_soc_info r8a7745_pinmux_info = {
5601         .name = "r8a77450_pfc",
5602         .ops = &r8a7794_pinmux_ops,
5603         .unlock_reg = 0xe6060000, /* PMMR */
5604
5605         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5606
5607         .pins = pinmux_pins,
5608         .nr_pins = ARRAY_SIZE(pinmux_pins),
5609         .groups = pinmux_groups,
5610         .nr_groups = ARRAY_SIZE(pinmux_groups),
5611         .functions = pinmux_functions,
5612         .nr_functions = ARRAY_SIZE(pinmux_functions),
5613
5614         .cfg_regs = pinmux_config_regs,
5615
5616         .pinmux_data = pinmux_data,
5617         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5618 };
5619 #endif
5620
5621 #ifdef CONFIG_PINCTRL_PFC_R8A7794
5622 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
5623         .name = "r8a77940_pfc",
5624         .ops = &r8a7794_pinmux_ops,
5625         .unlock_reg = 0xe6060000, /* PMMR */
5626
5627         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5628
5629         .pins = pinmux_pins,
5630         .nr_pins = ARRAY_SIZE(pinmux_pins),
5631         .groups = pinmux_groups,
5632         .nr_groups = ARRAY_SIZE(pinmux_groups),
5633         .functions = pinmux_functions,
5634         .nr_functions = ARRAY_SIZE(pinmux_functions),
5635
5636         .cfg_regs = pinmux_config_regs,
5637
5638         .pinmux_data = pinmux_data,
5639         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5640 };
5641 #endif