drivers/pinctrl/renesas/pfc-r8a7791.c

   1 /*
   2  * r8a7791/r8a7743 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2014-2017 Cogent Embedded, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <dm/pinctrl.h>
  14 #include <linux/kernel.h>
  15
  16 #include "sh_pfc.h"
  17
  18 /*
  19  * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
  20  * which case they support both 3.3V and 1.8V signalling.
  21  */
  22 #define CPU_ALL_PORT(fn, sfx)                                           \
  23         PORT_GP_32(0, fn, sfx),                                         \
  24         PORT_GP_26(1, fn, sfx),                                         \
  25         PORT_GP_32(2, fn, sfx),                                         \
  26         PORT_GP_32(3, fn, sfx),                                         \
  27         PORT_GP_32(4, fn, sfx),                                         \
  28         PORT_GP_32(5, fn, sfx),                                         \
  29         PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  30         PORT_GP_1(6, 24, fn, sfx),                                      \
  31         PORT_GP_1(6, 25, fn, sfx),                                      \
  32         PORT_GP_1(6, 26, fn, sfx),                                      \
  33         PORT_GP_1(6, 27, fn, sfx),                                      \
  34         PORT_GP_1(6, 28, fn, sfx),                                      \
  35         PORT_GP_1(6, 29, fn, sfx),                                      \
  36         PORT_GP_1(6, 30, fn, sfx),                                      \
  37         PORT_GP_1(6, 31, fn, sfx),                                      \
  38         PORT_GP_26(7, fn, sfx)
  39
  40 enum {
  41         PINMUX_RESERVED = 0,
  42
  43         PINMUX_DATA_BEGIN,
  44         GP_ALL(DATA),
  45         PINMUX_DATA_END,
  46
  47         PINMUX_FUNCTION_BEGIN,
  48         GP_ALL(FN),
  49
  50         /* GPSR0 */
  51         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  52         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  53         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  54         FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  55         FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  56         FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  57
  58         /* GPSR1 */
  59         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  60         FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  61         FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  62         FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  63         FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  64         FN_IP3_21_20,
  65
  66         /* GPSR2 */
  67         FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  68         FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  69         FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  70         FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  71         FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  72         FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  73         FN_IP6_5_3, FN_IP6_7_6,
  74
  75         /* GPSR3 */
  76         FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
  77         FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
  78         FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
  79         FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
  80         FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
  81         FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
  82         FN_IP9_18_17,
  83
  84         /* GPSR4 */
  85         FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
  86         FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
  87         FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
  88         FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
  89         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
  90         FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
  91         FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  92         FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
  93
  94         /* GPSR5 */
  95         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
  96         FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
  97         FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
  98         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
  99         FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
 100         FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
 101         FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
 102
 103         /* GPSR6 */
 104         FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
 105         FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
 106         FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
 107         FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
 108         FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
 109         FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
 110         FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
 111         FN_USB1_OVC, FN_DU0_DOTCLKIN,
 112
 113         /* GPSR7 */
 114         FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
 115         FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
 116         FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
 117         FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
 118         FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
 119         FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
 120
 121         /* IPSR0 */
 122         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
 123         FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
 124         FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
 125         FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
 126         FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
 127         FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
 128
 129         /* IPSR1 */
 130         FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
 131         FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
 132         FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
 133         FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
 134         FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
 135         FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
 136         FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
 137         FN_A15, FN_BPFCLK_C,
 138         FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
 139         FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
 140         FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
 141
 142         /* IPSR2 */
 143         FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
 144         FN_A20, FN_SPCLK,
 145         FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
 146         FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
 147         FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
 148         FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
 149         FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
 150         FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
 151         FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
 152         FN_EX_CS1_N, FN_MSIOF2_SCK,
 153         FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
 154         FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
 155
 156         /* IPSR3 */
 157         FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
 158         FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
 159         FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
 160         FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
 161         FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
 162         FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
 163         FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
 164         FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
 165         FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
 166         FN_DREQ0, FN_PWM3, FN_TPU_TO3,
 167         FN_DACK0, FN_DRACK0, FN_REMOCON,
 168         FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
 169         FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
 170         FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
 171         FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
 172
 173         /* IPSR4 */
 174         FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
 175         FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
 176         FN_GLO_I0_D,
 177         FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
 178         FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
 179         FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
 180         FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
 181         FN_GLO_Q1_D, FN_HCTS1_N_E,
 182         FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
 183         FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
 184         FN_SSI_SCK4, FN_GLO_SS_D,
 185         FN_SSI_WS4, FN_GLO_RFON_D,
 186         FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
 187         FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
 188         FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
 189
 190         /* IPSR5 */
 191         FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
 192         FN_MSIOF2_TXD_D, FN_VI1_R3_B,
 193         FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
 194         FN_MSIOF2_SS1_D, FN_VI1_R4_B,
 195         FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
 196         FN_MSIOF2_RXD_D, FN_VI1_R5_B,
 197         FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
 198         FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
 199         FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
 200         FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
 201         FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
 202         FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
 203         FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
 204         FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
 205         FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
 206
 207         /* IPSR6 */
 208         FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
 209         FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
 210         FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 211         FN_SCIFA2_RXD, FN_FMIN_E,
 212         FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 213         FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
 214         FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
 215         FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
 216         FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
 217         FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
 218         FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
 219         FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
 220         FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 221         FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
 222
 223         /* IPSR7 */
 224         FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
 225         FN_SCIF_CLK_B, FN_GPS_MAG_D,
 226         FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
 227         FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
 228         FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
 229         FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
 230         FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
 231         FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
 232         FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
 233         FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
 234         FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
 235         FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
 236         FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
 237         FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
 238         FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
 239         FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
 240         FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
 241         FN_SCIFA1_SCK, FN_SSI_SCK78_B,
 242
 243         /* IPSR8 */
 244         FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
 245         FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
 246         FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
 247         FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
 248         FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
 249         FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
 250         FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
 251         FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
 252         FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
 253         FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
 254         FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
 255         FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
 256         FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
 257         FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
 258         FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
 259         FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
 260         FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
 261
 262         /* IPSR9 */
 263         FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
 264         FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
 265         FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
 266         FN_DU1_DOTCLKOUT0, FN_QCLK,
 267         FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
 268         FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
 269         FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
 270         FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
 271         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
 272         FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
 273         FN_DU1_DISP, FN_QPOLA,
 274         FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
 275         FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
 276         FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
 277         FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
 278         FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
 279         FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
 280         FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
 281         FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
 282
 283         /* IPSR10 */
 284         FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
 285         FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
 286         FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
 287         FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
 288         FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
 289         FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
 290         FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
 291         FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
 292         FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
 293         FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
 294         FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
 295         FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
 296         FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
 297         FN_TS_SDATA0_C, FN_ATACS11_N,
 298         FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
 299         FN_TS_SCK0_C, FN_ATAG1_N,
 300         FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
 301         FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
 302         FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
 303
 304         /* IPSR11 */
 305         FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
 306         FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
 307         FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
 308         FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
 309         FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
 310         FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
 311         FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
 312         FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
 313         FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
 314         FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
 315         FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
 316         FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
 317         FN_VI1_DATA7, FN_AVB_MDC,
 318         FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
 319         FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
 320
 321         /* IPSR12 */
 322         FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
 323         FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
 324         FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
 325         FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
 326         FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
 327         FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
 328         FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
 329         FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
 330         FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
 331         FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
 332         FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
 333         FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
 334         FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
 335         FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
 336         FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
 337         FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
 338         FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
 339
 340         /* IPSR13 */
 341         FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
 342         FN_ADICLK_B, FN_MSIOF0_SS1_C,
 343         FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
 344         FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
 345         FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
 346         FN_ADICHS2_B, FN_MSIOF0_TXD_C,
 347         FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
 348         FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
 349         FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
 350         FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
 351         FN_SCIFA5_TXD_B, FN_TX3_C,
 352         FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
 353         FN_SCIFA5_RXD_B, FN_RX3_C,
 354         FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
 355         FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
 356         FN_SD1_DATA3, FN_IERX_B,
 357         FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
 358
 359         /* IPSR14 */
 360         FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
 361         FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
 362         FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
 363         FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
 364         FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
 365         FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
 366         FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
 367         FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
 368         FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
 369         FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
 370         FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
 371         FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
 372         FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
 373         FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
 374
 375         /* IPSR15 */
 376         FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
 377         FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
 378         FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
 379         FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
 380         FN_PWM5_B, FN_SCIFA3_TXD_C,
 381         FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
 382         FN_VI1_G6_B, FN_SCIFA3_RXD_C,
 383         FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
 384         FN_VI1_G7_B, FN_SCIFA3_SCK_C,
 385         FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
 386         FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
 387         FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
 388         FN_TCLK2, FN_VI1_DATA3_C,
 389         FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
 390         FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
 391
 392         /* IPSR16 */
 393         FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
 394         FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
 395         FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
 396         FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
 397         FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
 398
 399         /* MOD_SEL */
 400         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 401         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
 402         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
 403         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 404         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 405         FN_SEL_SSI9_0, FN_SEL_SSI9_1,
 406         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 407         FN_SEL_QSP_0, FN_SEL_QSP_1,
 408         FN_SEL_SSI7_0, FN_SEL_SSI7_1,
 409         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
 410         FN_SEL_HSCIF1_4,
 411         FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
 412         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 413         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
 414         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 415         FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
 416
 417         /* MOD_SEL2 */
 418         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 419         FN_SEL_SCIF0_4,
 420         FN_SEL_SCIF_0, FN_SEL_SCIF_1,
 421         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 422         FN_SEL_CAN0_4, FN_SEL_CAN0_5,
 423         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 424         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 425         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
 426         FN_SEL_ADG_0, FN_SEL_ADG_1,
 427         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
 428         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 429         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 430         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
 431         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
 432         FN_SEL_SIM_0, FN_SEL_SIM_1,
 433         FN_SEL_SSI8_0, FN_SEL_SSI8_1,
 434
 435         /* MOD_SEL3 */
 436         FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
 437         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
 438         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
 439         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
 440         FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
 441         FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
 442         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
 443         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 444         FN_SEL_MMC_0, FN_SEL_MMC_1,
 445         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 446         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 447         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
 448         FN_SEL_I2C1_4,
 449         FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
 450
 451         /* MOD_SEL4 */
 452         FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
 453         FN_SEL_SOF1_4,
 454         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
 455         FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
 456         FN_SEL_RAD_0, FN_SEL_RAD_1,
 457         FN_SEL_RCN_0, FN_SEL_RCN_1,
 458         FN_SEL_RSP_0, FN_SEL_RSP_1,
 459         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
 460         FN_SEL_SCIF2_4,
 461         FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
 462         FN_SEL_SOF2_4,
 463         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 464         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 465         FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
 466         PINMUX_FUNCTION_END,
 467
 468         PINMUX_MARK_BEGIN,
 469
 470         EX_CS0_N_MARK, RD_N_MARK,
 471
 472         AUDIO_CLKA_MARK,
 473
 474         VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
 475         VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
 476         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
 477
 478         SD1_CLK_MARK,
 479
 480         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 481         DU0_DOTCLKIN_MARK,
 482
 483         /* IPSR0 */
 484         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
 485         D6_MARK, D7_MARK, D8_MARK,
 486         D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
 487         A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
 488         PWM2_B_MARK,
 489         A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
 490         A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
 491         A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
 492
 493         /* IPSR1 */
 494         A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
 495         A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
 496         A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
 497         A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
 498         A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
 499         A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
 500         A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
 501         A15_MARK, BPFCLK_C_MARK,
 502         A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
 503         A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
 504         A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
 505
 506         /* IPSR2 */
 507         A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
 508         SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
 509         A20_MARK, SPCLK_MARK,
 510         A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
 511         A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
 512         A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
 513         A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
 514         A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
 515         RX1_MARK, SCIFA1_RXD_MARK,
 516         CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
 517         CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
 518         EX_CS1_N_MARK, MSIOF2_SCK_MARK,
 519         EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
 520         EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
 521         ATAG0_N_MARK, EX_WAIT1_MARK,
 522
 523         /* IPSR3 */
 524         EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
 525         EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
 526         SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
 527         BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
 528         SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
 529         RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
 530         SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
 531         WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
 532         WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
 533         EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
 534         DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
 535         DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
 536         SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
 537         SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
 538         SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
 539         SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
 540         SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
 541         SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
 542
 543         /* IPSR4 */
 544         SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
 545         SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
 546         MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
 547         SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
 548         MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
 549         SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
 550         SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
 551         HSCK1_E_MARK,
 552         SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
 553         GLO_Q1_D_MARK, HCTS1_N_E_MARK,
 554         SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
 555         SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
 556         SSI_SCK4_MARK, GLO_SS_D_MARK,
 557         SSI_WS4_MARK, GLO_RFON_D_MARK,
 558         SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
 559         SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
 560         MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
 561
 562         /* IPSR5 */
 563         SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
 564         MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
 565         SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
 566         MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
 567         SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
 568         MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
 569         SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
 570         SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
 571         SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
 572         SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
 573         SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
 574         SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
 575         SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
 576         SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
 577         SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
 578
 579         /* IPSR6 */
 580         AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
 581         SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
 582         AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 583         SCIFA2_RXD_MARK, FMIN_E_MARK,
 584         AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
 585         IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
 586         IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
 587         IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
 588         IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
 589         IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
 590         MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
 591         IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
 592         IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 593         I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
 594         IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
 595         GPS_CLK_C_MARK, GPS_CLK_D_MARK,
 596         IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
 597         GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
 598
 599         /* IPSR7 */
 600         IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
 601         SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
 602         DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
 603         SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
 604         DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
 605         SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
 606         DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
 607         DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
 608         DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
 609         DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
 610         DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
 611         DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
 612         DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
 613         SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
 614         DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
 615         SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
 616         DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
 617         SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
 618
 619         /* IPSR8 */
 620         DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
 621         DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
 622         SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
 623         DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
 624         SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
 625         DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
 626         SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
 627         DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
 628         SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
 629         DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
 630         SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
 631         DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
 632         SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
 633         DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
 634         SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
 635         DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
 636         DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
 637         DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
 638
 639         /* IPSR9 */
 640         DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
 641         DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
 642         SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
 643         DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 644         DU1_DOTCLKOUT0_MARK, QCLK_MARK,
 645         DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
 646         TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
 647         DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
 648         DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
 649         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 650         CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
 651         DU1_DISP_MARK, QPOLA_MARK,
 652         DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
 653         VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
 654         VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
 655         VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
 656         VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
 657         VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
 658         VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
 659         HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
 660
 661         /* IPSR10 */
 662         VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
 663         HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
 664         VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
 665         HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
 666         VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
 667         HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
 668         VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
 669         HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
 670         VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
 671         CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
 672         VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
 673         VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
 674         VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
 675         TS_SDATA0_C_MARK, ATACS11_N_MARK,
 676         VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
 677         TS_SCK0_C_MARK, ATAG1_N_MARK,
 678         VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
 679         VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
 680         VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
 681         I2C1_SCL_D_MARK,
 682
 683         /* IPSR11 */
 684         VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
 685         I2C1_SDA_D_MARK,
 686         VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
 687         VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
 688         I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
 689         VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
 690         TX4_B_MARK, SCIFA4_TXD_B_MARK,
 691         VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
 692         RX4_B_MARK, SCIFA4_RXD_B_MARK,
 693         VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
 694         VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
 695         VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
 696         VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
 697         VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
 698         VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
 699         VI1_DATA7_MARK, AVB_MDC_MARK,
 700         ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
 701         ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
 702
 703         /* IPSR12 */
 704         ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
 705         ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
 706         ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
 707         I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
 708         ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
 709         I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
 710         ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
 711         CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
 712         ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
 713         CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
 714         ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
 715         ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
 716         ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
 717         ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
 718         STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
 719         ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
 720         STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
 721         ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
 722
 723         /* IPSR13 */
 724         STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
 725         ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
 726         STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
 727         STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
 728         STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
 729         ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
 730         SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
 731         SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
 732         SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
 733         SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
 734         SCIFA5_TXD_B_MARK, TX3_C_MARK,
 735         SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
 736         SCIFA5_RXD_B_MARK, RX3_C_MARK,
 737         SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
 738         SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
 739         SD1_DATA3_MARK, IERX_B_MARK,
 740         SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
 741
 742         /* IPSR14 */
 743         SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
 744         SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
 745         SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
 746         SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
 747         SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
 748         SCIFA5_TXD_C_MARK,
 749         SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
 750         SCIFA5_RXD_C_MARK,
 751         MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
 752         VI1_CLK_C_MARK, VI1_G0_B_MARK,
 753         MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
 754         VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
 755         MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
 756         MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
 757         MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
 758         VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
 759         MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
 760         VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
 761
 762         /* IPSR15 */
 763         SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
 764         SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
 765         SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
 766         GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
 767         PWM5_B_MARK, SCIFA3_TXD_C_MARK,
 768         GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
 769         VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
 770         GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
 771         VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
 772         HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
 773         TCLK1_MARK, VI1_DATA1_C_MARK,
 774         HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
 775         HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
 776         TCLK2_MARK, VI1_DATA3_C_MARK,
 777         HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
 778         CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
 779         HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
 780         CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
 781
 782         /* IPSR16 */
 783         HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
 784         GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
 785         HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
 786         GLO_SS_C_MARK, VI1_DATA7_C_MARK,
 787         HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
 788         HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
 789         HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
 790         PINMUX_MARK_END,
 791 };
 792
 793 static const u16 pinmux_data[] = {
 794         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 795
 796         PINMUX_SINGLE(EX_CS0_N),
 797         PINMUX_SINGLE(RD_N),
 798         PINMUX_SINGLE(AUDIO_CLKA),
 799         PINMUX_SINGLE(VI0_CLK),
 800         PINMUX_SINGLE(VI0_DATA0_VI0_B0),
 801         PINMUX_SINGLE(VI0_DATA1_VI0_B1),
 802         PINMUX_SINGLE(VI0_DATA2_VI0_B2),
 803         PINMUX_SINGLE(VI0_DATA4_VI0_B4),
 804         PINMUX_SINGLE(VI0_DATA5_VI0_B5),
 805         PINMUX_SINGLE(VI0_DATA6_VI0_B6),
 806         PINMUX_SINGLE(VI0_DATA7_VI0_B7),
 807         PINMUX_SINGLE(USB0_PWEN),
 808         PINMUX_SINGLE(USB0_OVC),
 809         PINMUX_SINGLE(USB1_PWEN),
 810         PINMUX_SINGLE(USB1_OVC),
 811         PINMUX_SINGLE(DU0_DOTCLKIN),
 812         PINMUX_SINGLE(SD1_CLK),
 813
 814         /* IPSR0 */
 815         PINMUX_IPSR_GPSR(IP0_0, D0),
 816         PINMUX_IPSR_GPSR(IP0_1, D1),
 817         PINMUX_IPSR_GPSR(IP0_2, D2),
 818         PINMUX_IPSR_GPSR(IP0_3, D3),
 819         PINMUX_IPSR_GPSR(IP0_4, D4),
 820         PINMUX_IPSR_GPSR(IP0_5, D5),
 821         PINMUX_IPSR_GPSR(IP0_6, D6),
 822         PINMUX_IPSR_GPSR(IP0_7, D7),
 823         PINMUX_IPSR_GPSR(IP0_8, D8),
 824         PINMUX_IPSR_GPSR(IP0_9, D9),
 825         PINMUX_IPSR_GPSR(IP0_10, D10),
 826         PINMUX_IPSR_GPSR(IP0_11, D11),
 827         PINMUX_IPSR_GPSR(IP0_12, D12),
 828         PINMUX_IPSR_GPSR(IP0_13, D13),
 829         PINMUX_IPSR_GPSR(IP0_14, D14),
 830         PINMUX_IPSR_GPSR(IP0_15, D15),
 831         PINMUX_IPSR_GPSR(IP0_18_16, A0),
 832         PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
 833         PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
 834         PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
 835         PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
 836         PINMUX_IPSR_GPSR(IP0_20_19, A1),
 837         PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
 838         PINMUX_IPSR_GPSR(IP0_22_21, A2),
 839         PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
 840         PINMUX_IPSR_GPSR(IP0_24_23, A3),
 841         PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
 842         PINMUX_IPSR_GPSR(IP0_26_25, A4),
 843         PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
 844         PINMUX_IPSR_GPSR(IP0_28_27, A5),
 845         PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
 846         PINMUX_IPSR_GPSR(IP0_30_29, A6),
 847         PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 848
 849         /* IPSR1 */
 850         PINMUX_IPSR_GPSR(IP1_1_0, A7),
 851         PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
 852         PINMUX_IPSR_GPSR(IP1_3_2, A8),
 853         PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
 854         PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
 855         PINMUX_IPSR_GPSR(IP1_5_4, A9),
 856         PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
 857         PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
 858         PINMUX_IPSR_GPSR(IP1_7_6, A10),
 859         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
 860         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
 861         PINMUX_IPSR_GPSR(IP1_10_8, A11),
 862         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
 863         PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
 864         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
 865         PINMUX_IPSR_GPSR(IP1_13_11, A12),
 866         PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
 867         PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
 868         PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
 869         PINMUX_IPSR_GPSR(IP1_16_14, A13),
 870         PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
 871         PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
 872         PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
 873         PINMUX_IPSR_GPSR(IP1_19_17, A14),
 874         PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
 875         PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
 876         PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
 877         PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
 878         PINMUX_IPSR_GPSR(IP1_22_20, A15),
 879         PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
 880         PINMUX_IPSR_GPSR(IP1_25_23, A16),
 881         PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
 882         PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
 883         PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
 884         PINMUX_IPSR_GPSR(IP1_28_26, A17),
 885         PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
 886         PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
 887         PINMUX_IPSR_GPSR(IP1_31_29, A18),
 888         PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
 889         PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
 890         PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 891
 892         /* IPSR2 */
 893         PINMUX_IPSR_GPSR(IP2_2_0, A19),
 894         PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
 895         PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
 896         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
 897         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
 898         PINMUX_IPSR_GPSR(IP2_2_0, A20),
 899         PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
 900         PINMUX_IPSR_GPSR(IP2_6_5, A21),
 901         PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
 902         PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
 903         PINMUX_IPSR_GPSR(IP2_9_7, A22),
 904         PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
 905         PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
 906         PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
 907         PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
 908         PINMUX_IPSR_GPSR(IP2_12_10, A23),
 909         PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
 910         PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
 911         PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
 912         PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
 913         PINMUX_IPSR_GPSR(IP2_15_13, A24),
 914         PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
 915         PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
 916         PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
 917         PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
 918         PINMUX_IPSR_GPSR(IP2_18_16, A25),
 919         PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
 920         PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
 921         PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
 922         PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
 923         PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
 924         PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
 925         PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
 926         PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
 927         PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
 928         PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
 929         PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
 930         PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
 931         PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
 932         PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
 933         PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
 934         PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
 935         PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
 936         PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
 937         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
 938         PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
 939         PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
 940
 941         /* IPSR3 */
 942         PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
 943         PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
 944         PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
 945         PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
 946         PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
 947         PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
 948         PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
 949         PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
 950         PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
 951         PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
 952         PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
 953         PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
 954         PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
 955         PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
 956         PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
 957         PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
 958         PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
 959         PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
 960         PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
 961         PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
 962         PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
 963         PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
 964         PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
 965         PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
 966         PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
 967         PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
 968         PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
 969         PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
 970         PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
 971         PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
 972         PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
 973         PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
 974         PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
 975         PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
 976         PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
 977         PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
 978         PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
 979         PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
 980         PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
 981         PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
 982         PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
 983         PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
 984         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
 985         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
 986         PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
 987         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 988         PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
 989         PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
 990         PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
 991         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
 992         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
 993         PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
 994         PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
 995         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 996         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
 997         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
 998
 999         /* IPSR4 */
1000         PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
1001         PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
1002         PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
1003         PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
1004         PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
1005         PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
1006         PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
1007         PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
1008         PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1009         PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1010         PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
1011         PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
1012         PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1013         PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1014         PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1015         PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
1016         PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
1017         PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1018         PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
1019         PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
1020         PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1021         PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1022         PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
1023         PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
1024         PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
1025         PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1026         PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1027         PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1028         PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
1029         PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
1030         PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1031         PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1032         PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
1033         PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
1034         PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
1035         PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
1036         PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
1037         PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1038         PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
1039         PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1040         PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
1041         PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1042         PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
1043         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1044         PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1045         PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1046         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1047         PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
1048
1049         /* IPSR5 */
1050         PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
1051         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1052         PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1053         PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1054         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1055         PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
1056         PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
1057         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1058         PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1059         PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1060         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1061         PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
1062         PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
1063         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1064         PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1065         PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1066         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1067         PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
1068         PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
1069         PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1070         PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1071         PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
1072         PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
1073         PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1074         PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1075         PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
1076         PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1077         PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1078         PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1079         PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1080         PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1081         PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1082         PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1083         PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1084         PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1085         PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1086         PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1087         PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1088         PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1089         PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1090         PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1091         PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1092         PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1093         PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1094         PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1095         PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1096         PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1097         PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1098         PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1099
1100         /* IPSR6 */
1101         PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1102         PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1103         PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1104         PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1105         PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
1106         PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1107         PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
1108         PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1109         PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1110         PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1111         PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1112         PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1113         PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
1114         PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1115         PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
1116         PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1117         PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
1118         PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1119         PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
1120         PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
1121         PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1122         PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
1123         PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
1124         PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1125         PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
1126         PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
1127         PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
1128         PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1129         PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
1130         PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
1131         PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1132         PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
1133         PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1134         PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
1135         PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
1136         PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1137         PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
1138         PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1139         PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
1140         PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1141         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1142         PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
1143         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1144         PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
1145         PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1146         PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1147         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1148         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1149         PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
1150         PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1151         PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1152         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1153         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1154
1155         /* IPSR7 */
1156         PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
1157         PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1158         PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1159         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1160         PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1161         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1162         PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
1163         PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
1164         PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1165         PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1166         PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1167         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1168         PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
1169         PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
1170         PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1171         PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1172         PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1173         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1174         PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
1175         PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
1176         PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1177         PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
1178         PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
1179         PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1180         PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
1181         PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
1182         PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1183         PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
1184         PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
1185         PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1186         PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
1187         PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
1188         PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1189         PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
1190         PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
1191         PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1192         PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
1193         PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
1194         PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1195         PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1196         PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1197         PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1198         PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
1199         PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
1200         PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1201         PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1202         PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1203         PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1204         PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
1205         PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
1206         PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1207         PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
1208         PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1209         PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1210
1211         /* IPSR8 */
1212         PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
1213         PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
1214         PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1215         PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1216         PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
1217         PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
1218         PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1219         PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1220         PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1221         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1222         PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
1223         PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
1224         PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1225         PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1226         PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1227         PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1228         PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
1229         PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
1230         PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1231         PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1232         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1233         PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
1234         PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
1235         PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1236         PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1237         PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1238         PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
1239         PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
1240         PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1241         PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1242         PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1243         PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1244         PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
1245         PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
1246         PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1247         PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1248         PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1249         PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1250         PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
1251         PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
1252         PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1253         PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
1254         PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1255         PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1256         PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
1257         PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
1258         PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1259         PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
1260         PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
1261         PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1262         PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1263         PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
1264         PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
1265         PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1266         PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1267         PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1268
1269         /* IPSR9 */
1270         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
1271         PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
1272         PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
1273         PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1274         PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1275         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
1276         PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
1277         PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
1278         PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1279         PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1280         PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1281         PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
1282         PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
1283         PINMUX_IPSR_GPSR(IP9_7, QCLK),
1284         PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
1285         PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
1286         PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1287         PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1288         PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
1289         PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
1290         PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1291         PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
1292         PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1293         PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
1294         PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1295         PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
1296         PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1297         PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1298         PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
1299         PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
1300         PINMUX_IPSR_GPSR(IP9_16, QPOLA),
1301         PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
1302         PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
1303         PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
1304         PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
1305         PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1306         PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1307         PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1308         PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
1309         PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1310         PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1311         PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1312         PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
1313         PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1314         PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1315         PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1316         PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
1317         PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1318         PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1319         PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1320         PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
1321         PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1322         PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1323         PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
1324         PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
1325         PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1326         PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
1327         PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1328         PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1329         PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
1330
1331         /* IPSR10 */
1332         PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
1333         PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
1334         PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1335         PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
1336         PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1337         PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1338         PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
1339         PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
1340         PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
1341         PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1342         PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
1343         PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1344         PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1345         PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
1346         PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
1347         PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
1348         PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1349         PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
1350         PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1351         PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1352         PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
1353         PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
1354         PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
1355         PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1356         PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1357         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1358         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1359         PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
1360         PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
1361         PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1362         PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1363         PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1364         PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1365         PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1366         PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
1367         PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
1368         PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1369         PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
1370         PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
1371         PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1372         PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
1373         PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
1374         PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1375         PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1376         PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
1377         PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
1378         PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
1379         PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1380         PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1381         PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
1382         PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
1383         PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
1384         PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1385         PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1386         PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
1387         PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
1388         PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1389         PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1390         PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
1391         PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
1392         PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1393         PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1394         PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
1395
1396         /* IPSR11 */
1397         PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
1398         PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
1399         PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1400         PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1401         PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
1402         PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
1403         PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
1404         PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1405         PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1406         PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
1407         PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
1408         PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1409         PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1410         PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1411         PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
1412         PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1413         PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1414         PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1415         PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
1416         PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1417         PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1418         PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1419         PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1420         PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
1421         PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1422         PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1423         PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1424         PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1425         PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
1426         PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1427         PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1428         PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
1429         PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1430         PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1431         PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
1432         PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1433         PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
1434         PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1435         PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
1436         PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1437         PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
1438         PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1439         PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
1440         PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1441         PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
1442         PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1443         PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
1444         PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1445         PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
1446         PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1447         PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
1448         PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
1449         PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
1450         PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
1451         PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
1452         PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
1453         PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
1454
1455         /* IPSR12 */
1456         PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
1457         PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
1458         PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
1459         PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
1460         PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
1461         PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
1462         PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
1463         PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
1464         PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
1465         PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
1466         PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1467         PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
1468         PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1469         PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
1470         PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
1471         PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1472         PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
1473         PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1474         PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
1475         PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
1476         PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1477         PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1478         PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1479         PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
1480         PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
1481         PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1482         PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1483         PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1484         PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
1485         PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
1486         PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1487         PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1488         PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
1489         PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
1490         PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1491         PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
1492         PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
1493         PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1494         PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
1495         PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
1496         PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1497         PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1498         PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
1499         PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1500         PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1501         PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1502         PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1503         PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
1504         PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1505         PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1506         PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1507
1508         /* IPSR13 */
1509         PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1510         PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
1511         PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1512         PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1513         PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1514         PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1515         PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
1516         PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1517         PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1518         PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1519         PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
1520         PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1521         PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1522         PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1523         PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
1524         PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
1525         PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1526         PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1527         PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
1528         PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1529         PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
1530         PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1531         PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
1532         PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1533         PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
1534         PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1535         PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
1536         PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1537         PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
1538         PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1539         PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
1540         PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1541         PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1542         PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1543         PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1544         PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1545         PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
1546         PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1547         PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1548         PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1549         PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1550         PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1551         PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
1552         PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1553         PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
1554         PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1555         PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
1556         PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1557         PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
1558         PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1559         PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
1560         PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1561         PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
1562         PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
1563         PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
1564         PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
1565
1566         /* IPSR14 */
1567         PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
1568         PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
1569         PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
1570         PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
1571         PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
1572         PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
1573         PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
1574         PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
1575         PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
1576         PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
1577         PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
1578         PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
1579         PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
1580         PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
1581         PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
1582         PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
1583         PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
1584         PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
1585         PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1586         PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1587         PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
1588         PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
1589         PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
1590         PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1591         PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1592         PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1593         PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1594         PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1595         PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1596         PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
1597         PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1598         PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1599         PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1600         PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1601         PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
1602         PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1603         PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1604         PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1605         PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
1606         PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1607         PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1608         PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1609         PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
1610         PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1611         PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1612         PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1613         PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1614         PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1615         PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
1616         PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
1617         PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1618         PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1619         PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1620         PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1621         PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1622         PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
1623         PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
1624
1625         /* IPSR15 */
1626         PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1627         PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1628         PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1629         PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
1630         PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1631         PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1632         PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1633         PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1634         PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1635         PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1636         PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1637         PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1638         PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
1639         PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1640         PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1641         PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1642         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1643         PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
1644         PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
1645         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1646         PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1647         PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1648         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1649         PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
1650         PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
1651         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1652         PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1653         PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1654         PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1655         PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1656         PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1657         PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1658         PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1659         PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1660         PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1661         PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1662         PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1663         PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1664         PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1665         PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
1666         PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1667         PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1668         PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1669         PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1670         PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1671         PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1672         PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1673         PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1674         PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1675         PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1676         PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1677
1678         /* IPSR16 */
1679         PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1680         PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1681         PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
1682         PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1683         PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1684         PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1685         PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1686         PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
1687         PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1688         PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1689         PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1690         PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1691         PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
1692         PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1693         PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1694         PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
1695         PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
1696         PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1697         PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1698         PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
1699         PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
1700         PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1701 };
1702
1703 static const struct sh_pfc_pin pinmux_pins[] = {
1704         PINMUX_GPIO_GP_ALL(),
1705 };
1706
1707 /* - ADI -------------------------------------------------------------------- */
1708 static const unsigned int adi_common_pins[] = {
1709         /* ADIDATA, ADICS/SAMP, ADICLK */
1710         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
1711 };
1712 static const unsigned int adi_common_mux[] = {
1713         /* ADIDATA, ADICS/SAMP, ADICLK */
1714         ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
1715 };
1716 static const unsigned int adi_chsel0_pins[] = {
1717         /* ADICHS 0 */
1718         RCAR_GP_PIN(6, 27),
1719 };
1720 static const unsigned int adi_chsel0_mux[] = {
1721         /* ADICHS 0 */
1722         ADICHS0_MARK,
1723 };
1724 static const unsigned int adi_chsel1_pins[] = {
1725         /* ADICHS 1 */
1726         RCAR_GP_PIN(6, 28),
1727 };
1728 static const unsigned int adi_chsel1_mux[] = {
1729         /* ADICHS 1 */
1730         ADICHS1_MARK,
1731 };
1732 static const unsigned int adi_chsel2_pins[] = {
1733         /* ADICHS 2 */
1734         RCAR_GP_PIN(6, 29),
1735 };
1736 static const unsigned int adi_chsel2_mux[] = {
1737         /* ADICHS 2 */
1738         ADICHS2_MARK,
1739 };
1740 static const unsigned int adi_common_b_pins[] = {
1741         /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1742         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1743 };
1744 static const unsigned int adi_common_b_mux[] = {
1745         /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1746         ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
1747 };
1748 static const unsigned int adi_chsel0_b_pins[] = {
1749         /* ADICHS B 0 */
1750         RCAR_GP_PIN(5, 28),
1751 };
1752 static const unsigned int adi_chsel0_b_mux[] = {
1753         /* ADICHS B 0 */
1754         ADICHS0_B_MARK,
1755 };
1756 static const unsigned int adi_chsel1_b_pins[] = {
1757         /* ADICHS B 1 */
1758         RCAR_GP_PIN(5, 29),
1759 };
1760 static const unsigned int adi_chsel1_b_mux[] = {
1761         /* ADICHS B 1 */
1762         ADICHS1_B_MARK,
1763 };
1764 static const unsigned int adi_chsel2_b_pins[] = {
1765         /* ADICHS B 2 */
1766         RCAR_GP_PIN(5, 30),
1767 };
1768 static const unsigned int adi_chsel2_b_mux[] = {
1769         /* ADICHS B 2 */
1770         ADICHS2_B_MARK,
1771 };
1772
1773 /* - Audio Clock ------------------------------------------------------------ */
1774 static const unsigned int audio_clk_a_pins[] = {
1775         /* CLK */
1776         RCAR_GP_PIN(2, 28),
1777 };
1778
1779 static const unsigned int audio_clk_a_mux[] = {
1780         AUDIO_CLKA_MARK,
1781 };
1782
1783 static const unsigned int audio_clk_b_pins[] = {
1784         /* CLK */
1785         RCAR_GP_PIN(2, 29),
1786 };
1787
1788 static const unsigned int audio_clk_b_mux[] = {
1789         AUDIO_CLKB_MARK,
1790 };
1791
1792 static const unsigned int audio_clk_b_b_pins[] = {
1793         /* CLK */
1794         RCAR_GP_PIN(7, 20),
1795 };
1796
1797 static const unsigned int audio_clk_b_b_mux[] = {
1798         AUDIO_CLKB_B_MARK,
1799 };
1800
1801 static const unsigned int audio_clk_c_pins[] = {
1802         /* CLK */
1803         RCAR_GP_PIN(2, 30),
1804 };
1805
1806 static const unsigned int audio_clk_c_mux[] = {
1807         AUDIO_CLKC_MARK,
1808 };
1809
1810 static const unsigned int audio_clkout_pins[] = {
1811         /* CLK */
1812         RCAR_GP_PIN(2, 31),
1813 };
1814
1815 static const unsigned int audio_clkout_mux[] = {
1816         AUDIO_CLKOUT_MARK,
1817 };
1818
1819 /* - AVB -------------------------------------------------------------------- */
1820 static const unsigned int avb_link_pins[] = {
1821         RCAR_GP_PIN(5, 14),
1822 };
1823 static const unsigned int avb_link_mux[] = {
1824         AVB_LINK_MARK,
1825 };
1826 static const unsigned int avb_magic_pins[] = {
1827         RCAR_GP_PIN(5, 11),
1828 };
1829 static const unsigned int avb_magic_mux[] = {
1830         AVB_MAGIC_MARK,
1831 };
1832 static const unsigned int avb_phy_int_pins[] = {
1833         RCAR_GP_PIN(5, 16),
1834 };
1835 static const unsigned int avb_phy_int_mux[] = {
1836         AVB_PHY_INT_MARK,
1837 };
1838 static const unsigned int avb_mdio_pins[] = {
1839         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1840 };
1841 static const unsigned int avb_mdio_mux[] = {
1842         AVB_MDC_MARK, AVB_MDIO_MARK,
1843 };
1844 static const unsigned int avb_mii_pins[] = {
1845         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1846         RCAR_GP_PIN(5, 21),
1847
1848         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1849         RCAR_GP_PIN(5, 3),
1850
1851         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1852         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1853         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1854 };
1855 static const unsigned int avb_mii_mux[] = {
1856         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1857         AVB_TXD3_MARK,
1858
1859         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1860         AVB_RXD3_MARK,
1861
1862         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1863         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1864         AVB_TX_CLK_MARK, AVB_COL_MARK,
1865 };
1866 static const unsigned int avb_gmii_pins[] = {
1867         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1868         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1869         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1870
1871         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1872         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1873         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1874
1875         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1876         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1877         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1878         RCAR_GP_PIN(5, 29),
1879 };
1880 static const unsigned int avb_gmii_mux[] = {
1881         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1882         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1883         AVB_TXD6_MARK, AVB_TXD7_MARK,
1884
1885         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1886         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1887         AVB_RXD6_MARK, AVB_RXD7_MARK,
1888
1889         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1890         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1891         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1892         AVB_COL_MARK,
1893 };
1894
1895 /* - CAN -------------------------------------------------------------------- */
1896
1897 static const unsigned int can0_data_pins[] = {
1898         /* TX, RX */
1899         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1900 };
1901
1902 static const unsigned int can0_data_mux[] = {
1903         CAN0_TX_MARK, CAN0_RX_MARK,
1904 };
1905
1906 static const unsigned int can0_data_b_pins[] = {
1907         /* TX, RX */
1908         RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1909 };
1910
1911 static const unsigned int can0_data_b_mux[] = {
1912         CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1913 };
1914
1915 static const unsigned int can0_data_c_pins[] = {
1916         /* TX, RX */
1917         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1918 };
1919
1920 static const unsigned int can0_data_c_mux[] = {
1921         CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1922 };
1923
1924 static const unsigned int can0_data_d_pins[] = {
1925         /* TX, RX */
1926         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1927 };
1928
1929 static const unsigned int can0_data_d_mux[] = {
1930         CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1931 };
1932
1933 static const unsigned int can0_data_e_pins[] = {
1934         /* TX, RX */
1935         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1936 };
1937
1938 static const unsigned int can0_data_e_mux[] = {
1939         CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1940 };
1941
1942 static const unsigned int can0_data_f_pins[] = {
1943         /* TX, RX */
1944         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1945 };
1946
1947 static const unsigned int can0_data_f_mux[] = {
1948         CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1949 };
1950
1951 static const unsigned int can1_data_pins[] = {
1952         /* TX, RX */
1953          RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1954 };
1955
1956 static const unsigned int can1_data_mux[] = {
1957         CAN1_TX_MARK, CAN1_RX_MARK,
1958 };
1959
1960 static const unsigned int can1_data_b_pins[] = {
1961         /* TX, RX */
1962         RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1963 };
1964
1965 static const unsigned int can1_data_b_mux[] = {
1966         CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1967 };
1968
1969 static const unsigned int can1_data_c_pins[] = {
1970         /* TX, RX */
1971         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1972 };
1973
1974 static const unsigned int can1_data_c_mux[] = {
1975         CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1976 };
1977
1978 static const unsigned int can1_data_d_pins[] = {
1979         /* TX, RX */
1980          RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1981 };
1982
1983 static const unsigned int can1_data_d_mux[] = {
1984         CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1985 };
1986
1987 static const unsigned int can_clk_pins[] = {
1988         /* CLK */
1989         RCAR_GP_PIN(7, 2),
1990 };
1991
1992 static const unsigned int can_clk_mux[] = {
1993         CAN_CLK_MARK,
1994 };
1995
1996 static const unsigned int can_clk_b_pins[] = {
1997         /* CLK */
1998         RCAR_GP_PIN(5, 21),
1999 };
2000
2001 static const unsigned int can_clk_b_mux[] = {
2002         CAN_CLK_B_MARK,
2003 };
2004
2005 static const unsigned int can_clk_c_pins[] = {
2006         /* CLK */
2007         RCAR_GP_PIN(4, 30),
2008 };
2009
2010 static const unsigned int can_clk_c_mux[] = {
2011         CAN_CLK_C_MARK,
2012 };
2013
2014 static const unsigned int can_clk_d_pins[] = {
2015         /* CLK */
2016         RCAR_GP_PIN(7, 19),
2017 };
2018
2019 static const unsigned int can_clk_d_mux[] = {
2020         CAN_CLK_D_MARK,
2021 };
2022
2023 /* - DU --------------------------------------------------------------------- */
2024 static const unsigned int du_rgb666_pins[] = {
2025         /* R[7:2], G[7:2], B[7:2] */
2026         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
2027         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
2028         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2029         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2030         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2031         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2032 };
2033 static const unsigned int du_rgb666_mux[] = {
2034         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2035         DU1_DR3_MARK, DU1_DR2_MARK,
2036         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2037         DU1_DG3_MARK, DU1_DG2_MARK,
2038         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2039         DU1_DB3_MARK, DU1_DB2_MARK,
2040 };
2041 static const unsigned int du_rgb888_pins[] = {
2042         /* R[7:0], G[7:0], B[7:0] */
2043         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
2044         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
2045         RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
2046         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2047         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2048         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
2049         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2050         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2051         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2052 };
2053 static const unsigned int du_rgb888_mux[] = {
2054         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2055         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
2056         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2057         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
2058         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2059         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
2060 };
2061 static const unsigned int du_clk_out_0_pins[] = {
2062         /* CLKOUT */
2063         RCAR_GP_PIN(3, 25),
2064 };
2065 static const unsigned int du_clk_out_0_mux[] = {
2066         DU1_DOTCLKOUT0_MARK
2067 };
2068 static const unsigned int du_clk_out_1_pins[] = {
2069         /* CLKOUT */
2070         RCAR_GP_PIN(3, 26),
2071 };
2072 static const unsigned int du_clk_out_1_mux[] = {
2073         DU1_DOTCLKOUT1_MARK
2074 };
2075 static const unsigned int du_sync_pins[] = {
2076         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2077         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
2078 };
2079 static const unsigned int du_sync_mux[] = {
2080         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
2081 };
2082 static const unsigned int du_oddf_pins[] = {
2083         /* EXDISP/EXODDF/EXCDE */
2084         RCAR_GP_PIN(3, 29),
2085 };
2086 static const unsigned int du_oddf_mux[] = {
2087         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
2088 };
2089 static const unsigned int du_cde_pins[] = {
2090         /* CDE */
2091         RCAR_GP_PIN(3, 31),
2092 };
2093 static const unsigned int du_cde_mux[] = {
2094         DU1_CDE_MARK,
2095 };
2096 static const unsigned int du_disp_pins[] = {
2097         /* DISP */
2098         RCAR_GP_PIN(3, 30),
2099 };
2100 static const unsigned int du_disp_mux[] = {
2101         DU1_DISP_MARK,
2102 };
2103 static const unsigned int du0_clk_in_pins[] = {
2104         /* CLKIN */
2105         RCAR_GP_PIN(6, 31),
2106 };
2107 static const unsigned int du0_clk_in_mux[] = {
2108         DU0_DOTCLKIN_MARK
2109 };
2110 static const unsigned int du1_clk_in_pins[] = {
2111         /* CLKIN */
2112         RCAR_GP_PIN(3, 24),
2113 };
2114 static const unsigned int du1_clk_in_mux[] = {
2115         DU1_DOTCLKIN_MARK
2116 };
2117 static const unsigned int du1_clk_in_b_pins[] = {
2118         /* CLKIN */
2119         RCAR_GP_PIN(7, 19),
2120 };
2121 static const unsigned int du1_clk_in_b_mux[] = {
2122         DU1_DOTCLKIN_B_MARK,
2123 };
2124 static const unsigned int du1_clk_in_c_pins[] = {
2125         /* CLKIN */
2126         RCAR_GP_PIN(7, 20),
2127 };
2128 static const unsigned int du1_clk_in_c_mux[] = {
2129         DU1_DOTCLKIN_C_MARK,
2130 };
2131 /* - ETH -------------------------------------------------------------------- */
2132 static const unsigned int eth_link_pins[] = {
2133         /* LINK */
2134         RCAR_GP_PIN(5, 18),
2135 };
2136 static const unsigned int eth_link_mux[] = {
2137         ETH_LINK_MARK,
2138 };
2139 static const unsigned int eth_magic_pins[] = {
2140         /* MAGIC */
2141         RCAR_GP_PIN(5, 22),
2142 };
2143 static const unsigned int eth_magic_mux[] = {
2144         ETH_MAGIC_MARK,
2145 };
2146 static const unsigned int eth_mdio_pins[] = {
2147         /* MDC, MDIO */
2148         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2149 };
2150 static const unsigned int eth_mdio_mux[] = {
2151         ETH_MDC_MARK, ETH_MDIO_MARK,
2152 };
2153 static const unsigned int eth_rmii_pins[] = {
2154         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2155         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2156         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2157         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2158 };
2159 static const unsigned int eth_rmii_mux[] = {
2160         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2161         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2162 };
2163
2164 /* - HSCIF0 ----------------------------------------------------------------- */
2165 static const unsigned int hscif0_data_pins[] = {
2166         /* RX, TX */
2167         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2168 };
2169 static const unsigned int hscif0_data_mux[] = {
2170         HRX0_MARK, HTX0_MARK,
2171 };
2172 static const unsigned int hscif0_clk_pins[] = {
2173         /* SCK */
2174         RCAR_GP_PIN(7, 2),
2175 };
2176 static const unsigned int hscif0_clk_mux[] = {
2177         HSCK0_MARK,
2178 };
2179 static const unsigned int hscif0_ctrl_pins[] = {
2180         /* RTS, CTS */
2181         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2182 };
2183 static const unsigned int hscif0_ctrl_mux[] = {
2184         HRTS0_N_MARK, HCTS0_N_MARK,
2185 };
2186 static const unsigned int hscif0_data_b_pins[] = {
2187         /* RX, TX */
2188         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2189 };
2190 static const unsigned int hscif0_data_b_mux[] = {
2191         HRX0_B_MARK, HTX0_B_MARK,
2192 };
2193 static const unsigned int hscif0_ctrl_b_pins[] = {
2194         /* RTS, CTS */
2195         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2196 };
2197 static const unsigned int hscif0_ctrl_b_mux[] = {
2198         HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2199 };
2200 static const unsigned int hscif0_data_c_pins[] = {
2201         /* RX, TX */
2202         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2203 };
2204 static const unsigned int hscif0_data_c_mux[] = {
2205         HRX0_C_MARK, HTX0_C_MARK,
2206 };
2207 static const unsigned int hscif0_clk_c_pins[] = {
2208         /* SCK */
2209         RCAR_GP_PIN(5, 31),
2210 };
2211 static const unsigned int hscif0_clk_c_mux[] = {
2212         HSCK0_C_MARK,
2213 };
2214 /* - HSCIF1 ----------------------------------------------------------------- */
2215 static const unsigned int hscif1_data_pins[] = {
2216         /* RX, TX */
2217         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2218 };
2219 static const unsigned int hscif1_data_mux[] = {
2220         HRX1_MARK, HTX1_MARK,
2221 };
2222 static const unsigned int hscif1_clk_pins[] = {
2223         /* SCK */
2224         RCAR_GP_PIN(7, 7),
2225 };
2226 static const unsigned int hscif1_clk_mux[] = {
2227         HSCK1_MARK,
2228 };
2229 static const unsigned int hscif1_ctrl_pins[] = {
2230         /* RTS, CTS */
2231         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2232 };
2233 static const unsigned int hscif1_ctrl_mux[] = {
2234         HRTS1_N_MARK, HCTS1_N_MARK,
2235 };
2236 static const unsigned int hscif1_data_b_pins[] = {
2237         /* RX, TX */
2238         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2239 };
2240 static const unsigned int hscif1_data_b_mux[] = {
2241         HRX1_B_MARK, HTX1_B_MARK,
2242 };
2243 static const unsigned int hscif1_data_c_pins[] = {
2244         /* RX, TX */
2245         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2246 };
2247 static const unsigned int hscif1_data_c_mux[] = {
2248         HRX1_C_MARK, HTX1_C_MARK,
2249 };
2250 static const unsigned int hscif1_clk_c_pins[] = {
2251         /* SCK */
2252         RCAR_GP_PIN(7, 16),
2253 };
2254 static const unsigned int hscif1_clk_c_mux[] = {
2255         HSCK1_C_MARK,
2256 };
2257 static const unsigned int hscif1_ctrl_c_pins[] = {
2258         /* RTS, CTS */
2259         RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2260 };
2261 static const unsigned int hscif1_ctrl_c_mux[] = {
2262         HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2263 };
2264 static const unsigned int hscif1_data_d_pins[] = {
2265         /* RX, TX */
2266         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2267 };
2268 static const unsigned int hscif1_data_d_mux[] = {
2269         HRX1_D_MARK, HTX1_D_MARK,
2270 };
2271 static const unsigned int hscif1_data_e_pins[] = {
2272         /* RX, TX */
2273         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2274 };
2275 static const unsigned int hscif1_data_e_mux[] = {
2276         HRX1_C_MARK, HTX1_C_MARK,
2277 };
2278 static const unsigned int hscif1_clk_e_pins[] = {
2279         /* SCK */
2280         RCAR_GP_PIN(2, 6),
2281 };
2282 static const unsigned int hscif1_clk_e_mux[] = {
2283         HSCK1_E_MARK,
2284 };
2285 static const unsigned int hscif1_ctrl_e_pins[] = {
2286         /* RTS, CTS */
2287         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2288 };
2289 static const unsigned int hscif1_ctrl_e_mux[] = {
2290         HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2291 };
2292 /* - HSCIF2 ----------------------------------------------------------------- */
2293 static const unsigned int hscif2_data_pins[] = {
2294         /* RX, TX */
2295         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2296 };
2297 static const unsigned int hscif2_data_mux[] = {
2298         HRX2_MARK, HTX2_MARK,
2299 };
2300 static const unsigned int hscif2_clk_pins[] = {
2301         /* SCK */
2302         RCAR_GP_PIN(4, 15),
2303 };
2304 static const unsigned int hscif2_clk_mux[] = {
2305         HSCK2_MARK,
2306 };
2307 static const unsigned int hscif2_ctrl_pins[] = {
2308         /* RTS, CTS */
2309         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2310 };
2311 static const unsigned int hscif2_ctrl_mux[] = {
2312         HRTS2_N_MARK, HCTS2_N_MARK,
2313 };
2314 static const unsigned int hscif2_data_b_pins[] = {
2315         /* RX, TX */
2316         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2317 };
2318 static const unsigned int hscif2_data_b_mux[] = {
2319         HRX2_B_MARK, HTX2_B_MARK,
2320 };
2321 static const unsigned int hscif2_ctrl_b_pins[] = {
2322         /* RTS, CTS */
2323         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2324 };
2325 static const unsigned int hscif2_ctrl_b_mux[] = {
2326         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2327 };
2328 static const unsigned int hscif2_data_c_pins[] = {
2329         /* RX, TX */
2330         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2331 };
2332 static const unsigned int hscif2_data_c_mux[] = {
2333         HRX2_C_MARK, HTX2_C_MARK,
2334 };
2335 static const unsigned int hscif2_clk_c_pins[] = {
2336         /* SCK */
2337         RCAR_GP_PIN(5, 31),
2338 };
2339 static const unsigned int hscif2_clk_c_mux[] = {
2340         HSCK2_C_MARK,
2341 };
2342 static const unsigned int hscif2_data_d_pins[] = {
2343         /* RX, TX */
2344         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2345 };
2346 static const unsigned int hscif2_data_d_mux[] = {
2347         HRX2_B_MARK, HTX2_D_MARK,
2348 };
2349 /* - I2C0 ------------------------------------------------------------------- */
2350 static const unsigned int i2c0_pins[] = {
2351         /* SCL, SDA */
2352         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2353 };
2354 static const unsigned int i2c0_mux[] = {
2355         I2C0_SCL_MARK, I2C0_SDA_MARK,
2356 };
2357 static const unsigned int i2c0_b_pins[] = {
2358         /* SCL, SDA */
2359         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2360 };
2361 static const unsigned int i2c0_b_mux[] = {
2362         I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2363 };
2364 static const unsigned int i2c0_c_pins[] = {
2365         /* SCL, SDA */
2366         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2367 };
2368 static const unsigned int i2c0_c_mux[] = {
2369         I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2370 };
2371 /* - I2C1 ------------------------------------------------------------------- */
2372 static const unsigned int i2c1_pins[] = {
2373         /* SCL, SDA */
2374         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2375 };
2376 static const unsigned int i2c1_mux[] = {
2377         I2C1_SCL_MARK, I2C1_SDA_MARK,
2378 };
2379 static const unsigned int i2c1_b_pins[] = {
2380         /* SCL, SDA */
2381         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2382 };
2383 static const unsigned int i2c1_b_mux[] = {
2384         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2385 };
2386 static const unsigned int i2c1_c_pins[] = {
2387         /* SCL, SDA */
2388         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2389 };
2390 static const unsigned int i2c1_c_mux[] = {
2391         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2392 };
2393 static const unsigned int i2c1_d_pins[] = {
2394         /* SCL, SDA */
2395         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2396 };
2397 static const unsigned int i2c1_d_mux[] = {
2398         I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2399 };
2400 static const unsigned int i2c1_e_pins[] = {
2401         /* SCL, SDA */
2402         RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2403 };
2404 static const unsigned int i2c1_e_mux[] = {
2405         I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2406 };
2407 /* - I2C2 ------------------------------------------------------------------- */
2408 static const unsigned int i2c2_pins[] = {
2409         /* SCL, SDA */
2410         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2411 };
2412 static const unsigned int i2c2_mux[] = {
2413         I2C2_SCL_MARK, I2C2_SDA_MARK,
2414 };
2415 static const unsigned int i2c2_b_pins[] = {
2416         /* SCL, SDA */
2417         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2418 };
2419 static const unsigned int i2c2_b_mux[] = {
2420         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2421 };
2422 static const unsigned int i2c2_c_pins[] = {
2423         /* SCL, SDA */
2424         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2425 };
2426 static const unsigned int i2c2_c_mux[] = {
2427         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2428 };
2429 static const unsigned int i2c2_d_pins[] = {
2430         /* SCL, SDA */
2431         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2432 };
2433 static const unsigned int i2c2_d_mux[] = {
2434         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2435 };
2436 /* - I2C3 ------------------------------------------------------------------- */
2437 static const unsigned int i2c3_pins[] = {
2438         /* SCL, SDA */
2439         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2440 };
2441 static const unsigned int i2c3_mux[] = {
2442         I2C3_SCL_MARK, I2C3_SDA_MARK,
2443 };
2444 static const unsigned int i2c3_b_pins[] = {
2445         /* SCL, SDA */
2446         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2447 };
2448 static const unsigned int i2c3_b_mux[] = {
2449         I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2450 };
2451 static const unsigned int i2c3_c_pins[] = {
2452         /* SCL, SDA */
2453         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2454 };
2455 static const unsigned int i2c3_c_mux[] = {
2456         I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2457 };
2458 static const unsigned int i2c3_d_pins[] = {
2459         /* SCL, SDA */
2460         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2461 };
2462 static const unsigned int i2c3_d_mux[] = {
2463         I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2464 };
2465 /* - I2C4 ------------------------------------------------------------------- */
2466 static const unsigned int i2c4_pins[] = {
2467         /* SCL, SDA */
2468         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2469 };
2470 static const unsigned int i2c4_mux[] = {
2471         I2C4_SCL_MARK, I2C4_SDA_MARK,
2472 };
2473 static const unsigned int i2c4_b_pins[] = {
2474         /* SCL, SDA */
2475         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2476 };
2477 static const unsigned int i2c4_b_mux[] = {
2478         I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2479 };
2480 static const unsigned int i2c4_c_pins[] = {
2481         /* SCL, SDA */
2482         RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2483 };
2484 static const unsigned int i2c4_c_mux[] = {
2485         I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2486 };
2487 /* - I2C7 ------------------------------------------------------------------- */
2488 static const unsigned int i2c7_pins[] = {
2489         /* SCL, SDA */
2490         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2491 };
2492 static const unsigned int i2c7_mux[] = {
2493         IIC0_SCL_MARK, IIC0_SDA_MARK,
2494 };
2495 static const unsigned int i2c7_b_pins[] = {
2496         /* SCL, SDA */
2497         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2498 };
2499 static const unsigned int i2c7_b_mux[] = {
2500         IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
2501 };
2502 static const unsigned int i2c7_c_pins[] = {
2503         /* SCL, SDA */
2504         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2505 };
2506 static const unsigned int i2c7_c_mux[] = {
2507         IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
2508 };
2509 /* - I2C8 ------------------------------------------------------------------- */
2510 static const unsigned int i2c8_pins[] = {
2511         /* SCL, SDA */
2512         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2513 };
2514 static const unsigned int i2c8_mux[] = {
2515         IIC1_SCL_MARK, IIC1_SDA_MARK,
2516 };
2517 static const unsigned int i2c8_b_pins[] = {
2518         /* SCL, SDA */
2519         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2520 };
2521 static const unsigned int i2c8_b_mux[] = {
2522         IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2523 };
2524 static const unsigned int i2c8_c_pins[] = {
2525         /* SCL, SDA */
2526         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2527 };
2528 static const unsigned int i2c8_c_mux[] = {
2529         IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2530 };
2531 /* - INTC ------------------------------------------------------------------- */
2532 static const unsigned int intc_irq0_pins[] = {
2533         /* IRQ */
2534         RCAR_GP_PIN(7, 10),
2535 };
2536 static const unsigned int intc_irq0_mux[] = {
2537         IRQ0_MARK,
2538 };
2539 static const unsigned int intc_irq1_pins[] = {
2540         /* IRQ */
2541         RCAR_GP_PIN(7, 11),
2542 };
2543 static const unsigned int intc_irq1_mux[] = {
2544         IRQ1_MARK,
2545 };
2546 static const unsigned int intc_irq2_pins[] = {
2547         /* IRQ */
2548         RCAR_GP_PIN(7, 12),
2549 };
2550 static const unsigned int intc_irq2_mux[] = {
2551         IRQ2_MARK,
2552 };
2553 static const unsigned int intc_irq3_pins[] = {
2554         /* IRQ */
2555         RCAR_GP_PIN(7, 13),
2556 };
2557 static const unsigned int intc_irq3_mux[] = {
2558         IRQ3_MARK,
2559 };
2560 /* - MLB+ ------------------------------------------------------------------- */
2561 static const unsigned int mlb_3pin_pins[] = {
2562         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2563 };
2564 static const unsigned int mlb_3pin_mux[] = {
2565         MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2566 };
2567 /* - MMCIF ------------------------------------------------------------------ */
2568 static const unsigned int mmc_data1_pins[] = {
2569         /* D[0] */
2570         RCAR_GP_PIN(6, 18),
2571 };
2572 static const unsigned int mmc_data1_mux[] = {
2573         MMC_D0_MARK,
2574 };
2575 static const unsigned int mmc_data4_pins[] = {
2576         /* D[0:3] */
2577         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2578         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2579 };
2580 static const unsigned int mmc_data4_mux[] = {
2581         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2582 };
2583 static const unsigned int mmc_data8_pins[] = {
2584         /* D[0:7] */
2585         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2586         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2587         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2588         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2589 };
2590 static const unsigned int mmc_data8_mux[] = {
2591         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2592         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2593 };
2594 static const unsigned int mmc_data8_b_pins[] = {
2595         /* D[0:7] */
2596         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2597         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2598         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2599         RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
2600 };
2601 static const unsigned int mmc_data8_b_mux[] = {
2602         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2603         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
2604 };
2605 static const unsigned int mmc_ctrl_pins[] = {
2606         /* CLK, CMD */
2607         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2608 };
2609 static const unsigned int mmc_ctrl_mux[] = {
2610         MMC_CLK_MARK, MMC_CMD_MARK,
2611 };
2612 /* - MSIOF0 ----------------------------------------------------------------- */
2613 static const unsigned int msiof0_clk_pins[] = {
2614         /* SCK */
2615         RCAR_GP_PIN(6, 24),
2616 };
2617 static const unsigned int msiof0_clk_mux[] = {
2618         MSIOF0_SCK_MARK,
2619 };
2620 static const unsigned int msiof0_sync_pins[] = {
2621         /* SYNC */
2622         RCAR_GP_PIN(6, 25),
2623 };
2624 static const unsigned int msiof0_sync_mux[] = {
2625         MSIOF0_SYNC_MARK,
2626 };
2627 static const unsigned int msiof0_ss1_pins[] = {
2628         /* SS1 */
2629         RCAR_GP_PIN(6, 28),
2630 };
2631 static const unsigned int msiof0_ss1_mux[] = {
2632         MSIOF0_SS1_MARK,
2633 };
2634 static const unsigned int msiof0_ss2_pins[] = {
2635         /* SS2 */
2636         RCAR_GP_PIN(6, 29),
2637 };
2638 static const unsigned int msiof0_ss2_mux[] = {
2639         MSIOF0_SS2_MARK,
2640 };
2641 static const unsigned int msiof0_rx_pins[] = {
2642         /* RXD */
2643         RCAR_GP_PIN(6, 27),
2644 };
2645 static const unsigned int msiof0_rx_mux[] = {
2646         MSIOF0_RXD_MARK,
2647 };
2648 static const unsigned int msiof0_tx_pins[] = {
2649         /* TXD */
2650         RCAR_GP_PIN(6, 26),
2651 };
2652 static const unsigned int msiof0_tx_mux[] = {
2653         MSIOF0_TXD_MARK,
2654 };
2655
2656 static const unsigned int msiof0_clk_b_pins[] = {
2657         /* SCK */
2658         RCAR_GP_PIN(0, 16),
2659 };
2660 static const unsigned int msiof0_clk_b_mux[] = {
2661         MSIOF0_SCK_B_MARK,
2662 };
2663 static const unsigned int msiof0_sync_b_pins[] = {
2664         /* SYNC */
2665         RCAR_GP_PIN(0, 17),
2666 };
2667 static const unsigned int msiof0_sync_b_mux[] = {
2668         MSIOF0_SYNC_B_MARK,
2669 };
2670 static const unsigned int msiof0_ss1_b_pins[] = {
2671         /* SS1 */
2672         RCAR_GP_PIN(0, 18),
2673 };
2674 static const unsigned int msiof0_ss1_b_mux[] = {
2675         MSIOF0_SS1_B_MARK,
2676 };
2677 static const unsigned int msiof0_ss2_b_pins[] = {
2678         /* SS2 */
2679         RCAR_GP_PIN(0, 19),
2680 };
2681 static const unsigned int msiof0_ss2_b_mux[] = {
2682         MSIOF0_SS2_B_MARK,
2683 };
2684 static const unsigned int msiof0_rx_b_pins[] = {
2685         /* RXD */
2686         RCAR_GP_PIN(0, 21),
2687 };
2688 static const unsigned int msiof0_rx_b_mux[] = {
2689         MSIOF0_RXD_B_MARK,
2690 };
2691 static const unsigned int msiof0_tx_b_pins[] = {
2692         /* TXD */
2693         RCAR_GP_PIN(0, 20),
2694 };
2695 static const unsigned int msiof0_tx_b_mux[] = {
2696         MSIOF0_TXD_B_MARK,
2697 };
2698
2699 static const unsigned int msiof0_clk_c_pins[] = {
2700         /* SCK */
2701         RCAR_GP_PIN(5, 26),
2702 };
2703 static const unsigned int msiof0_clk_c_mux[] = {
2704         MSIOF0_SCK_C_MARK,
2705 };
2706 static const unsigned int msiof0_sync_c_pins[] = {
2707         /* SYNC */
2708         RCAR_GP_PIN(5, 25),
2709 };
2710 static const unsigned int msiof0_sync_c_mux[] = {
2711         MSIOF0_SYNC_C_MARK,
2712 };
2713 static const unsigned int msiof0_ss1_c_pins[] = {
2714         /* SS1 */
2715         RCAR_GP_PIN(5, 27),
2716 };
2717 static const unsigned int msiof0_ss1_c_mux[] = {
2718         MSIOF0_SS1_C_MARK,
2719 };
2720 static const unsigned int msiof0_ss2_c_pins[] = {
2721         /* SS2 */
2722         RCAR_GP_PIN(5, 28),
2723 };
2724 static const unsigned int msiof0_ss2_c_mux[] = {
2725         MSIOF0_SS2_C_MARK,
2726 };
2727 static const unsigned int msiof0_rx_c_pins[] = {
2728         /* RXD */
2729         RCAR_GP_PIN(5, 29),
2730 };
2731 static const unsigned int msiof0_rx_c_mux[] = {
2732         MSIOF0_RXD_C_MARK,
2733 };
2734 static const unsigned int msiof0_tx_c_pins[] = {
2735         /* TXD */
2736         RCAR_GP_PIN(5, 30),
2737 };
2738 static const unsigned int msiof0_tx_c_mux[] = {
2739         MSIOF0_TXD_C_MARK,
2740 };
2741 /* - MSIOF1 ----------------------------------------------------------------- */
2742 static const unsigned int msiof1_clk_pins[] = {
2743         /* SCK */
2744         RCAR_GP_PIN(0, 22),
2745 };
2746 static const unsigned int msiof1_clk_mux[] = {
2747         MSIOF1_SCK_MARK,
2748 };
2749 static const unsigned int msiof1_sync_pins[] = {
2750         /* SYNC */
2751         RCAR_GP_PIN(0, 23),
2752 };
2753 static const unsigned int msiof1_sync_mux[] = {
2754         MSIOF1_SYNC_MARK,
2755 };
2756 static const unsigned int msiof1_ss1_pins[] = {
2757         /* SS1 */
2758         RCAR_GP_PIN(0, 24),
2759 };
2760 static const unsigned int msiof1_ss1_mux[] = {
2761         MSIOF1_SS1_MARK,
2762 };
2763 static const unsigned int msiof1_ss2_pins[] = {
2764         /* SS2 */
2765         RCAR_GP_PIN(0, 25),
2766 };
2767 static const unsigned int msiof1_ss2_mux[] = {
2768         MSIOF1_SS2_MARK,
2769 };
2770 static const unsigned int msiof1_rx_pins[] = {
2771         /* RXD */
2772         RCAR_GP_PIN(0, 27),
2773 };
2774 static const unsigned int msiof1_rx_mux[] = {
2775         MSIOF1_RXD_MARK,
2776 };
2777 static const unsigned int msiof1_tx_pins[] = {
2778         /* TXD */
2779         RCAR_GP_PIN(0, 26),
2780 };
2781 static const unsigned int msiof1_tx_mux[] = {
2782         MSIOF1_TXD_MARK,
2783 };
2784
2785 static const unsigned int msiof1_clk_b_pins[] = {
2786         /* SCK */
2787         RCAR_GP_PIN(2, 29),
2788 };
2789 static const unsigned int msiof1_clk_b_mux[] = {
2790         MSIOF1_SCK_B_MARK,
2791 };
2792 static const unsigned int msiof1_sync_b_pins[] = {
2793         /* SYNC */
2794         RCAR_GP_PIN(2, 30),
2795 };
2796 static const unsigned int msiof1_sync_b_mux[] = {
2797         MSIOF1_SYNC_B_MARK,
2798 };
2799 static const unsigned int msiof1_ss1_b_pins[] = {
2800         /* SS1 */
2801         RCAR_GP_PIN(2, 31),
2802 };
2803 static const unsigned int msiof1_ss1_b_mux[] = {
2804         MSIOF1_SS1_B_MARK,
2805 };
2806 static const unsigned int msiof1_ss2_b_pins[] = {
2807         /* SS2 */
2808         RCAR_GP_PIN(7, 16),
2809 };
2810 static const unsigned int msiof1_ss2_b_mux[] = {
2811         MSIOF1_SS2_B_MARK,
2812 };
2813 static const unsigned int msiof1_rx_b_pins[] = {
2814         /* RXD */
2815         RCAR_GP_PIN(7, 18),
2816 };
2817 static const unsigned int msiof1_rx_b_mux[] = {
2818         MSIOF1_RXD_B_MARK,
2819 };
2820 static const unsigned int msiof1_tx_b_pins[] = {
2821         /* TXD */
2822         RCAR_GP_PIN(7, 17),
2823 };
2824 static const unsigned int msiof1_tx_b_mux[] = {
2825         MSIOF1_TXD_B_MARK,
2826 };
2827
2828 static const unsigned int msiof1_clk_c_pins[] = {
2829         /* SCK */
2830         RCAR_GP_PIN(2, 15),
2831 };
2832 static const unsigned int msiof1_clk_c_mux[] = {
2833         MSIOF1_SCK_C_MARK,
2834 };
2835 static const unsigned int msiof1_sync_c_pins[] = {
2836         /* SYNC */
2837         RCAR_GP_PIN(2, 16),
2838 };
2839 static const unsigned int msiof1_sync_c_mux[] = {
2840         MSIOF1_SYNC_C_MARK,
2841 };
2842 static const unsigned int msiof1_rx_c_pins[] = {
2843         /* RXD */
2844         RCAR_GP_PIN(2, 18),
2845 };
2846 static const unsigned int msiof1_rx_c_mux[] = {
2847         MSIOF1_RXD_C_MARK,
2848 };
2849 static const unsigned int msiof1_tx_c_pins[] = {
2850         /* TXD */
2851         RCAR_GP_PIN(2, 17),
2852 };
2853 static const unsigned int msiof1_tx_c_mux[] = {
2854         MSIOF1_TXD_C_MARK,
2855 };
2856
2857 static const unsigned int msiof1_clk_d_pins[] = {
2858         /* SCK */
2859         RCAR_GP_PIN(0, 28),
2860 };
2861 static const unsigned int msiof1_clk_d_mux[] = {
2862         MSIOF1_SCK_D_MARK,
2863 };
2864 static const unsigned int msiof1_sync_d_pins[] = {
2865         /* SYNC */
2866         RCAR_GP_PIN(0, 30),
2867 };
2868 static const unsigned int msiof1_sync_d_mux[] = {
2869         MSIOF1_SYNC_D_MARK,
2870 };
2871 static const unsigned int msiof1_ss1_d_pins[] = {
2872         /* SS1 */
2873         RCAR_GP_PIN(0, 29),
2874 };
2875 static const unsigned int msiof1_ss1_d_mux[] = {
2876         MSIOF1_SS1_D_MARK,
2877 };
2878 static const unsigned int msiof1_rx_d_pins[] = {
2879         /* RXD */
2880         RCAR_GP_PIN(0, 27),
2881 };
2882 static const unsigned int msiof1_rx_d_mux[] = {
2883         MSIOF1_RXD_D_MARK,
2884 };
2885 static const unsigned int msiof1_tx_d_pins[] = {
2886         /* TXD */
2887         RCAR_GP_PIN(0, 26),
2888 };
2889 static const unsigned int msiof1_tx_d_mux[] = {
2890         MSIOF1_TXD_D_MARK,
2891 };
2892
2893 static const unsigned int msiof1_clk_e_pins[] = {
2894         /* SCK */
2895         RCAR_GP_PIN(5, 18),
2896 };
2897 static const unsigned int msiof1_clk_e_mux[] = {
2898         MSIOF1_SCK_E_MARK,
2899 };
2900 static const unsigned int msiof1_sync_e_pins[] = {
2901         /* SYNC */
2902         RCAR_GP_PIN(5, 19),
2903 };
2904 static const unsigned int msiof1_sync_e_mux[] = {
2905         MSIOF1_SYNC_E_MARK,
2906 };
2907 static const unsigned int msiof1_rx_e_pins[] = {
2908         /* RXD */
2909         RCAR_GP_PIN(5, 17),
2910 };
2911 static const unsigned int msiof1_rx_e_mux[] = {
2912         MSIOF1_RXD_E_MARK,
2913 };
2914 static const unsigned int msiof1_tx_e_pins[] = {
2915         /* TXD */
2916         RCAR_GP_PIN(5, 20),
2917 };
2918 static const unsigned int msiof1_tx_e_mux[] = {
2919         MSIOF1_TXD_E_MARK,
2920 };
2921 /* - MSIOF2 ----------------------------------------------------------------- */
2922 static const unsigned int msiof2_clk_pins[] = {
2923         /* SCK */
2924         RCAR_GP_PIN(1, 13),
2925 };
2926 static const unsigned int msiof2_clk_mux[] = {
2927         MSIOF2_SCK_MARK,
2928 };
2929 static const unsigned int msiof2_sync_pins[] = {
2930         /* SYNC */
2931         RCAR_GP_PIN(1, 14),
2932 };
2933 static const unsigned int msiof2_sync_mux[] = {
2934         MSIOF2_SYNC_MARK,
2935 };
2936 static const unsigned int msiof2_ss1_pins[] = {
2937         /* SS1 */
2938         RCAR_GP_PIN(1, 17),
2939 };
2940 static const unsigned int msiof2_ss1_mux[] = {
2941         MSIOF2_SS1_MARK,
2942 };
2943 static const unsigned int msiof2_ss2_pins[] = {
2944         /* SS2 */
2945         RCAR_GP_PIN(1, 18),
2946 };
2947 static const unsigned int msiof2_ss2_mux[] = {
2948         MSIOF2_SS2_MARK,
2949 };
2950 static const unsigned int msiof2_rx_pins[] = {
2951         /* RXD */
2952         RCAR_GP_PIN(1, 16),
2953 };
2954 static const unsigned int msiof2_rx_mux[] = {
2955         MSIOF2_RXD_MARK,
2956 };
2957 static const unsigned int msiof2_tx_pins[] = {
2958         /* TXD */
2959         RCAR_GP_PIN(1, 15),
2960 };
2961 static const unsigned int msiof2_tx_mux[] = {
2962         MSIOF2_TXD_MARK,
2963 };
2964
2965 static const unsigned int msiof2_clk_b_pins[] = {
2966         /* SCK */
2967         RCAR_GP_PIN(3, 0),
2968 };
2969 static const unsigned int msiof2_clk_b_mux[] = {
2970         MSIOF2_SCK_B_MARK,
2971 };
2972 static const unsigned int msiof2_sync_b_pins[] = {
2973         /* SYNC */
2974         RCAR_GP_PIN(3, 1),
2975 };
2976 static const unsigned int msiof2_sync_b_mux[] = {
2977         MSIOF2_SYNC_B_MARK,
2978 };
2979 static const unsigned int msiof2_ss1_b_pins[] = {
2980         /* SS1 */
2981         RCAR_GP_PIN(3, 8),
2982 };
2983 static const unsigned int msiof2_ss1_b_mux[] = {
2984         MSIOF2_SS1_B_MARK,
2985 };
2986 static const unsigned int msiof2_ss2_b_pins[] = {
2987         /* SS2 */
2988         RCAR_GP_PIN(3, 9),
2989 };
2990 static const unsigned int msiof2_ss2_b_mux[] = {
2991         MSIOF2_SS2_B_MARK,
2992 };
2993 static const unsigned int msiof2_rx_b_pins[] = {
2994         /* RXD */
2995         RCAR_GP_PIN(3, 17),
2996 };
2997 static const unsigned int msiof2_rx_b_mux[] = {
2998         MSIOF2_RXD_B_MARK,
2999 };
3000 static const unsigned int msiof2_tx_b_pins[] = {
3001         /* TXD */
3002         RCAR_GP_PIN(3, 16),
3003 };
3004 static const unsigned int msiof2_tx_b_mux[] = {
3005         MSIOF2_TXD_B_MARK,
3006 };
3007
3008 static const unsigned int msiof2_clk_c_pins[] = {
3009         /* SCK */
3010         RCAR_GP_PIN(2, 2),
3011 };
3012 static const unsigned int msiof2_clk_c_mux[] = {
3013         MSIOF2_SCK_C_MARK,
3014 };
3015 static const unsigned int msiof2_sync_c_pins[] = {
3016         /* SYNC */
3017         RCAR_GP_PIN(2, 3),
3018 };
3019 static const unsigned int msiof2_sync_c_mux[] = {
3020         MSIOF2_SYNC_C_MARK,
3021 };
3022 static const unsigned int msiof2_rx_c_pins[] = {
3023         /* RXD */
3024         RCAR_GP_PIN(2, 5),
3025 };
3026 static const unsigned int msiof2_rx_c_mux[] = {
3027         MSIOF2_RXD_C_MARK,
3028 };
3029 static const unsigned int msiof2_tx_c_pins[] = {
3030         /* TXD */
3031         RCAR_GP_PIN(2, 4),
3032 };
3033 static const unsigned int msiof2_tx_c_mux[] = {
3034         MSIOF2_TXD_C_MARK,
3035 };
3036
3037 static const unsigned int msiof2_clk_d_pins[] = {
3038         /* SCK */
3039         RCAR_GP_PIN(2, 14),
3040 };
3041 static const unsigned int msiof2_clk_d_mux[] = {
3042         MSIOF2_SCK_D_MARK,
3043 };
3044 static const unsigned int msiof2_sync_d_pins[] = {
3045         /* SYNC */
3046         RCAR_GP_PIN(2, 15),
3047 };
3048 static const unsigned int msiof2_sync_d_mux[] = {
3049         MSIOF2_SYNC_D_MARK,
3050 };
3051 static const unsigned int msiof2_ss1_d_pins[] = {
3052         /* SS1 */
3053         RCAR_GP_PIN(2, 17),
3054 };
3055 static const unsigned int msiof2_ss1_d_mux[] = {
3056         MSIOF2_SS1_D_MARK,
3057 };
3058 static const unsigned int msiof2_ss2_d_pins[] = {
3059         /* SS2 */
3060         RCAR_GP_PIN(2, 19),
3061 };
3062 static const unsigned int msiof2_ss2_d_mux[] = {
3063         MSIOF2_SS2_D_MARK,
3064 };
3065 static const unsigned int msiof2_rx_d_pins[] = {
3066         /* RXD */
3067         RCAR_GP_PIN(2, 18),
3068 };
3069 static const unsigned int msiof2_rx_d_mux[] = {
3070         MSIOF2_RXD_D_MARK,
3071 };
3072 static const unsigned int msiof2_tx_d_pins[] = {
3073         /* TXD */
3074         RCAR_GP_PIN(2, 16),
3075 };
3076 static const unsigned int msiof2_tx_d_mux[] = {
3077         MSIOF2_TXD_D_MARK,
3078 };
3079
3080 static const unsigned int msiof2_clk_e_pins[] = {
3081         /* SCK */
3082         RCAR_GP_PIN(7, 15),
3083 };
3084 static const unsigned int msiof2_clk_e_mux[] = {
3085         MSIOF2_SCK_E_MARK,
3086 };
3087 static const unsigned int msiof2_sync_e_pins[] = {
3088         /* SYNC */
3089         RCAR_GP_PIN(7, 16),
3090 };
3091 static const unsigned int msiof2_sync_e_mux[] = {
3092         MSIOF2_SYNC_E_MARK,
3093 };
3094 static const unsigned int msiof2_rx_e_pins[] = {
3095         /* RXD */
3096         RCAR_GP_PIN(7, 14),
3097 };
3098 static const unsigned int msiof2_rx_e_mux[] = {
3099         MSIOF2_RXD_E_MARK,
3100 };
3101 static const unsigned int msiof2_tx_e_pins[] = {
3102         /* TXD */
3103         RCAR_GP_PIN(7, 13),
3104 };
3105 static const unsigned int msiof2_tx_e_mux[] = {
3106         MSIOF2_TXD_E_MARK,
3107 };
3108 /* - PWM -------------------------------------------------------------------- */
3109 static const unsigned int pwm0_pins[] = {
3110         RCAR_GP_PIN(6, 14),
3111 };
3112 static const unsigned int pwm0_mux[] = {
3113         PWM0_MARK,
3114 };
3115 static const unsigned int pwm0_b_pins[] = {
3116         RCAR_GP_PIN(5, 30),
3117 };
3118 static const unsigned int pwm0_b_mux[] = {
3119         PWM0_B_MARK,
3120 };
3121 static const unsigned int pwm1_pins[] = {
3122         RCAR_GP_PIN(1, 17),
3123 };
3124 static const unsigned int pwm1_mux[] = {
3125         PWM1_MARK,
3126 };
3127 static const unsigned int pwm1_b_pins[] = {
3128         RCAR_GP_PIN(6, 15),
3129 };
3130 static const unsigned int pwm1_b_mux[] = {
3131         PWM1_B_MARK,
3132 };
3133 static const unsigned int pwm2_pins[] = {
3134         RCAR_GP_PIN(1, 18),
3135 };
3136 static const unsigned int pwm2_mux[] = {
3137         PWM2_MARK,
3138 };
3139 static const unsigned int pwm2_b_pins[] = {
3140         RCAR_GP_PIN(0, 16),
3141 };
3142 static const unsigned int pwm2_b_mux[] = {
3143         PWM2_B_MARK,
3144 };
3145 static const unsigned int pwm3_pins[] = {
3146         RCAR_GP_PIN(1, 24),
3147 };
3148 static const unsigned int pwm3_mux[] = {
3149         PWM3_MARK,
3150 };
3151 static const unsigned int pwm4_pins[] = {
3152         RCAR_GP_PIN(3, 26),
3153 };
3154 static const unsigned int pwm4_mux[] = {
3155         PWM4_MARK,
3156 };
3157 static const unsigned int pwm4_b_pins[] = {
3158         RCAR_GP_PIN(3, 31),
3159 };
3160 static const unsigned int pwm4_b_mux[] = {
3161         PWM4_B_MARK,
3162 };
3163 static const unsigned int pwm5_pins[] = {
3164         RCAR_GP_PIN(7, 21),
3165 };
3166 static const unsigned int pwm5_mux[] = {
3167         PWM5_MARK,
3168 };
3169 static const unsigned int pwm5_b_pins[] = {
3170         RCAR_GP_PIN(7, 20),
3171 };
3172 static const unsigned int pwm5_b_mux[] = {
3173         PWM5_B_MARK,
3174 };
3175 static const unsigned int pwm6_pins[] = {
3176         RCAR_GP_PIN(7, 22),
3177 };
3178 static const unsigned int pwm6_mux[] = {
3179         PWM6_MARK,
3180 };
3181 /* - QSPI ------------------------------------------------------------------- */
3182 static const unsigned int qspi_ctrl_pins[] = {
3183         /* SPCLK, SSL */
3184         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3185 };
3186 static const unsigned int qspi_ctrl_mux[] = {
3187         SPCLK_MARK, SSL_MARK,
3188 };
3189 static const unsigned int qspi_data2_pins[] = {
3190         /* MOSI_IO0, MISO_IO1 */
3191         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3192 };
3193 static const unsigned int qspi_data2_mux[] = {
3194         MOSI_IO0_MARK, MISO_IO1_MARK,
3195 };
3196 static const unsigned int qspi_data4_pins[] = {
3197         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3198         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3199         RCAR_GP_PIN(1, 8),
3200 };
3201 static const unsigned int qspi_data4_mux[] = {
3202         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3203 };
3204
3205 static const unsigned int qspi_ctrl_b_pins[] = {
3206         /* SPCLK, SSL */
3207         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3208 };
3209 static const unsigned int qspi_ctrl_b_mux[] = {
3210         SPCLK_B_MARK, SSL_B_MARK,
3211 };
3212 static const unsigned int qspi_data2_b_pins[] = {
3213         /* MOSI_IO0, MISO_IO1 */
3214         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3215 };
3216 static const unsigned int qspi_data2_b_mux[] = {
3217         MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3218 };
3219 static const unsigned int qspi_data4_b_pins[] = {
3220         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3221         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3222         RCAR_GP_PIN(6, 4),
3223 };
3224 static const unsigned int qspi_data4_b_mux[] = {
3225         SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3226         IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
3227 };
3228 /* - SCIF0 ------------------------------------------------------------------ */
3229 static const unsigned int scif0_data_pins[] = {
3230         /* RX, TX */
3231         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3232 };
3233 static const unsigned int scif0_data_mux[] = {
3234         RX0_MARK, TX0_MARK,
3235 };
3236 static const unsigned int scif0_data_b_pins[] = {
3237         /* RX, TX */
3238         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3239 };
3240 static const unsigned int scif0_data_b_mux[] = {
3241         RX0_B_MARK, TX0_B_MARK,
3242 };
3243 static const unsigned int scif0_data_c_pins[] = {
3244         /* RX, TX */
3245         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3246 };
3247 static const unsigned int scif0_data_c_mux[] = {
3248         RX0_C_MARK, TX0_C_MARK,
3249 };
3250 static const unsigned int scif0_data_d_pins[] = {
3251         /* RX, TX */
3252         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3253 };
3254 static const unsigned int scif0_data_d_mux[] = {
3255         RX0_D_MARK, TX0_D_MARK,
3256 };
3257 static const unsigned int scif0_data_e_pins[] = {
3258         /* RX, TX */
3259         RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3260 };
3261 static const unsigned int scif0_data_e_mux[] = {
3262         RX0_E_MARK, TX0_E_MARK,
3263 };
3264 /* - SCIF1 ------------------------------------------------------------------ */
3265 static const unsigned int scif1_data_pins[] = {
3266         /* RX, TX */
3267         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3268 };
3269 static const unsigned int scif1_data_mux[] = {
3270         RX1_MARK, TX1_MARK,
3271 };
3272 static const unsigned int scif1_data_b_pins[] = {
3273         /* RX, TX */
3274         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3275 };
3276 static const unsigned int scif1_data_b_mux[] = {
3277         RX1_B_MARK, TX1_B_MARK,
3278 };
3279 static const unsigned int scif1_clk_b_pins[] = {
3280         /* SCK */
3281         RCAR_GP_PIN(3, 10),
3282 };
3283 static const unsigned int scif1_clk_b_mux[] = {
3284         SCIF1_SCK_B_MARK,
3285 };
3286 static const unsigned int scif1_data_c_pins[] = {
3287         /* RX, TX */
3288         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3289 };
3290 static const unsigned int scif1_data_c_mux[] = {
3291         RX1_C_MARK, TX1_C_MARK,
3292 };
3293 static const unsigned int scif1_data_d_pins[] = {
3294         /* RX, TX */
3295         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3296 };
3297 static const unsigned int scif1_data_d_mux[] = {
3298         RX1_D_MARK, TX1_D_MARK,
3299 };
3300 /* - SCIF2 ------------------------------------------------------------------ */
3301 static const unsigned int scif2_data_pins[] = {
3302         /* RX, TX */
3303         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3304 };
3305 static const unsigned int scif2_data_mux[] = {
3306         RX2_MARK, TX2_MARK,
3307 };
3308 static const unsigned int scif2_data_b_pins[] = {
3309         /* RX, TX */
3310         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3311 };
3312 static const unsigned int scif2_data_b_mux[] = {
3313         RX2_B_MARK, TX2_B_MARK,
3314 };
3315 static const unsigned int scif2_clk_b_pins[] = {
3316         /* SCK */
3317         RCAR_GP_PIN(3, 18),
3318 };
3319 static const unsigned int scif2_clk_b_mux[] = {
3320         SCIF2_SCK_B_MARK,
3321 };
3322 static const unsigned int scif2_data_c_pins[] = {
3323         /* RX, TX */
3324         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3325 };
3326 static const unsigned int scif2_data_c_mux[] = {
3327         RX2_C_MARK, TX2_C_MARK,
3328 };
3329 static const unsigned int scif2_data_e_pins[] = {
3330         /* RX, TX */
3331         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3332 };
3333 static const unsigned int scif2_data_e_mux[] = {
3334         RX2_E_MARK, TX2_E_MARK,
3335 };
3336 /* - SCIF3 ------------------------------------------------------------------ */
3337 static const unsigned int scif3_data_pins[] = {
3338         /* RX, TX */
3339         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3340 };
3341 static const unsigned int scif3_data_mux[] = {
3342         RX3_MARK, TX3_MARK,
3343 };
3344 static const unsigned int scif3_clk_pins[] = {
3345         /* SCK */
3346         RCAR_GP_PIN(3, 23),
3347 };
3348 static const unsigned int scif3_clk_mux[] = {
3349         SCIF3_SCK_MARK,
3350 };
3351 static const unsigned int scif3_data_b_pins[] = {
3352         /* RX, TX */
3353         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3354 };
3355 static const unsigned int scif3_data_b_mux[] = {
3356         RX3_B_MARK, TX3_B_MARK,
3357 };
3358 static const unsigned int scif3_clk_b_pins[] = {
3359         /* SCK */
3360         RCAR_GP_PIN(4, 8),
3361 };
3362 static const unsigned int scif3_clk_b_mux[] = {
3363         SCIF3_SCK_B_MARK,
3364 };
3365 static const unsigned int scif3_data_c_pins[] = {
3366         /* RX, TX */
3367         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3368 };
3369 static const unsigned int scif3_data_c_mux[] = {
3370         RX3_C_MARK, TX3_C_MARK,
3371 };
3372 static const unsigned int scif3_data_d_pins[] = {
3373         /* RX, TX */
3374         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3375 };
3376 static const unsigned int scif3_data_d_mux[] = {
3377         RX3_D_MARK, TX3_D_MARK,
3378 };
3379 /* - SCIF4 ------------------------------------------------------------------ */
3380 static const unsigned int scif4_data_pins[] = {
3381         /* RX, TX */
3382         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3383 };
3384 static const unsigned int scif4_data_mux[] = {
3385         RX4_MARK, TX4_MARK,
3386 };
3387 static const unsigned int scif4_data_b_pins[] = {
3388         /* RX, TX */
3389         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3390 };
3391 static const unsigned int scif4_data_b_mux[] = {
3392         RX4_B_MARK, TX4_B_MARK,
3393 };
3394 static const unsigned int scif4_data_c_pins[] = {
3395         /* RX, TX */
3396         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3397 };
3398 static const unsigned int scif4_data_c_mux[] = {
3399         RX4_C_MARK, TX4_C_MARK,
3400 };
3401 /* - SCIF5 ------------------------------------------------------------------ */
3402 static const unsigned int scif5_data_pins[] = {
3403         /* RX, TX */
3404         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3405 };
3406 static const unsigned int scif5_data_mux[] = {
3407         RX5_MARK, TX5_MARK,
3408 };
3409 static const unsigned int scif5_data_b_pins[] = {
3410         /* RX, TX */
3411         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3412 };
3413 static const unsigned int scif5_data_b_mux[] = {
3414         RX5_B_MARK, TX5_B_MARK,
3415 };
3416 /* - SCIFA0 ----------------------------------------------------------------- */
3417 static const unsigned int scifa0_data_pins[] = {
3418         /* RXD, TXD */
3419         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3420 };
3421 static const unsigned int scifa0_data_mux[] = {
3422         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3423 };
3424 static const unsigned int scifa0_data_b_pins[] = {
3425         /* RXD, TXD */
3426         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3427 };
3428 static const unsigned int scifa0_data_b_mux[] = {
3429         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3430 };
3431 /* - SCIFA1 ----------------------------------------------------------------- */
3432 static const unsigned int scifa1_data_pins[] = {
3433         /* RXD, TXD */
3434         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3435 };
3436 static const unsigned int scifa1_data_mux[] = {
3437         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3438 };
3439 static const unsigned int scifa1_clk_pins[] = {
3440         /* SCK */
3441         RCAR_GP_PIN(3, 10),
3442 };
3443 static const unsigned int scifa1_clk_mux[] = {
3444         SCIFA1_SCK_MARK,
3445 };
3446 static const unsigned int scifa1_data_b_pins[] = {
3447         /* RXD, TXD */
3448         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3449 };
3450 static const unsigned int scifa1_data_b_mux[] = {
3451         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3452 };
3453 static const unsigned int scifa1_clk_b_pins[] = {
3454         /* SCK */
3455         RCAR_GP_PIN(1, 0),
3456 };
3457 static const unsigned int scifa1_clk_b_mux[] = {
3458         SCIFA1_SCK_B_MARK,
3459 };
3460 static const unsigned int scifa1_data_c_pins[] = {
3461         /* RXD, TXD */
3462         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3463 };
3464 static const unsigned int scifa1_data_c_mux[] = {
3465         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3466 };
3467 /* - SCIFA2 ----------------------------------------------------------------- */
3468 static const unsigned int scifa2_data_pins[] = {
3469         /* RXD, TXD */
3470         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3471 };
3472 static const unsigned int scifa2_data_mux[] = {
3473         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3474 };
3475 static const unsigned int scifa2_clk_pins[] = {
3476         /* SCK */
3477         RCAR_GP_PIN(3, 18),
3478 };
3479 static const unsigned int scifa2_clk_mux[] = {
3480         SCIFA2_SCK_MARK,
3481 };
3482 static const unsigned int scifa2_data_b_pins[] = {
3483         /* RXD, TXD */
3484         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3485 };
3486 static const unsigned int scifa2_data_b_mux[] = {
3487         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3488 };
3489 /* - SCIFA3 ----------------------------------------------------------------- */
3490 static const unsigned int scifa3_data_pins[] = {
3491         /* RXD, TXD */
3492         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3493 };
3494 static const unsigned int scifa3_data_mux[] = {
3495         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3496 };
3497 static const unsigned int scifa3_clk_pins[] = {
3498         /* SCK */
3499         RCAR_GP_PIN(3, 23),
3500 };
3501 static const unsigned int scifa3_clk_mux[] = {
3502         SCIFA3_SCK_MARK,
3503 };
3504 static const unsigned int scifa3_data_b_pins[] = {
3505         /* RXD, TXD */
3506         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3507 };
3508 static const unsigned int scifa3_data_b_mux[] = {
3509         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3510 };
3511 static const unsigned int scifa3_clk_b_pins[] = {
3512         /* SCK */
3513         RCAR_GP_PIN(4, 8),
3514 };
3515 static const unsigned int scifa3_clk_b_mux[] = {
3516         SCIFA3_SCK_B_MARK,
3517 };
3518 static const unsigned int scifa3_data_c_pins[] = {
3519         /* RXD, TXD */
3520         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3521 };
3522 static const unsigned int scifa3_data_c_mux[] = {
3523         SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3524 };
3525 static const unsigned int scifa3_clk_c_pins[] = {
3526         /* SCK */
3527         RCAR_GP_PIN(7, 22),
3528 };
3529 static const unsigned int scifa3_clk_c_mux[] = {
3530         SCIFA3_SCK_C_MARK,
3531 };
3532 /* - SCIFA4 ----------------------------------------------------------------- */
3533 static const unsigned int scifa4_data_pins[] = {
3534         /* RXD, TXD */
3535         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3536 };
3537 static const unsigned int scifa4_data_mux[] = {
3538         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3539 };
3540 static const unsigned int scifa4_data_b_pins[] = {
3541         /* RXD, TXD */
3542         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3543 };
3544 static const unsigned int scifa4_data_b_mux[] = {
3545         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3546 };
3547 static const unsigned int scifa4_data_c_pins[] = {
3548         /* RXD, TXD */
3549         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3550 };
3551 static const unsigned int scifa4_data_c_mux[] = {
3552         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3553 };
3554 /* - SCIFA5 ----------------------------------------------------------------- */
3555 static const unsigned int scifa5_data_pins[] = {
3556         /* RXD, TXD */
3557         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3558 };
3559 static const unsigned int scifa5_data_mux[] = {
3560         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3561 };
3562 static const unsigned int scifa5_data_b_pins[] = {
3563         /* RXD, TXD */
3564         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3565 };
3566 static const unsigned int scifa5_data_b_mux[] = {
3567         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3568 };
3569 static const unsigned int scifa5_data_c_pins[] = {
3570         /* RXD, TXD */
3571         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3572 };
3573 static const unsigned int scifa5_data_c_mux[] = {
3574         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3575 };
3576 /* - SCIFB0 ----------------------------------------------------------------- */
3577 static const unsigned int scifb0_data_pins[] = {
3578         /* RXD, TXD */
3579         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3580 };
3581 static const unsigned int scifb0_data_mux[] = {
3582         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3583 };
3584 static const unsigned int scifb0_clk_pins[] = {
3585         /* SCK */
3586         RCAR_GP_PIN(7, 2),
3587 };
3588 static const unsigned int scifb0_clk_mux[] = {
3589         SCIFB0_SCK_MARK,
3590 };
3591 static const unsigned int scifb0_ctrl_pins[] = {
3592         /* RTS, CTS */
3593         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3594 };
3595 static const unsigned int scifb0_ctrl_mux[] = {
3596         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3597 };
3598 static const unsigned int scifb0_data_b_pins[] = {
3599         /* RXD, TXD */
3600         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3601 };
3602 static const unsigned int scifb0_data_b_mux[] = {
3603         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3604 };
3605 static const unsigned int scifb0_clk_b_pins[] = {
3606         /* SCK */
3607         RCAR_GP_PIN(5, 31),
3608 };
3609 static const unsigned int scifb0_clk_b_mux[] = {
3610         SCIFB0_SCK_B_MARK,
3611 };
3612 static const unsigned int scifb0_ctrl_b_pins[] = {
3613         /* RTS, CTS */
3614         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3615 };
3616 static const unsigned int scifb0_ctrl_b_mux[] = {
3617         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3618 };
3619 static const unsigned int scifb0_data_c_pins[] = {
3620         /* RXD, TXD */
3621         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3622 };
3623 static const unsigned int scifb0_data_c_mux[] = {
3624         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3625 };
3626 static const unsigned int scifb0_clk_c_pins[] = {
3627         /* SCK */
3628         RCAR_GP_PIN(2, 30),
3629 };
3630 static const unsigned int scifb0_clk_c_mux[] = {
3631         SCIFB0_SCK_C_MARK,
3632 };
3633 static const unsigned int scifb0_data_d_pins[] = {
3634         /* RXD, TXD */
3635         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3636 };
3637 static const unsigned int scifb0_data_d_mux[] = {
3638         SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3639 };
3640 static const unsigned int scifb0_clk_d_pins[] = {
3641         /* SCK */
3642         RCAR_GP_PIN(4, 17),
3643 };
3644 static const unsigned int scifb0_clk_d_mux[] = {
3645         SCIFB0_SCK_D_MARK,
3646 };
3647 /* - SCIFB1 ----------------------------------------------------------------- */
3648 static const unsigned int scifb1_data_pins[] = {
3649         /* RXD, TXD */
3650         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3651 };
3652 static const unsigned int scifb1_data_mux[] = {
3653         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3654 };
3655 static const unsigned int scifb1_clk_pins[] = {
3656         /* SCK */
3657         RCAR_GP_PIN(7, 7),
3658 };
3659 static const unsigned int scifb1_clk_mux[] = {
3660         SCIFB1_SCK_MARK,
3661 };
3662 static const unsigned int scifb1_ctrl_pins[] = {
3663         /* RTS, CTS */
3664         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3665 };
3666 static const unsigned int scifb1_ctrl_mux[] = {
3667         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3668 };
3669 static const unsigned int scifb1_data_b_pins[] = {
3670         /* RXD, TXD */
3671         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3672 };
3673 static const unsigned int scifb1_data_b_mux[] = {
3674         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3675 };
3676 static const unsigned int scifb1_clk_b_pins[] = {
3677         /* SCK */
3678         RCAR_GP_PIN(1, 3),
3679 };
3680 static const unsigned int scifb1_clk_b_mux[] = {
3681         SCIFB1_SCK_B_MARK,
3682 };
3683 static const unsigned int scifb1_data_c_pins[] = {
3684         /* RXD, TXD */
3685         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3686 };
3687 static const unsigned int scifb1_data_c_mux[] = {
3688         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3689 };
3690 static const unsigned int scifb1_clk_c_pins[] = {
3691         /* SCK */
3692         RCAR_GP_PIN(7, 11),
3693 };
3694 static const unsigned int scifb1_clk_c_mux[] = {
3695         SCIFB1_SCK_C_MARK,
3696 };
3697 static const unsigned int scifb1_data_d_pins[] = {
3698         /* RXD, TXD */
3699         RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3700 };
3701 static const unsigned int scifb1_data_d_mux[] = {
3702         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3703 };
3704 /* - SCIFB2 ----------------------------------------------------------------- */
3705 static const unsigned int scifb2_data_pins[] = {
3706         /* RXD, TXD */
3707         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3708 };
3709 static const unsigned int scifb2_data_mux[] = {
3710         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3711 };
3712 static const unsigned int scifb2_clk_pins[] = {
3713         /* SCK */
3714         RCAR_GP_PIN(4, 15),
3715 };
3716 static const unsigned int scifb2_clk_mux[] = {
3717         SCIFB2_SCK_MARK,
3718 };
3719 static const unsigned int scifb2_ctrl_pins[] = {
3720         /* RTS, CTS */
3721         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3722 };
3723 static const unsigned int scifb2_ctrl_mux[] = {
3724         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3725 };
3726 static const unsigned int scifb2_data_b_pins[] = {
3727         /* RXD, TXD */
3728         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3729 };
3730 static const unsigned int scifb2_data_b_mux[] = {
3731         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3732 };
3733 static const unsigned int scifb2_clk_b_pins[] = {
3734         /* SCK */
3735         RCAR_GP_PIN(5, 31),
3736 };
3737 static const unsigned int scifb2_clk_b_mux[] = {
3738         SCIFB2_SCK_B_MARK,
3739 };
3740 static const unsigned int scifb2_ctrl_b_pins[] = {
3741         /* RTS, CTS */
3742         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3743 };
3744 static const unsigned int scifb2_ctrl_b_mux[] = {
3745         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3746 };
3747 static const unsigned int scifb2_data_c_pins[] = {
3748         /* RXD, TXD */
3749         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3750 };
3751 static const unsigned int scifb2_data_c_mux[] = {
3752         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3753 };
3754 static const unsigned int scifb2_clk_c_pins[] = {
3755         /* SCK */
3756         RCAR_GP_PIN(5, 27),
3757 };
3758 static const unsigned int scifb2_clk_c_mux[] = {
3759         SCIFB2_SCK_C_MARK,
3760 };
3761 static const unsigned int scifb2_data_d_pins[] = {
3762         /* RXD, TXD */
3763         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3764 };
3765 static const unsigned int scifb2_data_d_mux[] = {
3766         SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3767 };
3768
3769 /* - SCIF Clock ------------------------------------------------------------- */
3770 static const unsigned int scif_clk_pins[] = {
3771         /* SCIF_CLK */
3772         RCAR_GP_PIN(2, 29),
3773 };
3774 static const unsigned int scif_clk_mux[] = {
3775         SCIF_CLK_MARK,
3776 };
3777 static const unsigned int scif_clk_b_pins[] = {
3778         /* SCIF_CLK */
3779         RCAR_GP_PIN(7, 19),
3780 };
3781 static const unsigned int scif_clk_b_mux[] = {
3782         SCIF_CLK_B_MARK,
3783 };
3784
3785 /* - SDHI0 ------------------------------------------------------------------ */
3786 static const unsigned int sdhi0_data1_pins[] = {
3787         /* D0 */
3788         RCAR_GP_PIN(6, 2),
3789 };
3790 static const unsigned int sdhi0_data1_mux[] = {
3791         SD0_DATA0_MARK,
3792 };
3793 static const unsigned int sdhi0_data4_pins[] = {
3794         /* D[0:3] */
3795         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3796         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3797 };
3798 static const unsigned int sdhi0_data4_mux[] = {
3799         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3800 };
3801 static const unsigned int sdhi0_ctrl_pins[] = {
3802         /* CLK, CMD */
3803         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3804 };
3805 static const unsigned int sdhi0_ctrl_mux[] = {
3806         SD0_CLK_MARK, SD0_CMD_MARK,
3807 };
3808 static const unsigned int sdhi0_cd_pins[] = {
3809         /* CD */
3810         RCAR_GP_PIN(6, 6),
3811 };
3812 static const unsigned int sdhi0_cd_mux[] = {
3813         SD0_CD_MARK,
3814 };
3815 static const unsigned int sdhi0_wp_pins[] = {
3816         /* WP */
3817         RCAR_GP_PIN(6, 7),
3818 };
3819 static const unsigned int sdhi0_wp_mux[] = {
3820         SD0_WP_MARK,
3821 };
3822 /* - SDHI1 ------------------------------------------------------------------ */
3823 static const unsigned int sdhi1_data1_pins[] = {
3824         /* D0 */
3825         RCAR_GP_PIN(6, 10),
3826 };
3827 static const unsigned int sdhi1_data1_mux[] = {
3828         SD1_DATA0_MARK,
3829 };
3830 static const unsigned int sdhi1_data4_pins[] = {
3831         /* D[0:3] */
3832         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3833         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3834 };
3835 static const unsigned int sdhi1_data4_mux[] = {
3836         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3837 };
3838 static const unsigned int sdhi1_ctrl_pins[] = {
3839         /* CLK, CMD */
3840         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3841 };
3842 static const unsigned int sdhi1_ctrl_mux[] = {
3843         SD1_CLK_MARK, SD1_CMD_MARK,
3844 };
3845 static const unsigned int sdhi1_cd_pins[] = {
3846         /* CD */
3847         RCAR_GP_PIN(6, 14),
3848 };
3849 static const unsigned int sdhi1_cd_mux[] = {
3850         SD1_CD_MARK,
3851 };
3852 static const unsigned int sdhi1_wp_pins[] = {
3853         /* WP */
3854         RCAR_GP_PIN(6, 15),
3855 };
3856 static const unsigned int sdhi1_wp_mux[] = {
3857         SD1_WP_MARK,
3858 };
3859 /* - SDHI2 ------------------------------------------------------------------ */
3860 static const unsigned int sdhi2_data1_pins[] = {
3861         /* D0 */
3862         RCAR_GP_PIN(6, 18),
3863 };
3864 static const unsigned int sdhi2_data1_mux[] = {
3865         SD2_DATA0_MARK,
3866 };
3867 static const unsigned int sdhi2_data4_pins[] = {
3868         /* D[0:3] */
3869         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3870         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3871 };
3872 static const unsigned int sdhi2_data4_mux[] = {
3873         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3874 };
3875 static const unsigned int sdhi2_ctrl_pins[] = {
3876         /* CLK, CMD */
3877         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3878 };
3879 static const unsigned int sdhi2_ctrl_mux[] = {
3880         SD2_CLK_MARK, SD2_CMD_MARK,
3881 };
3882 static const unsigned int sdhi2_cd_pins[] = {
3883         /* CD */
3884         RCAR_GP_PIN(6, 22),
3885 };
3886 static const unsigned int sdhi2_cd_mux[] = {
3887         SD2_CD_MARK,
3888 };
3889 static const unsigned int sdhi2_wp_pins[] = {
3890         /* WP */
3891         RCAR_GP_PIN(6, 23),
3892 };
3893 static const unsigned int sdhi2_wp_mux[] = {
3894         SD2_WP_MARK,
3895 };
3896
3897 /* - SSI -------------------------------------------------------------------- */
3898 static const unsigned int ssi0_data_pins[] = {
3899         /* SDATA */
3900         RCAR_GP_PIN(2, 2),
3901 };
3902
3903 static const unsigned int ssi0_data_mux[] = {
3904         SSI_SDATA0_MARK,
3905 };
3906
3907 static const unsigned int ssi0_data_b_pins[] = {
3908         /* SDATA */
3909         RCAR_GP_PIN(3, 4),
3910 };
3911
3912 static const unsigned int ssi0_data_b_mux[] = {
3913         SSI_SDATA0_B_MARK,
3914 };
3915
3916 static const unsigned int ssi0129_ctrl_pins[] = {
3917         /* SCK, WS */
3918         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3919 };
3920
3921 static const unsigned int ssi0129_ctrl_mux[] = {
3922         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3923 };
3924
3925 static const unsigned int ssi0129_ctrl_b_pins[] = {
3926         /* SCK, WS */
3927         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3928 };
3929
3930 static const unsigned int ssi0129_ctrl_b_mux[] = {
3931         SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3932 };
3933
3934 static const unsigned int ssi1_data_pins[] = {
3935         /* SDATA */
3936         RCAR_GP_PIN(2, 5),
3937 };
3938
3939 static const unsigned int ssi1_data_mux[] = {
3940         SSI_SDATA1_MARK,
3941 };
3942
3943 static const unsigned int ssi1_data_b_pins[] = {
3944         /* SDATA */
3945         RCAR_GP_PIN(3, 7),
3946 };
3947
3948 static const unsigned int ssi1_data_b_mux[] = {
3949         SSI_SDATA1_B_MARK,
3950 };
3951
3952 static const unsigned int ssi1_ctrl_pins[] = {
3953         /* SCK, WS */
3954         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3955 };
3956
3957 static const unsigned int ssi1_ctrl_mux[] = {
3958         SSI_SCK1_MARK, SSI_WS1_MARK,
3959 };
3960
3961 static const unsigned int ssi1_ctrl_b_pins[] = {
3962         /* SCK, WS */
3963         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3964 };
3965
3966 static const unsigned int ssi1_ctrl_b_mux[] = {
3967         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3968 };
3969
3970 static const unsigned int ssi2_data_pins[] = {
3971         /* SDATA */
3972         RCAR_GP_PIN(2, 8),
3973 };
3974
3975 static const unsigned int ssi2_data_mux[] = {
3976         SSI_SDATA2_MARK,
3977 };
3978
3979 static const unsigned int ssi2_ctrl_pins[] = {
3980         /* SCK, WS */
3981         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3982 };
3983
3984 static const unsigned int ssi2_ctrl_mux[] = {
3985         SSI_SCK2_MARK, SSI_WS2_MARK,
3986 };
3987
3988 static const unsigned int ssi3_data_pins[] = {
3989         /* SDATA */
3990         RCAR_GP_PIN(2, 11),
3991 };
3992
3993 static const unsigned int ssi3_data_mux[] = {
3994         SSI_SDATA3_MARK,
3995 };
3996
3997 static const unsigned int ssi34_ctrl_pins[] = {
3998         /* SCK, WS */
3999         RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
4000 };
4001
4002 static const unsigned int ssi34_ctrl_mux[] = {
4003         SSI_SCK34_MARK, SSI_WS34_MARK,
4004 };
4005
4006 static const unsigned int ssi4_data_pins[] = {
4007         /* SDATA */
4008         RCAR_GP_PIN(2, 14),
4009 };
4010
4011 static const unsigned int ssi4_data_mux[] = {
4012         SSI_SDATA4_MARK,
4013 };
4014
4015 static const unsigned int ssi4_ctrl_pins[] = {
4016         /* SCK, WS */
4017         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
4018 };
4019
4020 static const unsigned int ssi4_ctrl_mux[] = {
4021         SSI_SCK4_MARK, SSI_WS4_MARK,
4022 };
4023
4024 static const unsigned int ssi5_data_pins[] = {
4025         /* SDATA */
4026         RCAR_GP_PIN(2, 17),
4027 };
4028
4029 static const unsigned int ssi5_data_mux[] = {
4030         SSI_SDATA5_MARK,
4031 };
4032
4033 static const unsigned int ssi5_ctrl_pins[] = {
4034         /* SCK, WS */
4035         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4036 };
4037
4038 static const unsigned int ssi5_ctrl_mux[] = {
4039         SSI_SCK5_MARK, SSI_WS5_MARK,
4040 };
4041
4042 static const unsigned int ssi6_data_pins[] = {
4043         /* SDATA */
4044         RCAR_GP_PIN(2, 20),
4045 };
4046
4047 static const unsigned int ssi6_data_mux[] = {
4048         SSI_SDATA6_MARK,
4049 };
4050
4051 static const unsigned int ssi6_ctrl_pins[] = {
4052         /* SCK, WS */
4053         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
4054 };
4055
4056 static const unsigned int ssi6_ctrl_mux[] = {
4057         SSI_SCK6_MARK, SSI_WS6_MARK,
4058 };
4059
4060 static const unsigned int ssi7_data_pins[] = {
4061         /* SDATA */
4062         RCAR_GP_PIN(2, 23),
4063 };
4064
4065 static const unsigned int ssi7_data_mux[] = {
4066         SSI_SDATA7_MARK,
4067 };
4068
4069 static const unsigned int ssi7_data_b_pins[] = {
4070         /* SDATA */
4071         RCAR_GP_PIN(3, 12),
4072 };
4073
4074 static const unsigned int ssi7_data_b_mux[] = {
4075         SSI_SDATA7_B_MARK,
4076 };
4077
4078 static const unsigned int ssi78_ctrl_pins[] = {
4079         /* SCK, WS */
4080         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
4081 };
4082
4083 static const unsigned int ssi78_ctrl_mux[] = {
4084         SSI_SCK78_MARK, SSI_WS78_MARK,
4085 };
4086
4087 static const unsigned int ssi78_ctrl_b_pins[] = {
4088         /* SCK, WS */
4089         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4090 };
4091
4092 static const unsigned int ssi78_ctrl_b_mux[] = {
4093         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
4094 };
4095
4096 static const unsigned int ssi8_data_pins[] = {
4097         /* SDATA */
4098         RCAR_GP_PIN(2, 24),
4099 };
4100
4101 static const unsigned int ssi8_data_mux[] = {
4102         SSI_SDATA8_MARK,
4103 };
4104
4105 static const unsigned int ssi8_data_b_pins[] = {
4106         /* SDATA */
4107         RCAR_GP_PIN(3, 13),
4108 };
4109
4110 static const unsigned int ssi8_data_b_mux[] = {
4111         SSI_SDATA8_B_MARK,
4112 };
4113
4114 static const unsigned int ssi9_data_pins[] = {
4115         /* SDATA */
4116         RCAR_GP_PIN(2, 27),
4117 };
4118
4119 static const unsigned int ssi9_data_mux[] = {
4120         SSI_SDATA9_MARK,
4121 };
4122
4123 static const unsigned int ssi9_data_b_pins[] = {
4124         /* SDATA */
4125         RCAR_GP_PIN(3, 18),
4126 };
4127
4128 static const unsigned int ssi9_data_b_mux[] = {
4129         SSI_SDATA9_B_MARK,
4130 };
4131
4132 static const unsigned int ssi9_ctrl_pins[] = {
4133         /* SCK, WS */
4134         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4135 };
4136
4137 static const unsigned int ssi9_ctrl_mux[] = {
4138         SSI_SCK9_MARK, SSI_WS9_MARK,
4139 };
4140
4141 static const unsigned int ssi9_ctrl_b_pins[] = {
4142         /* SCK, WS */
4143         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4144 };
4145
4146 static const unsigned int ssi9_ctrl_b_mux[] = {
4147         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4148 };
4149
4150 /* - USB0 ------------------------------------------------------------------- */
4151 static const unsigned int usb0_pins[] = {
4152         RCAR_GP_PIN(7, 23), /* PWEN */
4153         RCAR_GP_PIN(7, 24), /* OVC */
4154 };
4155 static const unsigned int usb0_mux[] = {
4156         USB0_PWEN_MARK,
4157         USB0_OVC_MARK,
4158 };
4159 /* - USB1 ------------------------------------------------------------------- */
4160 static const unsigned int usb1_pins[] = {
4161         RCAR_GP_PIN(7, 25), /* PWEN */
4162         RCAR_GP_PIN(6, 30), /* OVC */
4163 };
4164 static const unsigned int usb1_mux[] = {
4165         USB1_PWEN_MARK,
4166         USB1_OVC_MARK,
4167 };
4168 /* - VIN0 ------------------------------------------------------------------- */
4169 static const union vin_data vin0_data_pins = {
4170         .data24 = {
4171                 /* B */
4172                 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4173                 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4174                 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4175                 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4176                 /* G */
4177                 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4178                 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4179                 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4180                 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4181                 /* R */
4182                 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4183                 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4184                 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4185                 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4186         },
4187 };
4188 static const union vin_data vin0_data_mux = {
4189         .data24 = {
4190                 /* B */
4191                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4192                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4193                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4194                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4195                 /* G */
4196                 VI0_G0_MARK, VI0_G1_MARK,
4197                 VI0_G2_MARK, VI0_G3_MARK,
4198                 VI0_G4_MARK, VI0_G5_MARK,
4199                 VI0_G6_MARK, VI0_G7_MARK,
4200                 /* R */
4201                 VI0_R0_MARK, VI0_R1_MARK,
4202                 VI0_R2_MARK, VI0_R3_MARK,
4203                 VI0_R4_MARK, VI0_R5_MARK,
4204                 VI0_R6_MARK, VI0_R7_MARK,
4205         },
4206 };
4207 static const unsigned int vin0_data18_pins[] = {
4208         /* B */
4209         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4210         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4211         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4212         /* G */
4213         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4214         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4215         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4216         /* R */
4217         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4218         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4219         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4220 };
4221 static const unsigned int vin0_data18_mux[] = {
4222         /* B */
4223         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4224         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4225         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4226         /* G */
4227         VI0_G2_MARK, VI0_G3_MARK,
4228         VI0_G4_MARK, VI0_G5_MARK,
4229         VI0_G6_MARK, VI0_G7_MARK,
4230         /* R */
4231         VI0_R2_MARK, VI0_R3_MARK,
4232         VI0_R4_MARK, VI0_R5_MARK,
4233         VI0_R6_MARK, VI0_R7_MARK,
4234 };
4235 static const unsigned int vin0_sync_pins[] = {
4236         RCAR_GP_PIN(4, 3), /* HSYNC */
4237         RCAR_GP_PIN(4, 4), /* VSYNC */
4238 };
4239 static const unsigned int vin0_sync_mux[] = {
4240         VI0_HSYNC_N_MARK,
4241         VI0_VSYNC_N_MARK,
4242 };
4243 static const unsigned int vin0_field_pins[] = {
4244         RCAR_GP_PIN(4, 2),
4245 };
4246 static const unsigned int vin0_field_mux[] = {
4247         VI0_FIELD_MARK,
4248 };
4249 static const unsigned int vin0_clkenb_pins[] = {
4250         RCAR_GP_PIN(4, 1),
4251 };
4252 static const unsigned int vin0_clkenb_mux[] = {
4253         VI0_CLKENB_MARK,
4254 };
4255 static const unsigned int vin0_clk_pins[] = {
4256         RCAR_GP_PIN(4, 0),
4257 };
4258 static const unsigned int vin0_clk_mux[] = {
4259         VI0_CLK_MARK,
4260 };
4261 /* - VIN1 ----------------------------------------------------------------- */
4262 static const unsigned int vin1_data8_pins[] = {
4263         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4264         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4265         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4266         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4267 };
4268 static const unsigned int vin1_data8_mux[] = {
4269         VI1_DATA0_MARK, VI1_DATA1_MARK,
4270         VI1_DATA2_MARK, VI1_DATA3_MARK,
4271         VI1_DATA4_MARK, VI1_DATA5_MARK,
4272         VI1_DATA6_MARK, VI1_DATA7_MARK,
4273 };
4274 static const unsigned int vin1_sync_pins[] = {
4275         RCAR_GP_PIN(5, 0), /* HSYNC */
4276         RCAR_GP_PIN(5, 1), /* VSYNC */
4277 };
4278 static const unsigned int vin1_sync_mux[] = {
4279         VI1_HSYNC_N_MARK,
4280         VI1_VSYNC_N_MARK,
4281 };
4282 static const unsigned int vin1_field_pins[] = {
4283         RCAR_GP_PIN(5, 3),
4284 };
4285 static const unsigned int vin1_field_mux[] = {
4286         VI1_FIELD_MARK,
4287 };
4288 static const unsigned int vin1_clkenb_pins[] = {
4289         RCAR_GP_PIN(5, 2),
4290 };
4291 static const unsigned int vin1_clkenb_mux[] = {
4292         VI1_CLKENB_MARK,
4293 };
4294 static const unsigned int vin1_clk_pins[] = {
4295         RCAR_GP_PIN(5, 4),
4296 };
4297 static const unsigned int vin1_clk_mux[] = {
4298         VI1_CLK_MARK,
4299 };
4300 static const union vin_data vin1_b_data_pins = {
4301         .data24 = {
4302                 /* B */
4303                 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4304                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4305                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4306                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4307                 /* G */
4308                 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4309                 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4310                 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4311                 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4312                 /* R */
4313                 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4314                 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4315                 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4316                 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4317         },
4318 };
4319 static const union vin_data vin1_b_data_mux = {
4320         .data24 = {
4321                 /* B */
4322                 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4323                 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4324                 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4325                 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4326                 /* G */
4327                 VI1_G0_B_MARK, VI1_G1_B_MARK,
4328                 VI1_G2_B_MARK, VI1_G3_B_MARK,
4329                 VI1_G4_B_MARK, VI1_G5_B_MARK,
4330                 VI1_G6_B_MARK, VI1_G7_B_MARK,
4331                 /* R */
4332                 VI1_R0_B_MARK, VI1_R1_B_MARK,
4333                 VI1_R2_B_MARK, VI1_R3_B_MARK,
4334                 VI1_R4_B_MARK, VI1_R5_B_MARK,
4335                 VI1_R6_B_MARK, VI1_R7_B_MARK,
4336         },
4337 };
4338 static const unsigned int vin1_b_data18_pins[] = {
4339         /* B */
4340         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4341         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4342         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4343         /* G */
4344         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4345         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4346         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4347         /* R */
4348         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4349         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4350         RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4351 };
4352 static const unsigned int vin1_b_data18_mux[] = {
4353         /* B */
4354         VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4355         VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4356         VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4357         VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4358         /* G */
4359         VI1_G0_B_MARK, VI1_G1_B_MARK,
4360         VI1_G2_B_MARK, VI1_G3_B_MARK,
4361         VI1_G4_B_MARK, VI1_G5_B_MARK,
4362         VI1_G6_B_MARK, VI1_G7_B_MARK,
4363         /* R */
4364         VI1_R0_B_MARK, VI1_R1_B_MARK,
4365         VI1_R2_B_MARK, VI1_R3_B_MARK,
4366         VI1_R4_B_MARK, VI1_R5_B_MARK,
4367         VI1_R6_B_MARK, VI1_R7_B_MARK,
4368 };
4369 static const unsigned int vin1_b_sync_pins[] = {
4370         RCAR_GP_PIN(3, 17), /* HSYNC */
4371         RCAR_GP_PIN(3, 18), /* VSYNC */
4372 };
4373 static const unsigned int vin1_b_sync_mux[] = {
4374         VI1_HSYNC_N_B_MARK,
4375         VI1_VSYNC_N_B_MARK,
4376 };
4377 static const unsigned int vin1_b_field_pins[] = {
4378         RCAR_GP_PIN(3, 20),
4379 };
4380 static const unsigned int vin1_b_field_mux[] = {
4381         VI1_FIELD_B_MARK,
4382 };
4383 static const unsigned int vin1_b_clkenb_pins[] = {
4384         RCAR_GP_PIN(3, 19),
4385 };
4386 static const unsigned int vin1_b_clkenb_mux[] = {
4387         VI1_CLKENB_B_MARK,
4388 };
4389 static const unsigned int vin1_b_clk_pins[] = {
4390         RCAR_GP_PIN(3, 16),
4391 };
4392 static const unsigned int vin1_b_clk_mux[] = {
4393         VI1_CLK_B_MARK,
4394 };
4395 /* - VIN2 ----------------------------------------------------------------- */
4396 static const unsigned int vin2_data8_pins[] = {
4397         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4398         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4399         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4400         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4401 };
4402 static const unsigned int vin2_data8_mux[] = {
4403         VI2_DATA0_MARK, VI2_DATA1_MARK,
4404         VI2_DATA2_MARK, VI2_DATA3_MARK,
4405         VI2_DATA4_MARK, VI2_DATA5_MARK,
4406         VI2_DATA6_MARK, VI2_DATA7_MARK,
4407 };
4408 static const unsigned int vin2_sync_pins[] = {
4409         RCAR_GP_PIN(4, 15), /* HSYNC */
4410         RCAR_GP_PIN(4, 16), /* VSYNC */
4411 };
4412 static const unsigned int vin2_sync_mux[] = {
4413         VI2_HSYNC_N_MARK,
4414         VI2_VSYNC_N_MARK,
4415 };
4416 static const unsigned int vin2_field_pins[] = {
4417         RCAR_GP_PIN(4, 18),
4418 };
4419 static const unsigned int vin2_field_mux[] = {
4420         VI2_FIELD_MARK,
4421 };
4422 static const unsigned int vin2_clkenb_pins[] = {
4423         RCAR_GP_PIN(4, 17),
4424 };
4425 static const unsigned int vin2_clkenb_mux[] = {
4426         VI2_CLKENB_MARK,
4427 };
4428 static const unsigned int vin2_clk_pins[] = {
4429         RCAR_GP_PIN(4, 19),
4430 };
4431 static const unsigned int vin2_clk_mux[] = {
4432         VI2_CLK_MARK,
4433 };
4434
4435 static const struct {
4436         struct sh_pfc_pin_group common[342];
4437         struct sh_pfc_pin_group r8a779x[9];
4438 } pinmux_groups = {
4439         .common = {
4440                 SH_PFC_PIN_GROUP(audio_clk_a),
4441                 SH_PFC_PIN_GROUP(audio_clk_b),
4442                 SH_PFC_PIN_GROUP(audio_clk_b_b),
4443                 SH_PFC_PIN_GROUP(audio_clk_c),
4444                 SH_PFC_PIN_GROUP(audio_clkout),
4445                 SH_PFC_PIN_GROUP(avb_link),
4446                 SH_PFC_PIN_GROUP(avb_magic),
4447                 SH_PFC_PIN_GROUP(avb_phy_int),
4448                 SH_PFC_PIN_GROUP(avb_mdio),
4449                 SH_PFC_PIN_GROUP(avb_mii),
4450                 SH_PFC_PIN_GROUP(avb_gmii),
4451                 SH_PFC_PIN_GROUP(can0_data),
4452                 SH_PFC_PIN_GROUP(can0_data_b),
4453                 SH_PFC_PIN_GROUP(can0_data_c),
4454                 SH_PFC_PIN_GROUP(can0_data_d),
4455                 SH_PFC_PIN_GROUP(can0_data_e),
4456                 SH_PFC_PIN_GROUP(can0_data_f),
4457                 SH_PFC_PIN_GROUP(can1_data),
4458                 SH_PFC_PIN_GROUP(can1_data_b),
4459                 SH_PFC_PIN_GROUP(can1_data_c),
4460                 SH_PFC_PIN_GROUP(can1_data_d),
4461                 SH_PFC_PIN_GROUP(can_clk),
4462                 SH_PFC_PIN_GROUP(can_clk_b),
4463                 SH_PFC_PIN_GROUP(can_clk_c),
4464                 SH_PFC_PIN_GROUP(can_clk_d),
4465                 SH_PFC_PIN_GROUP(du_rgb666),
4466                 SH_PFC_PIN_GROUP(du_rgb888),
4467                 SH_PFC_PIN_GROUP(du_clk_out_0),
4468                 SH_PFC_PIN_GROUP(du_clk_out_1),
4469                 SH_PFC_PIN_GROUP(du_sync),
4470                 SH_PFC_PIN_GROUP(du_oddf),
4471                 SH_PFC_PIN_GROUP(du_cde),
4472                 SH_PFC_PIN_GROUP(du_disp),
4473                 SH_PFC_PIN_GROUP(du0_clk_in),
4474                 SH_PFC_PIN_GROUP(du1_clk_in),
4475                 SH_PFC_PIN_GROUP(du1_clk_in_b),
4476                 SH_PFC_PIN_GROUP(du1_clk_in_c),
4477                 SH_PFC_PIN_GROUP(eth_link),
4478                 SH_PFC_PIN_GROUP(eth_magic),
4479                 SH_PFC_PIN_GROUP(eth_mdio),
4480                 SH_PFC_PIN_GROUP(eth_rmii),
4481                 SH_PFC_PIN_GROUP(hscif0_data),
4482                 SH_PFC_PIN_GROUP(hscif0_clk),
4483                 SH_PFC_PIN_GROUP(hscif0_ctrl),
4484                 SH_PFC_PIN_GROUP(hscif0_data_b),
4485                 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4486                 SH_PFC_PIN_GROUP(hscif0_data_c),
4487                 SH_PFC_PIN_GROUP(hscif0_clk_c),
4488                 SH_PFC_PIN_GROUP(hscif1_data),
4489                 SH_PFC_PIN_GROUP(hscif1_clk),
4490                 SH_PFC_PIN_GROUP(hscif1_ctrl),
4491                 SH_PFC_PIN_GROUP(hscif1_data_b),
4492                 SH_PFC_PIN_GROUP(hscif1_data_c),
4493                 SH_PFC_PIN_GROUP(hscif1_clk_c),
4494                 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4495                 SH_PFC_PIN_GROUP(hscif1_data_d),
4496                 SH_PFC_PIN_GROUP(hscif1_data_e),
4497                 SH_PFC_PIN_GROUP(hscif1_clk_e),
4498                 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4499                 SH_PFC_PIN_GROUP(hscif2_data),
4500                 SH_PFC_PIN_GROUP(hscif2_clk),
4501                 SH_PFC_PIN_GROUP(hscif2_ctrl),
4502                 SH_PFC_PIN_GROUP(hscif2_data_b),
4503                 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4504                 SH_PFC_PIN_GROUP(hscif2_data_c),
4505                 SH_PFC_PIN_GROUP(hscif2_clk_c),
4506                 SH_PFC_PIN_GROUP(hscif2_data_d),
4507                 SH_PFC_PIN_GROUP(i2c0),
4508                 SH_PFC_PIN_GROUP(i2c0_b),
4509                 SH_PFC_PIN_GROUP(i2c0_c),
4510                 SH_PFC_PIN_GROUP(i2c1),
4511                 SH_PFC_PIN_GROUP(i2c1_b),
4512                 SH_PFC_PIN_GROUP(i2c1_c),
4513                 SH_PFC_PIN_GROUP(i2c1_d),
4514                 SH_PFC_PIN_GROUP(i2c1_e),
4515                 SH_PFC_PIN_GROUP(i2c2),
4516                 SH_PFC_PIN_GROUP(i2c2_b),
4517                 SH_PFC_PIN_GROUP(i2c2_c),
4518                 SH_PFC_PIN_GROUP(i2c2_d),
4519                 SH_PFC_PIN_GROUP(i2c3),
4520                 SH_PFC_PIN_GROUP(i2c3_b),
4521                 SH_PFC_PIN_GROUP(i2c3_c),
4522                 SH_PFC_PIN_GROUP(i2c3_d),
4523                 SH_PFC_PIN_GROUP(i2c4),
4524                 SH_PFC_PIN_GROUP(i2c4_b),
4525                 SH_PFC_PIN_GROUP(i2c4_c),
4526                 SH_PFC_PIN_GROUP(i2c7),
4527                 SH_PFC_PIN_GROUP(i2c7_b),
4528                 SH_PFC_PIN_GROUP(i2c7_c),
4529                 SH_PFC_PIN_GROUP(i2c8),
4530                 SH_PFC_PIN_GROUP(i2c8_b),
4531                 SH_PFC_PIN_GROUP(i2c8_c),
4532                 SH_PFC_PIN_GROUP(intc_irq0),
4533                 SH_PFC_PIN_GROUP(intc_irq1),
4534                 SH_PFC_PIN_GROUP(intc_irq2),
4535                 SH_PFC_PIN_GROUP(intc_irq3),
4536                 SH_PFC_PIN_GROUP(mmc_data1),
4537                 SH_PFC_PIN_GROUP(mmc_data4),
4538                 SH_PFC_PIN_GROUP(mmc_data8),
4539                 SH_PFC_PIN_GROUP(mmc_data8_b),
4540                 SH_PFC_PIN_GROUP(mmc_ctrl),
4541                 SH_PFC_PIN_GROUP(msiof0_clk),
4542                 SH_PFC_PIN_GROUP(msiof0_sync),
4543                 SH_PFC_PIN_GROUP(msiof0_ss1),
4544                 SH_PFC_PIN_GROUP(msiof0_ss2),
4545                 SH_PFC_PIN_GROUP(msiof0_rx),
4546                 SH_PFC_PIN_GROUP(msiof0_tx),
4547                 SH_PFC_PIN_GROUP(msiof0_clk_b),
4548                 SH_PFC_PIN_GROUP(msiof0_sync_b),
4549                 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4550                 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4551                 SH_PFC_PIN_GROUP(msiof0_rx_b),
4552                 SH_PFC_PIN_GROUP(msiof0_tx_b),
4553                 SH_PFC_PIN_GROUP(msiof0_clk_c),
4554                 SH_PFC_PIN_GROUP(msiof0_sync_c),
4555                 SH_PFC_PIN_GROUP(msiof0_ss1_c),
4556                 SH_PFC_PIN_GROUP(msiof0_ss2_c),
4557                 SH_PFC_PIN_GROUP(msiof0_rx_c),
4558                 SH_PFC_PIN_GROUP(msiof0_tx_c),
4559                 SH_PFC_PIN_GROUP(msiof1_clk),
4560                 SH_PFC_PIN_GROUP(msiof1_sync),
4561                 SH_PFC_PIN_GROUP(msiof1_ss1),
4562                 SH_PFC_PIN_GROUP(msiof1_ss2),
4563                 SH_PFC_PIN_GROUP(msiof1_rx),
4564                 SH_PFC_PIN_GROUP(msiof1_tx),
4565                 SH_PFC_PIN_GROUP(msiof1_clk_b),
4566                 SH_PFC_PIN_GROUP(msiof1_sync_b),
4567                 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4568                 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4569                 SH_PFC_PIN_GROUP(msiof1_rx_b),
4570                 SH_PFC_PIN_GROUP(msiof1_tx_b),
4571                 SH_PFC_PIN_GROUP(msiof1_clk_c),
4572                 SH_PFC_PIN_GROUP(msiof1_sync_c),
4573                 SH_PFC_PIN_GROUP(msiof1_rx_c),
4574                 SH_PFC_PIN_GROUP(msiof1_tx_c),
4575                 SH_PFC_PIN_GROUP(msiof1_clk_d),
4576                 SH_PFC_PIN_GROUP(msiof1_sync_d),
4577                 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4578                 SH_PFC_PIN_GROUP(msiof1_rx_d),
4579                 SH_PFC_PIN_GROUP(msiof1_tx_d),
4580                 SH_PFC_PIN_GROUP(msiof1_clk_e),
4581                 SH_PFC_PIN_GROUP(msiof1_sync_e),
4582                 SH_PFC_PIN_GROUP(msiof1_rx_e),
4583                 SH_PFC_PIN_GROUP(msiof1_tx_e),
4584                 SH_PFC_PIN_GROUP(msiof2_clk),
4585                 SH_PFC_PIN_GROUP(msiof2_sync),
4586                 SH_PFC_PIN_GROUP(msiof2_ss1),
4587                 SH_PFC_PIN_GROUP(msiof2_ss2),
4588                 SH_PFC_PIN_GROUP(msiof2_rx),
4589                 SH_PFC_PIN_GROUP(msiof2_tx),
4590                 SH_PFC_PIN_GROUP(msiof2_clk_b),
4591                 SH_PFC_PIN_GROUP(msiof2_sync_b),
4592                 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4593                 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4594                 SH_PFC_PIN_GROUP(msiof2_rx_b),
4595                 SH_PFC_PIN_GROUP(msiof2_tx_b),
4596                 SH_PFC_PIN_GROUP(msiof2_clk_c),
4597                 SH_PFC_PIN_GROUP(msiof2_sync_c),
4598                 SH_PFC_PIN_GROUP(msiof2_rx_c),
4599                 SH_PFC_PIN_GROUP(msiof2_tx_c),
4600                 SH_PFC_PIN_GROUP(msiof2_clk_d),
4601                 SH_PFC_PIN_GROUP(msiof2_sync_d),
4602                 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4603                 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4604                 SH_PFC_PIN_GROUP(msiof2_rx_d),
4605                 SH_PFC_PIN_GROUP(msiof2_tx_d),
4606                 SH_PFC_PIN_GROUP(msiof2_clk_e),
4607                 SH_PFC_PIN_GROUP(msiof2_sync_e),
4608                 SH_PFC_PIN_GROUP(msiof2_rx_e),
4609                 SH_PFC_PIN_GROUP(msiof2_tx_e),
4610                 SH_PFC_PIN_GROUP(pwm0),
4611                 SH_PFC_PIN_GROUP(pwm0_b),
4612                 SH_PFC_PIN_GROUP(pwm1),
4613                 SH_PFC_PIN_GROUP(pwm1_b),
4614                 SH_PFC_PIN_GROUP(pwm2),
4615                 SH_PFC_PIN_GROUP(pwm2_b),
4616                 SH_PFC_PIN_GROUP(pwm3),
4617                 SH_PFC_PIN_GROUP(pwm4),
4618                 SH_PFC_PIN_GROUP(pwm4_b),
4619                 SH_PFC_PIN_GROUP(pwm5),
4620                 SH_PFC_PIN_GROUP(pwm5_b),
4621                 SH_PFC_PIN_GROUP(pwm6),
4622                 SH_PFC_PIN_GROUP(qspi_ctrl),
4623                 SH_PFC_PIN_GROUP(qspi_data2),
4624                 SH_PFC_PIN_GROUP(qspi_data4),
4625                 SH_PFC_PIN_GROUP(qspi_ctrl_b),
4626                 SH_PFC_PIN_GROUP(qspi_data2_b),
4627                 SH_PFC_PIN_GROUP(qspi_data4_b),
4628                 SH_PFC_PIN_GROUP(scif0_data),
4629                 SH_PFC_PIN_GROUP(scif0_data_b),
4630                 SH_PFC_PIN_GROUP(scif0_data_c),
4631                 SH_PFC_PIN_GROUP(scif0_data_d),
4632                 SH_PFC_PIN_GROUP(scif0_data_e),
4633                 SH_PFC_PIN_GROUP(scif1_data),
4634                 SH_PFC_PIN_GROUP(scif1_data_b),
4635                 SH_PFC_PIN_GROUP(scif1_clk_b),
4636                 SH_PFC_PIN_GROUP(scif1_data_c),
4637                 SH_PFC_PIN_GROUP(scif1_data_d),
4638                 SH_PFC_PIN_GROUP(scif2_data),
4639                 SH_PFC_PIN_GROUP(scif2_data_b),
4640                 SH_PFC_PIN_GROUP(scif2_clk_b),
4641                 SH_PFC_PIN_GROUP(scif2_data_c),
4642                 SH_PFC_PIN_GROUP(scif2_data_e),
4643                 SH_PFC_PIN_GROUP(scif3_data),
4644                 SH_PFC_PIN_GROUP(scif3_clk),
4645                 SH_PFC_PIN_GROUP(scif3_data_b),
4646                 SH_PFC_PIN_GROUP(scif3_clk_b),
4647                 SH_PFC_PIN_GROUP(scif3_data_c),
4648                 SH_PFC_PIN_GROUP(scif3_data_d),
4649                 SH_PFC_PIN_GROUP(scif4_data),
4650                 SH_PFC_PIN_GROUP(scif4_data_b),
4651                 SH_PFC_PIN_GROUP(scif4_data_c),
4652                 SH_PFC_PIN_GROUP(scif5_data),
4653                 SH_PFC_PIN_GROUP(scif5_data_b),
4654                 SH_PFC_PIN_GROUP(scifa0_data),
4655                 SH_PFC_PIN_GROUP(scifa0_data_b),
4656                 SH_PFC_PIN_GROUP(scifa1_data),
4657                 SH_PFC_PIN_GROUP(scifa1_clk),
4658                 SH_PFC_PIN_GROUP(scifa1_data_b),
4659                 SH_PFC_PIN_GROUP(scifa1_clk_b),
4660                 SH_PFC_PIN_GROUP(scifa1_data_c),
4661                 SH_PFC_PIN_GROUP(scifa2_data),
4662                 SH_PFC_PIN_GROUP(scifa2_clk),
4663                 SH_PFC_PIN_GROUP(scifa2_data_b),
4664                 SH_PFC_PIN_GROUP(scifa3_data),
4665                 SH_PFC_PIN_GROUP(scifa3_clk),
4666                 SH_PFC_PIN_GROUP(scifa3_data_b),
4667                 SH_PFC_PIN_GROUP(scifa3_clk_b),
4668                 SH_PFC_PIN_GROUP(scifa3_data_c),
4669                 SH_PFC_PIN_GROUP(scifa3_clk_c),
4670                 SH_PFC_PIN_GROUP(scifa4_data),
4671                 SH_PFC_PIN_GROUP(scifa4_data_b),
4672                 SH_PFC_PIN_GROUP(scifa4_data_c),
4673                 SH_PFC_PIN_GROUP(scifa5_data),
4674                 SH_PFC_PIN_GROUP(scifa5_data_b),
4675                 SH_PFC_PIN_GROUP(scifa5_data_c),
4676                 SH_PFC_PIN_GROUP(scifb0_data),
4677                 SH_PFC_PIN_GROUP(scifb0_clk),
4678                 SH_PFC_PIN_GROUP(scifb0_ctrl),
4679                 SH_PFC_PIN_GROUP(scifb0_data_b),
4680                 SH_PFC_PIN_GROUP(scifb0_clk_b),
4681                 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4682                 SH_PFC_PIN_GROUP(scifb0_data_c),
4683                 SH_PFC_PIN_GROUP(scifb0_clk_c),
4684                 SH_PFC_PIN_GROUP(scifb0_data_d),
4685                 SH_PFC_PIN_GROUP(scifb0_clk_d),
4686                 SH_PFC_PIN_GROUP(scifb1_data),
4687                 SH_PFC_PIN_GROUP(scifb1_clk),
4688                 SH_PFC_PIN_GROUP(scifb1_ctrl),
4689                 SH_PFC_PIN_GROUP(scifb1_data_b),
4690                 SH_PFC_PIN_GROUP(scifb1_clk_b),
4691                 SH_PFC_PIN_GROUP(scifb1_data_c),
4692                 SH_PFC_PIN_GROUP(scifb1_clk_c),
4693                 SH_PFC_PIN_GROUP(scifb1_data_d),
4694                 SH_PFC_PIN_GROUP(scifb2_data),
4695                 SH_PFC_PIN_GROUP(scifb2_clk),
4696                 SH_PFC_PIN_GROUP(scifb2_ctrl),
4697                 SH_PFC_PIN_GROUP(scifb2_data_b),
4698                 SH_PFC_PIN_GROUP(scifb2_clk_b),
4699                 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4700                 SH_PFC_PIN_GROUP(scifb2_data_c),
4701                 SH_PFC_PIN_GROUP(scifb2_clk_c),
4702                 SH_PFC_PIN_GROUP(scifb2_data_d),
4703                 SH_PFC_PIN_GROUP(scif_clk),
4704                 SH_PFC_PIN_GROUP(scif_clk_b),
4705                 SH_PFC_PIN_GROUP(sdhi0_data1),
4706                 SH_PFC_PIN_GROUP(sdhi0_data4),
4707                 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4708                 SH_PFC_PIN_GROUP(sdhi0_cd),
4709                 SH_PFC_PIN_GROUP(sdhi0_wp),
4710                 SH_PFC_PIN_GROUP(sdhi1_data1),
4711                 SH_PFC_PIN_GROUP(sdhi1_data4),
4712                 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4713                 SH_PFC_PIN_GROUP(sdhi1_cd),
4714                 SH_PFC_PIN_GROUP(sdhi1_wp),
4715                 SH_PFC_PIN_GROUP(sdhi2_data1),
4716                 SH_PFC_PIN_GROUP(sdhi2_data4),
4717                 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4718                 SH_PFC_PIN_GROUP(sdhi2_cd),
4719                 SH_PFC_PIN_GROUP(sdhi2_wp),
4720                 SH_PFC_PIN_GROUP(ssi0_data),
4721                 SH_PFC_PIN_GROUP(ssi0_data_b),
4722                 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4723                 SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4724                 SH_PFC_PIN_GROUP(ssi1_data),
4725                 SH_PFC_PIN_GROUP(ssi1_data_b),
4726                 SH_PFC_PIN_GROUP(ssi1_ctrl),
4727                 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4728                 SH_PFC_PIN_GROUP(ssi2_data),
4729                 SH_PFC_PIN_GROUP(ssi2_ctrl),
4730                 SH_PFC_PIN_GROUP(ssi3_data),
4731                 SH_PFC_PIN_GROUP(ssi34_ctrl),
4732                 SH_PFC_PIN_GROUP(ssi4_data),
4733                 SH_PFC_PIN_GROUP(ssi4_ctrl),
4734                 SH_PFC_PIN_GROUP(ssi5_data),
4735                 SH_PFC_PIN_GROUP(ssi5_ctrl),
4736                 SH_PFC_PIN_GROUP(ssi6_data),
4737                 SH_PFC_PIN_GROUP(ssi6_ctrl),
4738                 SH_PFC_PIN_GROUP(ssi7_data),
4739                 SH_PFC_PIN_GROUP(ssi7_data_b),
4740                 SH_PFC_PIN_GROUP(ssi78_ctrl),
4741                 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4742                 SH_PFC_PIN_GROUP(ssi8_data),
4743                 SH_PFC_PIN_GROUP(ssi8_data_b),
4744                 SH_PFC_PIN_GROUP(ssi9_data),
4745                 SH_PFC_PIN_GROUP(ssi9_data_b),
4746                 SH_PFC_PIN_GROUP(ssi9_ctrl),
4747                 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4748                 SH_PFC_PIN_GROUP(usb0),
4749                 SH_PFC_PIN_GROUP(usb1),
4750                 VIN_DATA_PIN_GROUP(vin0_data, 24),
4751                 VIN_DATA_PIN_GROUP(vin0_data, 20),
4752                 SH_PFC_PIN_GROUP(vin0_data18),
4753                 VIN_DATA_PIN_GROUP(vin0_data, 16),
4754                 VIN_DATA_PIN_GROUP(vin0_data, 12),
4755                 VIN_DATA_PIN_GROUP(vin0_data, 10),
4756                 VIN_DATA_PIN_GROUP(vin0_data, 8),
4757                 SH_PFC_PIN_GROUP(vin0_sync),
4758                 SH_PFC_PIN_GROUP(vin0_field),
4759                 SH_PFC_PIN_GROUP(vin0_clkenb),
4760                 SH_PFC_PIN_GROUP(vin0_clk),
4761                 SH_PFC_PIN_GROUP(vin1_data8),
4762                 SH_PFC_PIN_GROUP(vin1_sync),
4763                 SH_PFC_PIN_GROUP(vin1_field),
4764                 SH_PFC_PIN_GROUP(vin1_clkenb),
4765                 SH_PFC_PIN_GROUP(vin1_clk),
4766                 VIN_DATA_PIN_GROUP(vin1_b_data, 24),
4767                 VIN_DATA_PIN_GROUP(vin1_b_data, 20),
4768                 SH_PFC_PIN_GROUP(vin1_b_data18),
4769                 VIN_DATA_PIN_GROUP(vin1_b_data, 16),
4770                 VIN_DATA_PIN_GROUP(vin1_b_data, 12),
4771                 VIN_DATA_PIN_GROUP(vin1_b_data, 10),
4772                 VIN_DATA_PIN_GROUP(vin1_b_data, 8),
4773                 SH_PFC_PIN_GROUP(vin1_b_sync),
4774                 SH_PFC_PIN_GROUP(vin1_b_field),
4775                 SH_PFC_PIN_GROUP(vin1_b_clkenb),
4776                 SH_PFC_PIN_GROUP(vin1_b_clk),
4777                 SH_PFC_PIN_GROUP(vin2_data8),
4778                 SH_PFC_PIN_GROUP(vin2_sync),
4779                 SH_PFC_PIN_GROUP(vin2_field),
4780                 SH_PFC_PIN_GROUP(vin2_clkenb),
4781                 SH_PFC_PIN_GROUP(vin2_clk),
4782         },
4783         .r8a779x = {
4784                 SH_PFC_PIN_GROUP(adi_common),
4785                 SH_PFC_PIN_GROUP(adi_chsel0),
4786                 SH_PFC_PIN_GROUP(adi_chsel1),
4787                 SH_PFC_PIN_GROUP(adi_chsel2),
4788                 SH_PFC_PIN_GROUP(adi_common_b),
4789                 SH_PFC_PIN_GROUP(adi_chsel0_b),
4790                 SH_PFC_PIN_GROUP(adi_chsel1_b),
4791                 SH_PFC_PIN_GROUP(adi_chsel2_b),
4792                 SH_PFC_PIN_GROUP(mlb_3pin),
4793         }
4794 };
4795
4796 static const char * const adi_groups[] = {
4797         "adi_common",
4798         "adi_chsel0",
4799         "adi_chsel1",
4800         "adi_chsel2",
4801         "adi_common_b",
4802         "adi_chsel0_b",
4803         "adi_chsel1_b",
4804         "adi_chsel2_b",
4805 };
4806
4807 static const char * const audio_clk_groups[] = {
4808         "audio_clk_a",
4809         "audio_clk_b",
4810         "audio_clk_b_b",
4811         "audio_clk_c",
4812         "audio_clkout",
4813 };
4814
4815 static const char * const avb_groups[] = {
4816         "avb_link",
4817         "avb_magic",
4818         "avb_phy_int",
4819         "avb_mdio",
4820         "avb_mii",
4821         "avb_gmii",
4822 };
4823
4824 static const char * const can0_groups[] = {
4825         "can0_data",
4826         "can0_data_b",
4827         "can0_data_c",
4828         "can0_data_d",
4829         "can0_data_e",
4830         "can0_data_f",
4831         "can_clk",
4832         "can_clk_b",
4833         "can_clk_c",
4834         "can_clk_d",
4835 };
4836
4837 static const char * const can1_groups[] = {
4838         "can1_data",
4839         "can1_data_b",
4840         "can1_data_c",
4841         "can1_data_d",
4842         "can_clk",
4843         "can_clk_b",
4844         "can_clk_c",
4845         "can_clk_d",
4846 };
4847
4848 static const char * const du_groups[] = {
4849         "du_rgb666",
4850         "du_rgb888",
4851         "du_clk_out_0",
4852         "du_clk_out_1",
4853         "du_sync",
4854         "du_oddf",
4855         "du_cde",
4856         "du_disp",
4857 };
4858
4859 static const char * const du0_groups[] = {
4860         "du0_clk_in",
4861 };
4862
4863 static const char * const du1_groups[] = {
4864         "du1_clk_in",
4865         "du1_clk_in_b",
4866         "du1_clk_in_c",
4867 };
4868
4869 static const char * const eth_groups[] = {
4870         "eth_link",
4871         "eth_magic",
4872         "eth_mdio",
4873         "eth_rmii",
4874 };
4875
4876 static const char * const hscif0_groups[] = {
4877         "hscif0_data",
4878         "hscif0_clk",
4879         "hscif0_ctrl",
4880         "hscif0_data_b",
4881         "hscif0_ctrl_b",
4882         "hscif0_data_c",
4883         "hscif0_clk_c",
4884 };
4885
4886 static const char * const hscif1_groups[] = {
4887         "hscif1_data",
4888         "hscif1_clk",
4889         "hscif1_ctrl",
4890         "hscif1_data_b",
4891         "hscif1_data_c",
4892         "hscif1_clk_c",
4893         "hscif1_ctrl_c",
4894         "hscif1_data_d",
4895         "hscif1_data_e",
4896         "hscif1_clk_e",
4897         "hscif1_ctrl_e",
4898 };
4899
4900 static const char * const hscif2_groups[] = {
4901         "hscif2_data",
4902         "hscif2_clk",
4903         "hscif2_ctrl",
4904         "hscif2_data_b",
4905         "hscif2_ctrl_b",
4906         "hscif2_data_c",
4907         "hscif2_clk_c",
4908         "hscif2_data_d",
4909 };
4910
4911 static const char * const i2c0_groups[] = {
4912         "i2c0",
4913         "i2c0_b",
4914         "i2c0_c",
4915 };
4916
4917 static const char * const i2c1_groups[] = {
4918         "i2c1",
4919         "i2c1_b",
4920         "i2c1_c",
4921         "i2c1_d",
4922         "i2c1_e",
4923 };
4924
4925 static const char * const i2c2_groups[] = {
4926         "i2c2",
4927         "i2c2_b",
4928         "i2c2_c",
4929         "i2c2_d",
4930 };
4931
4932 static const char * const i2c3_groups[] = {
4933         "i2c3",
4934         "i2c3_b",
4935         "i2c3_c",
4936         "i2c3_d",
4937 };
4938
4939 static const char * const i2c4_groups[] = {
4940         "i2c4",
4941         "i2c4_b",
4942         "i2c4_c",
4943 };
4944
4945 static const char * const i2c7_groups[] = {
4946         "i2c7",
4947         "i2c7_b",
4948         "i2c7_c",
4949 };
4950
4951 static const char * const i2c8_groups[] = {
4952         "i2c8",
4953         "i2c8_b",
4954         "i2c8_c",
4955 };
4956
4957 static const char * const intc_groups[] = {
4958         "intc_irq0",
4959         "intc_irq1",
4960         "intc_irq2",
4961         "intc_irq3",
4962 };
4963
4964 static const char * const mlb_groups[] = {
4965         "mlb_3pin",
4966 };
4967
4968 static const char * const mmc_groups[] = {
4969         "mmc_data1",
4970         "mmc_data4",
4971         "mmc_data8",
4972         "mmc_data8_b",
4973         "mmc_ctrl",
4974 };
4975
4976 static const char * const msiof0_groups[] = {
4977         "msiof0_clk",
4978         "msiof0_sync",
4979         "msiof0_ss1",
4980         "msiof0_ss2",
4981         "msiof0_rx",
4982         "msiof0_tx",
4983         "msiof0_clk_b",
4984         "msiof0_sync_b",
4985         "msiof0_ss1_b",
4986         "msiof0_ss2_b",
4987         "msiof0_rx_b",
4988         "msiof0_tx_b",
4989         "msiof0_clk_c",
4990         "msiof0_sync_c",
4991         "msiof0_ss1_c",
4992         "msiof0_ss2_c",
4993         "msiof0_rx_c",
4994         "msiof0_tx_c",
4995 };
4996
4997 static const char * const msiof1_groups[] = {
4998         "msiof1_clk",
4999         "msiof1_sync",
5000         "msiof1_ss1",
5001         "msiof1_ss2",
5002         "msiof1_rx",
5003         "msiof1_tx",
5004         "msiof1_clk_b",
5005         "msiof1_sync_b",
5006         "msiof1_ss1_b",
5007         "msiof1_ss2_b",
5008         "msiof1_rx_b",
5009         "msiof1_tx_b",
5010         "msiof1_clk_c",
5011         "msiof1_sync_c",
5012         "msiof1_rx_c",
5013         "msiof1_tx_c",
5014         "msiof1_clk_d",
5015         "msiof1_sync_d",
5016         "msiof1_ss1_d",
5017         "msiof1_rx_d",
5018         "msiof1_tx_d",
5019         "msiof1_clk_e",
5020         "msiof1_sync_e",
5021         "msiof1_rx_e",
5022         "msiof1_tx_e",
5023 };
5024
5025 static const char * const msiof2_groups[] = {
5026         "msiof2_clk",
5027         "msiof2_sync",
5028         "msiof2_ss1",
5029         "msiof2_ss2",
5030         "msiof2_rx",
5031         "msiof2_tx",
5032         "msiof2_clk_b",
5033         "msiof2_sync_b",
5034         "msiof2_ss1_b",
5035         "msiof2_ss2_b",
5036         "msiof2_rx_b",
5037         "msiof2_tx_b",
5038         "msiof2_clk_c",
5039         "msiof2_sync_c",
5040         "msiof2_rx_c",
5041         "msiof2_tx_c",
5042         "msiof2_clk_d",
5043         "msiof2_sync_d",
5044         "msiof2_ss1_d",
5045         "msiof2_ss2_d",
5046         "msiof2_rx_d",
5047         "msiof2_tx_d",
5048         "msiof2_clk_e",
5049         "msiof2_sync_e",
5050         "msiof2_rx_e",
5051         "msiof2_tx_e",
5052 };
5053
5054 static const char * const pwm0_groups[] = {
5055         "pwm0",
5056         "pwm0_b",
5057 };
5058
5059 static const char * const pwm1_groups[] = {
5060         "pwm1",
5061         "pwm1_b",
5062 };
5063
5064 static const char * const pwm2_groups[] = {
5065         "pwm2",
5066         "pwm2_b",
5067 };
5068
5069 static const char * const pwm3_groups[] = {
5070         "pwm3",
5071 };
5072
5073 static const char * const pwm4_groups[] = {
5074         "pwm4",
5075         "pwm4_b",
5076 };
5077
5078 static const char * const pwm5_groups[] = {
5079         "pwm5",
5080         "pwm5_b",
5081 };
5082
5083 static const char * const pwm6_groups[] = {
5084         "pwm6",
5085 };
5086
5087 static const char * const qspi_groups[] = {
5088         "qspi_ctrl",
5089         "qspi_data2",
5090         "qspi_data4",
5091         "qspi_ctrl_b",
5092         "qspi_data2_b",
5093         "qspi_data4_b",
5094 };
5095
5096 static const char * const scif0_groups[] = {
5097         "scif0_data",
5098         "scif0_data_b",
5099         "scif0_data_c",
5100         "scif0_data_d",
5101         "scif0_data_e",
5102 };
5103
5104 static const char * const scif1_groups[] = {
5105         "scif1_data",
5106         "scif1_data_b",
5107         "scif1_clk_b",
5108         "scif1_data_c",
5109         "scif1_data_d",
5110 };
5111
5112 static const char * const scif2_groups[] = {
5113         "scif2_data",
5114         "scif2_data_b",
5115         "scif2_clk_b",
5116         "scif2_data_c",
5117         "scif2_data_e",
5118 };
5119 static const char * const scif3_groups[] = {
5120         "scif3_data",
5121         "scif3_clk",
5122         "scif3_data_b",
5123         "scif3_clk_b",
5124         "scif3_data_c",
5125         "scif3_data_d",
5126 };
5127 static const char * const scif4_groups[] = {
5128         "scif4_data",
5129         "scif4_data_b",
5130         "scif4_data_c",
5131 };
5132 static const char * const scif5_groups[] = {
5133         "scif5_data",
5134         "scif5_data_b",
5135 };
5136 static const char * const scifa0_groups[] = {
5137         "scifa0_data",
5138         "scifa0_data_b",
5139 };
5140 static const char * const scifa1_groups[] = {
5141         "scifa1_data",
5142         "scifa1_clk",
5143         "scifa1_data_b",
5144         "scifa1_clk_b",
5145         "scifa1_data_c",
5146 };
5147 static const char * const scifa2_groups[] = {
5148         "scifa2_data",
5149         "scifa2_clk",
5150         "scifa2_data_b",
5151 };
5152 static const char * const scifa3_groups[] = {
5153         "scifa3_data",
5154         "scifa3_clk",
5155         "scifa3_data_b",
5156         "scifa3_clk_b",
5157         "scifa3_data_c",
5158         "scifa3_clk_c",
5159 };
5160 static const char * const scifa4_groups[] = {
5161         "scifa4_data",
5162         "scifa4_data_b",
5163         "scifa4_data_c",
5164 };
5165 static const char * const scifa5_groups[] = {
5166         "scifa5_data",
5167         "scifa5_data_b",
5168         "scifa5_data_c",
5169 };
5170 static const char * const scifb0_groups[] = {
5171         "scifb0_data",
5172         "scifb0_clk",
5173         "scifb0_ctrl",
5174         "scifb0_data_b",
5175         "scifb0_clk_b",
5176         "scifb0_ctrl_b",
5177         "scifb0_data_c",
5178         "scifb0_clk_c",
5179         "scifb0_data_d",
5180         "scifb0_clk_d",
5181 };
5182 static const char * const scifb1_groups[] = {
5183         "scifb1_data",
5184         "scifb1_clk",
5185         "scifb1_ctrl",
5186         "scifb1_data_b",
5187         "scifb1_clk_b",
5188         "scifb1_data_c",
5189         "scifb1_clk_c",
5190         "scifb1_data_d",
5191 };
5192 static const char * const scifb2_groups[] = {
5193         "scifb2_data",
5194         "scifb2_clk",
5195         "scifb2_ctrl",
5196         "scifb2_data_b",
5197         "scifb2_clk_b",
5198         "scifb2_ctrl_b",
5199         "scifb0_data_c",
5200         "scifb2_clk_c",
5201         "scifb2_data_d",
5202 };
5203
5204 static const char * const scif_clk_groups[] = {
5205         "scif_clk",
5206         "scif_clk_b",
5207 };
5208
5209 static const char * const sdhi0_groups[] = {
5210         "sdhi0_data1",
5211         "sdhi0_data4",
5212         "sdhi0_ctrl",
5213         "sdhi0_cd",
5214         "sdhi0_wp",
5215 };
5216
5217 static const char * const sdhi1_groups[] = {
5218         "sdhi1_data1",
5219         "sdhi1_data4",
5220         "sdhi1_ctrl",
5221         "sdhi1_cd",
5222         "sdhi1_wp",
5223 };
5224
5225 static const char * const sdhi2_groups[] = {
5226         "sdhi2_data1",
5227         "sdhi2_data4",
5228         "sdhi2_ctrl",
5229         "sdhi2_cd",
5230         "sdhi2_wp",
5231 };
5232
5233 static const char * const ssi_groups[] = {
5234         "ssi0_data",
5235         "ssi0_data_b",
5236         "ssi0129_ctrl",
5237         "ssi0129_ctrl_b",
5238         "ssi1_data",
5239         "ssi1_data_b",
5240         "ssi1_ctrl",
5241         "ssi1_ctrl_b",
5242         "ssi2_data",
5243         "ssi2_ctrl",
5244         "ssi3_data",
5245         "ssi34_ctrl",
5246         "ssi4_data",
5247         "ssi4_ctrl",
5248         "ssi5_data",
5249         "ssi5_ctrl",
5250         "ssi6_data",
5251         "ssi6_ctrl",
5252         "ssi7_data",
5253         "ssi7_data_b",
5254         "ssi78_ctrl",
5255         "ssi78_ctrl_b",
5256         "ssi8_data",
5257         "ssi8_data_b",
5258         "ssi9_data",
5259         "ssi9_data_b",
5260         "ssi9_ctrl",
5261         "ssi9_ctrl_b",
5262 };
5263
5264 static const char * const usb0_groups[] = {
5265         "usb0",
5266 };
5267 static const char * const usb1_groups[] = {
5268         "usb1",
5269 };
5270
5271 static const char * const vin0_groups[] = {
5272         "vin0_data24",
5273         "vin0_data20",
5274         "vin0_data18",
5275         "vin0_data16",
5276         "vin0_data12",
5277         "vin0_data10",
5278         "vin0_data8",
5279         "vin0_sync",
5280         "vin0_field",
5281         "vin0_clkenb",
5282         "vin0_clk",
5283 };
5284
5285 static const char * const vin1_groups[] = {
5286         "vin1_data8",
5287         "vin1_sync",
5288         "vin1_field",
5289         "vin1_clkenb",
5290         "vin1_clk",
5291         "vin1_b_data24",
5292         "vin1_b_data20",
5293         "vin1_b_data18",
5294         "vin1_b_data16",
5295         "vin1_b_data12",
5296         "vin1_b_data10",
5297         "vin1_b_data8",
5298         "vin1_b_sync",
5299         "vin1_b_field",
5300         "vin1_b_clkenb",
5301         "vin1_b_clk",
5302 };
5303
5304 static const char * const vin2_groups[] = {
5305         "vin2_data8",
5306         "vin2_sync",
5307         "vin2_field",
5308         "vin2_clkenb",
5309         "vin2_clk",
5310 };
5311
5312 static const struct {
5313         struct sh_pfc_function common[56];
5314         struct sh_pfc_function r8a779x[2];
5315 } pinmux_functions = {
5316         .common = {
5317                 SH_PFC_FUNCTION(audio_clk),
5318                 SH_PFC_FUNCTION(avb),
5319                 SH_PFC_FUNCTION(can0),
5320                 SH_PFC_FUNCTION(can1),
5321                 SH_PFC_FUNCTION(du),
5322                 SH_PFC_FUNCTION(du0),
5323                 SH_PFC_FUNCTION(du1),
5324                 SH_PFC_FUNCTION(eth),
5325                 SH_PFC_FUNCTION(hscif0),
5326                 SH_PFC_FUNCTION(hscif1),
5327                 SH_PFC_FUNCTION(hscif2),
5328                 SH_PFC_FUNCTION(i2c0),
5329                 SH_PFC_FUNCTION(i2c1),
5330                 SH_PFC_FUNCTION(i2c2),
5331                 SH_PFC_FUNCTION(i2c3),
5332                 SH_PFC_FUNCTION(i2c4),
5333                 SH_PFC_FUNCTION(i2c7),
5334                 SH_PFC_FUNCTION(i2c8),
5335                 SH_PFC_FUNCTION(intc),
5336                 SH_PFC_FUNCTION(mmc),
5337                 SH_PFC_FUNCTION(msiof0),
5338                 SH_PFC_FUNCTION(msiof1),
5339                 SH_PFC_FUNCTION(msiof2),
5340                 SH_PFC_FUNCTION(pwm0),
5341                 SH_PFC_FUNCTION(pwm1),
5342                 SH_PFC_FUNCTION(pwm2),
5343                 SH_PFC_FUNCTION(pwm3),
5344                 SH_PFC_FUNCTION(pwm4),
5345                 SH_PFC_FUNCTION(pwm5),
5346                 SH_PFC_FUNCTION(pwm6),
5347                 SH_PFC_FUNCTION(qspi),
5348                 SH_PFC_FUNCTION(scif0),
5349                 SH_PFC_FUNCTION(scif1),
5350                 SH_PFC_FUNCTION(scif2),
5351                 SH_PFC_FUNCTION(scif3),
5352                 SH_PFC_FUNCTION(scif4),
5353                 SH_PFC_FUNCTION(scif5),
5354                 SH_PFC_FUNCTION(scifa0),
5355                 SH_PFC_FUNCTION(scifa1),
5356                 SH_PFC_FUNCTION(scifa2),
5357                 SH_PFC_FUNCTION(scifa3),
5358                 SH_PFC_FUNCTION(scifa4),
5359                 SH_PFC_FUNCTION(scifa5),
5360                 SH_PFC_FUNCTION(scifb0),
5361                 SH_PFC_FUNCTION(scifb1),
5362                 SH_PFC_FUNCTION(scifb2),
5363                 SH_PFC_FUNCTION(scif_clk),
5364                 SH_PFC_FUNCTION(sdhi0),
5365                 SH_PFC_FUNCTION(sdhi1),
5366                 SH_PFC_FUNCTION(sdhi2),
5367                 SH_PFC_FUNCTION(ssi),
5368                 SH_PFC_FUNCTION(usb0),
5369                 SH_PFC_FUNCTION(usb1),
5370                 SH_PFC_FUNCTION(vin0),
5371                 SH_PFC_FUNCTION(vin1),
5372                 SH_PFC_FUNCTION(vin2),
5373         },
5374         .r8a779x = {
5375                 SH_PFC_FUNCTION(adi),
5376                 SH_PFC_FUNCTION(mlb),
5377         }
5378 };
5379
5380 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5381         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5382                 GP_0_31_FN, FN_IP1_22_20,
5383                 GP_0_30_FN, FN_IP1_19_17,
5384                 GP_0_29_FN, FN_IP1_16_14,
5385                 GP_0_28_FN, FN_IP1_13_11,
5386                 GP_0_27_FN, FN_IP1_10_8,
5387                 GP_0_26_FN, FN_IP1_7_6,
5388                 GP_0_25_FN, FN_IP1_5_4,
5389                 GP_0_24_FN, FN_IP1_3_2,
5390                 GP_0_23_FN, FN_IP1_1_0,
5391                 GP_0_22_FN, FN_IP0_30_29,
5392                 GP_0_21_FN, FN_IP0_28_27,
5393                 GP_0_20_FN, FN_IP0_26_25,
5394                 GP_0_19_FN, FN_IP0_24_23,
5395                 GP_0_18_FN, FN_IP0_22_21,
5396                 GP_0_17_FN, FN_IP0_20_19,
5397                 GP_0_16_FN, FN_IP0_18_16,
5398                 GP_0_15_FN, FN_IP0_15,
5399                 GP_0_14_FN, FN_IP0_14,
5400                 GP_0_13_FN, FN_IP0_13,
5401                 GP_0_12_FN, FN_IP0_12,
5402                 GP_0_11_FN, FN_IP0_11,
5403                 GP_0_10_FN, FN_IP0_10,
5404                 GP_0_9_FN, FN_IP0_9,
5405                 GP_0_8_FN, FN_IP0_8,
5406                 GP_0_7_FN, FN_IP0_7,
5407                 GP_0_6_FN, FN_IP0_6,
5408                 GP_0_5_FN, FN_IP0_5,
5409                 GP_0_4_FN, FN_IP0_4,
5410                 GP_0_3_FN, FN_IP0_3,
5411                 GP_0_2_FN, FN_IP0_2,
5412                 GP_0_1_FN, FN_IP0_1,
5413                 GP_0_0_FN, FN_IP0_0, }
5414         },
5415         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5416                 0, 0,
5417                 0, 0,
5418                 0, 0,
5419                 0, 0,
5420                 0, 0,
5421                 0, 0,
5422                 GP_1_25_FN, FN_IP3_21_20,
5423                 GP_1_24_FN, FN_IP3_19_18,
5424                 GP_1_23_FN, FN_IP3_17_16,
5425                 GP_1_22_FN, FN_IP3_15_14,
5426                 GP_1_21_FN, FN_IP3_13_12,
5427                 GP_1_20_FN, FN_IP3_11_9,
5428                 GP_1_19_FN, FN_RD_N,
5429                 GP_1_18_FN, FN_IP3_8_6,
5430                 GP_1_17_FN, FN_IP3_5_3,
5431                 GP_1_16_FN, FN_IP3_2_0,
5432                 GP_1_15_FN, FN_IP2_29_27,
5433                 GP_1_14_FN, FN_IP2_26_25,
5434                 GP_1_13_FN, FN_IP2_24_23,
5435                 GP_1_12_FN, FN_EX_CS0_N,
5436                 GP_1_11_FN, FN_IP2_22_21,
5437                 GP_1_10_FN, FN_IP2_20_19,
5438                 GP_1_9_FN, FN_IP2_18_16,
5439                 GP_1_8_FN, FN_IP2_15_13,
5440                 GP_1_7_FN, FN_IP2_12_10,
5441                 GP_1_6_FN, FN_IP2_9_7,
5442                 GP_1_5_FN, FN_IP2_6_5,
5443                 GP_1_4_FN, FN_IP2_4_3,
5444                 GP_1_3_FN, FN_IP2_2_0,
5445                 GP_1_2_FN, FN_IP1_31_29,
5446                 GP_1_1_FN, FN_IP1_28_26,
5447                 GP_1_0_FN, FN_IP1_25_23, }
5448         },
5449         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5450                 GP_2_31_FN, FN_IP6_7_6,
5451                 GP_2_30_FN, FN_IP6_5_3,
5452                 GP_2_29_FN, FN_IP6_2_0,
5453                 GP_2_28_FN, FN_AUDIO_CLKA,
5454                 GP_2_27_FN, FN_IP5_31_29,
5455                 GP_2_26_FN, FN_IP5_28_26,
5456                 GP_2_25_FN, FN_IP5_25_24,
5457                 GP_2_24_FN, FN_IP5_23_22,
5458                 GP_2_23_FN, FN_IP5_21_20,
5459                 GP_2_22_FN, FN_IP5_19_17,
5460                 GP_2_21_FN, FN_IP5_16_15,
5461                 GP_2_20_FN, FN_IP5_14_12,
5462                 GP_2_19_FN, FN_IP5_11_9,
5463                 GP_2_18_FN, FN_IP5_8_6,
5464                 GP_2_17_FN, FN_IP5_5_3,
5465                 GP_2_16_FN, FN_IP5_2_0,
5466                 GP_2_15_FN, FN_IP4_30_28,
5467                 GP_2_14_FN, FN_IP4_27_26,
5468                 GP_2_13_FN, FN_IP4_25_24,
5469                 GP_2_12_FN, FN_IP4_23_22,
5470                 GP_2_11_FN, FN_IP4_21,
5471                 GP_2_10_FN, FN_IP4_20,
5472                 GP_2_9_FN, FN_IP4_19,
5473                 GP_2_8_FN, FN_IP4_18_16,
5474                 GP_2_7_FN, FN_IP4_15_13,
5475                 GP_2_6_FN, FN_IP4_12_10,
5476                 GP_2_5_FN, FN_IP4_9_8,
5477                 GP_2_4_FN, FN_IP4_7_5,
5478                 GP_2_3_FN, FN_IP4_4_2,
5479                 GP_2_2_FN, FN_IP4_1_0,
5480                 GP_2_1_FN, FN_IP3_30_28,
5481                 GP_2_0_FN, FN_IP3_27_25 }
5482         },
5483         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5484                 GP_3_31_FN, FN_IP9_18_17,
5485                 GP_3_30_FN, FN_IP9_16,
5486                 GP_3_29_FN, FN_IP9_15_13,
5487                 GP_3_28_FN, FN_IP9_12,
5488                 GP_3_27_FN, FN_IP9_11,
5489                 GP_3_26_FN, FN_IP9_10_8,
5490                 GP_3_25_FN, FN_IP9_7,
5491                 GP_3_24_FN, FN_IP9_6,
5492                 GP_3_23_FN, FN_IP9_5_3,
5493                 GP_3_22_FN, FN_IP9_2_0,
5494                 GP_3_21_FN, FN_IP8_30_28,
5495                 GP_3_20_FN, FN_IP8_27_26,
5496                 GP_3_19_FN, FN_IP8_25_24,
5497                 GP_3_18_FN, FN_IP8_23_21,
5498                 GP_3_17_FN, FN_IP8_20_18,
5499                 GP_3_16_FN, FN_IP8_17_15,
5500                 GP_3_15_FN, FN_IP8_14_12,
5501                 GP_3_14_FN, FN_IP8_11_9,
5502                 GP_3_13_FN, FN_IP8_8_6,
5503                 GP_3_12_FN, FN_IP8_5_3,
5504                 GP_3_11_FN, FN_IP8_2_0,
5505                 GP_3_10_FN, FN_IP7_29_27,
5506                 GP_3_9_FN, FN_IP7_26_24,
5507                 GP_3_8_FN, FN_IP7_23_21,
5508                 GP_3_7_FN, FN_IP7_20_19,
5509                 GP_3_6_FN, FN_IP7_18_17,
5510                 GP_3_5_FN, FN_IP7_16_15,
5511                 GP_3_4_FN, FN_IP7_14_13,
5512                 GP_3_3_FN, FN_IP7_12_11,
5513                 GP_3_2_FN, FN_IP7_10_9,
5514                 GP_3_1_FN, FN_IP7_8_6,
5515                 GP_3_0_FN, FN_IP7_5_3 }
5516         },
5517         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5518                 GP_4_31_FN, FN_IP15_5_4,
5519                 GP_4_30_FN, FN_IP15_3_2,
5520                 GP_4_29_FN, FN_IP15_1_0,
5521                 GP_4_28_FN, FN_IP11_8_6,
5522                 GP_4_27_FN, FN_IP11_5_3,
5523                 GP_4_26_FN, FN_IP11_2_0,
5524                 GP_4_25_FN, FN_IP10_31_29,
5525                 GP_4_24_FN, FN_IP10_28_27,
5526                 GP_4_23_FN, FN_IP10_26_25,
5527                 GP_4_22_FN, FN_IP10_24_22,
5528                 GP_4_21_FN, FN_IP10_21_19,
5529                 GP_4_20_FN, FN_IP10_18_17,
5530                 GP_4_19_FN, FN_IP10_16_15,
5531                 GP_4_18_FN, FN_IP10_14_12,
5532                 GP_4_17_FN, FN_IP10_11_9,
5533                 GP_4_16_FN, FN_IP10_8_6,
5534                 GP_4_15_FN, FN_IP10_5_3,
5535                 GP_4_14_FN, FN_IP10_2_0,
5536                 GP_4_13_FN, FN_IP9_31_29,
5537                 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5538                 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5539                 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5540                 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5541                 GP_4_8_FN, FN_IP9_28_27,
5542                 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5543                 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5544                 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5545                 GP_4_4_FN, FN_IP9_26_25,
5546                 GP_4_3_FN, FN_IP9_24_23,
5547                 GP_4_2_FN, FN_IP9_22_21,
5548                 GP_4_1_FN, FN_IP9_20_19,
5549                 GP_4_0_FN, FN_VI0_CLK }
5550         },
5551         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5552                 GP_5_31_FN, FN_IP3_24_22,
5553                 GP_5_30_FN, FN_IP13_9_7,
5554                 GP_5_29_FN, FN_IP13_6_5,
5555                 GP_5_28_FN, FN_IP13_4_3,
5556                 GP_5_27_FN, FN_IP13_2_0,
5557                 GP_5_26_FN, FN_IP12_29_27,
5558                 GP_5_25_FN, FN_IP12_26_24,
5559                 GP_5_24_FN, FN_IP12_23_22,
5560                 GP_5_23_FN, FN_IP12_21_20,
5561                 GP_5_22_FN, FN_IP12_19_18,
5562                 GP_5_21_FN, FN_IP12_17_16,
5563                 GP_5_20_FN, FN_IP12_15_13,
5564                 GP_5_19_FN, FN_IP12_12_10,
5565                 GP_5_18_FN, FN_IP12_9_7,
5566                 GP_5_17_FN, FN_IP12_6_4,
5567                 GP_5_16_FN, FN_IP12_3_2,
5568                 GP_5_15_FN, FN_IP12_1_0,
5569                 GP_5_14_FN, FN_IP11_31_30,
5570                 GP_5_13_FN, FN_IP11_29_28,
5571                 GP_5_12_FN, FN_IP11_27,
5572                 GP_5_11_FN, FN_IP11_26,
5573                 GP_5_10_FN, FN_IP11_25,
5574                 GP_5_9_FN, FN_IP11_24,
5575                 GP_5_8_FN, FN_IP11_23,
5576                 GP_5_7_FN, FN_IP11_22,
5577                 GP_5_6_FN, FN_IP11_21,
5578                 GP_5_5_FN, FN_IP11_20,
5579                 GP_5_4_FN, FN_IP11_19,
5580                 GP_5_3_FN, FN_IP11_18_17,
5581                 GP_5_2_FN, FN_IP11_16_15,
5582                 GP_5_1_FN, FN_IP11_14_12,
5583                 GP_5_0_FN, FN_IP11_11_9 }
5584         },
5585         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5586                 GP_6_31_FN, FN_DU0_DOTCLKIN,
5587                 GP_6_30_FN, FN_USB1_OVC,
5588                 GP_6_29_FN, FN_IP14_31_29,
5589                 GP_6_28_FN, FN_IP14_28_26,
5590                 GP_6_27_FN, FN_IP14_25_23,
5591                 GP_6_26_FN, FN_IP14_22_20,
5592                 GP_6_25_FN, FN_IP14_19_17,
5593                 GP_6_24_FN, FN_IP14_16_14,
5594                 GP_6_23_FN, FN_IP14_13_11,
5595                 GP_6_22_FN, FN_IP14_10_8,
5596                 GP_6_21_FN, FN_IP14_7,
5597                 GP_6_20_FN, FN_IP14_6,
5598                 GP_6_19_FN, FN_IP14_5,
5599                 GP_6_18_FN, FN_IP14_4,
5600                 GP_6_17_FN, FN_IP14_3,
5601                 GP_6_16_FN, FN_IP14_2,
5602                 GP_6_15_FN, FN_IP14_1_0,
5603                 GP_6_14_FN, FN_IP13_30_28,
5604                 GP_6_13_FN, FN_IP13_27,
5605                 GP_6_12_FN, FN_IP13_26,
5606                 GP_6_11_FN, FN_IP13_25,
5607                 GP_6_10_FN, FN_IP13_24_23,
5608                 GP_6_9_FN, FN_IP13_22,
5609                 GP_6_8_FN, FN_SD1_CLK,
5610                 GP_6_7_FN, FN_IP13_21_19,
5611                 GP_6_6_FN, FN_IP13_18_16,
5612                 GP_6_5_FN, FN_IP13_15,
5613                 GP_6_4_FN, FN_IP13_14,
5614                 GP_6_3_FN, FN_IP13_13,
5615                 GP_6_2_FN, FN_IP13_12,
5616                 GP_6_1_FN, FN_IP13_11,
5617                 GP_6_0_FN, FN_IP13_10 }
5618         },
5619         { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
5620                 0, 0,
5621                 0, 0,
5622                 0, 0,
5623                 0, 0,
5624                 0, 0,
5625                 0, 0,
5626                 GP_7_25_FN, FN_USB1_PWEN,
5627                 GP_7_24_FN, FN_USB0_OVC,
5628                 GP_7_23_FN, FN_USB0_PWEN,
5629                 GP_7_22_FN, FN_IP15_14_12,
5630                 GP_7_21_FN, FN_IP15_11_9,
5631                 GP_7_20_FN, FN_IP15_8_6,
5632                 GP_7_19_FN, FN_IP7_2_0,
5633                 GP_7_18_FN, FN_IP6_29_27,
5634                 GP_7_17_FN, FN_IP6_26_24,
5635                 GP_7_16_FN, FN_IP6_23_21,
5636                 GP_7_15_FN, FN_IP6_20_19,
5637                 GP_7_14_FN, FN_IP6_18_16,
5638                 GP_7_13_FN, FN_IP6_15_14,
5639                 GP_7_12_FN, FN_IP6_13_12,
5640                 GP_7_11_FN, FN_IP6_11_10,
5641                 GP_7_10_FN, FN_IP6_9_8,
5642                 GP_7_9_FN, FN_IP16_11_10,
5643                 GP_7_8_FN, FN_IP16_9_8,
5644                 GP_7_7_FN, FN_IP16_7_6,
5645                 GP_7_6_FN, FN_IP16_5_3,
5646                 GP_7_5_FN, FN_IP16_2_0,
5647                 GP_7_4_FN, FN_IP15_29_27,
5648                 GP_7_3_FN, FN_IP15_26_24,
5649                 GP_7_2_FN, FN_IP15_23_21,
5650                 GP_7_1_FN, FN_IP15_20_18,
5651                 GP_7_0_FN, FN_IP15_17_15 }
5652         },
5653         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5654                              1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
5655                              1, 1, 1, 1, 1, 1, 1, 1) {
5656                 /* IP0_31 [1] */
5657                 0, 0,
5658                 /* IP0_30_29 [2] */
5659                 FN_A6, FN_MSIOF1_SCK,
5660                 0, 0,
5661                 /* IP0_28_27 [2] */
5662                 FN_A5, FN_MSIOF0_RXD_B,
5663                 0, 0,
5664                 /* IP0_26_25 [2] */
5665                 FN_A4, FN_MSIOF0_TXD_B,
5666                 0, 0,
5667                 /* IP0_24_23 [2] */
5668                 FN_A3, FN_MSIOF0_SS2_B,
5669                 0, 0,
5670                 /* IP0_22_21 [2] */
5671                 FN_A2, FN_MSIOF0_SS1_B,
5672                 0, 0,
5673                 /* IP0_20_19 [2] */
5674                 FN_A1, FN_MSIOF0_SYNC_B,
5675                 0, 0,
5676                 /* IP0_18_16 [3] */
5677                 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
5678                 0, 0, 0,
5679                 /* IP0_15 [1] */
5680                 FN_D15, 0,
5681                 /* IP0_14 [1] */
5682                 FN_D14, 0,
5683                 /* IP0_13 [1] */
5684                 FN_D13, 0,
5685                 /* IP0_12 [1] */
5686                 FN_D12, 0,
5687                 /* IP0_11 [1] */
5688                 FN_D11, 0,
5689                 /* IP0_10 [1] */
5690                 FN_D10, 0,
5691                 /* IP0_9 [1] */
5692                 FN_D9, 0,
5693                 /* IP0_8 [1] */
5694                 FN_D8, 0,
5695                 /* IP0_7 [1] */
5696                 FN_D7, 0,
5697                 /* IP0_6 [1] */
5698                 FN_D6, 0,
5699                 /* IP0_5 [1] */
5700                 FN_D5, 0,
5701                 /* IP0_4 [1] */
5702                 FN_D4, 0,
5703                 /* IP0_3 [1] */
5704                 FN_D3, 0,
5705                 /* IP0_2 [1] */
5706                 FN_D2, 0,
5707                 /* IP0_1 [1] */
5708                 FN_D1, 0,
5709                 /* IP0_0 [1] */
5710                 FN_D0, 0, }
5711         },
5712         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5713                              3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5714                 /* IP1_31_29 [3] */
5715                 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5716                 0, 0, 0,
5717                 /* IP1_28_26 [3] */
5718                 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
5719                 0, 0, 0, 0,
5720                 /* IP1_25_23 [3] */
5721                 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5722                 0, 0, 0,
5723                 /* IP1_22_20 [3] */
5724                 FN_A15, FN_BPFCLK_C,
5725                 0, 0, 0, 0, 0, 0,
5726                 /* IP1_19_17 [3] */
5727                 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5728                 0, 0, 0,
5729                 /* IP1_16_14 [3] */
5730                 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5731                 0, 0, 0, 0,
5732                 /* IP1_13_11 [3] */
5733                 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
5734                 0, 0, 0, 0,
5735                 /* IP1_10_8 [3] */
5736                 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
5737                 0, 0, 0, 0,
5738                 /* IP1_7_6 [2] */
5739                 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5740                 /* IP1_5_4 [2] */
5741                 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
5742                 /* IP1_3_2 [2] */
5743                 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5744                 /* IP1_1_0 [2] */
5745                 FN_A7, FN_MSIOF1_SYNC,
5746                 0, 0, }
5747         },
5748         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5749                              2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
5750                 /* IP2_31_30 [2] */
5751                 0, 0, 0, 0,
5752                 /* IP2_29_27 [3] */
5753                 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5754                 FN_ATAG0_N, 0, FN_EX_WAIT1,
5755                 0, 0,
5756                 /* IP2_26_25 [2] */
5757                 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5758                 /* IP2_24_23 [2] */
5759                 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5760                 /* IP2_22_21 [2] */
5761                 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
5762                 /* IP2_20_19 [2] */
5763                 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
5764                 /* IP2_18_16 [3] */
5765                 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5766                 0, 0,
5767                 /* IP2_15_13 [3] */
5768                 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5769                 0, 0, 0,
5770                 /* IP2_12_10 [3] */
5771                 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5772                 0, 0, 0,
5773                 /* IP2_9_7 [3] */
5774                 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5775                 0, 0, 0,
5776                 /* IP2_6_5 [2] */
5777                 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5778                 /* IP2_4_3 [2] */
5779                 FN_A20, FN_SPCLK, 0, 0,
5780                 /* IP2_2_0 [3] */
5781                 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5782                 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
5783         },
5784         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5785                              1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
5786                 /* IP3_31 [1] */
5787                 0, 0,
5788                 /* IP3_30_28 [3] */
5789                 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5790                 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5791                 0, 0, 0,
5792                 /* IP3_27_25 [3] */
5793                 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5794                 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5795                 0, 0, 0,
5796                 /* IP3_24_22 [3] */
5797                 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5798                 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5799                 /* IP3_21_20 [2] */
5800                 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5801                 /* IP3_19_18 [2] */
5802                 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5803                 /* IP3_17_16 [2] */
5804                 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5805                 /* IP3_15_14 [2] */
5806                 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5807                 /* IP3_13_12 [2] */
5808                 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5809                 /* IP3_11_9 [3] */
5810                 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5811                 0, 0, 0,
5812                 /* IP3_8_6 [3] */
5813                 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5814                 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5815                 /* IP3_5_3 [3] */
5816                 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5817                 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5818                 /* IP3_2_0 [3] */
5819                 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5820                 0, 0, 0, }
5821         },
5822         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5823                              1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5824                 /* IP4_31 [1] */
5825                 0, 0,
5826                 /* IP4_30_28 [3] */
5827                 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5828                 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5829                 0, 0,
5830                 /* IP4_27_26 [2] */
5831                 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5832                 /* IP4_25_24 [2] */
5833                 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5834                 /* IP4_23_22 [2] */
5835                 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5836                 /* IP4_21 [1] */
5837                 FN_SSI_SDATA3, 0,
5838                 /* IP4_20 [1] */
5839                 FN_SSI_WS34, 0,
5840                 /* IP4_19 [1] */
5841                 FN_SSI_SCK34, 0,
5842                 /* IP4_18_16 [3] */
5843                 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5844                 0, 0, 0, 0,
5845                 /* IP4_15_13 [3] */
5846                 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
5847                 FN_GLO_Q1_D, FN_HCTS1_N_E,
5848                 0, 0,
5849                 /* IP4_12_10 [3] */
5850                 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5851                 0, 0, 0,
5852                 /* IP4_9_8 [2] */
5853                 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
5854                 /* IP4_7_5 [3] */
5855                 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
5856                 FN_GLO_I1_D, 0, 0, 0,
5857                 /* IP4_4_2 [3] */
5858                 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
5859                 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5860                 0, 0, 0,
5861                 /* IP4_1_0 [2] */
5862                 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, }
5863         },
5864         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5865                              3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5866                 /* IP5_31_29 [3] */
5867                 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5868                 0, 0, 0, 0, 0,
5869                 /* IP5_28_26 [3] */
5870                 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5871                 0, 0, 0, 0,
5872                 /* IP5_25_24 [2] */
5873                 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5874                 /* IP5_23_22 [2] */
5875                 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5876                 /* IP5_21_20 [2] */
5877                 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5878                 /* IP5_19_17 [3] */
5879                 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5880                 0, 0, 0, 0,
5881                 /* IP5_16_15 [2] */
5882                 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5883                 /* IP5_14_12 [3] */
5884                 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5885                 0, 0, 0, 0,
5886                 /* IP5_11_9 [3] */
5887                 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5888                 0, 0, 0, 0,
5889                 /* IP5_8_6 [3] */
5890                 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5891                 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5892                 0, 0,
5893                 /* IP5_5_3 [3] */
5894                 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5895                 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5896                 0, 0,
5897                 /* IP5_2_0 [3] */
5898                 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5899                 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5900                 0, 0, }
5901         },
5902         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5903                              2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5904                 /* IP6_31_30 [2] */
5905                 0, 0, 0, 0,
5906                 /* IP6_29_27 [3] */
5907                 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5908                 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5909                 0, 0, 0,
5910                 /* IP6_26_24 [3] */
5911                 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5912                 FN_GPS_CLK_C, FN_GPS_CLK_D,
5913                 0, 0, 0,
5914                 /* IP6_23_21 [3] */
5915                 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5916                 FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
5917                 0, 0, 0,
5918                 /* IP6_20_19 [2] */
5919                 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
5920                 /* IP6_18_16 [3] */
5921                 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
5922                 FN_INTC_IRQ4_N, 0, 0, 0,
5923                 /* IP6_15_14 [2] */
5924                 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5925                 /* IP6_13_12 [2] */
5926                 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5927                 /* IP6_11_10 [2] */
5928                 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5929                 /* IP6_9_8 [2] */
5930                 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5931                 /* IP6_7_6 [2] */
5932                 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5933                 /* IP6_5_3 [3] */
5934                 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5935                 FN_SCIFA2_RXD, FN_FMIN_E,
5936                 0, 0,
5937                 /* IP6_2_0 [3] */
5938                 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5939                 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
5940                 0, 0, }
5941         },
5942         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5943                              2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
5944                 /* IP7_31_30 [2] */
5945                 0, 0, 0, 0,
5946                 /* IP7_29_27 [3] */
5947                 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
5948                 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
5949                 0, 0,
5950                 /* IP7_26_24 [3] */
5951                 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
5952                 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
5953                 0, 0,
5954                 /* IP7_23_21 [3] */
5955                 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
5956                 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
5957                 0, 0,
5958                 /* IP7_20_19 [2] */
5959                 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
5960                 /* IP7_18_17 [2] */
5961                 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
5962                 /* IP7_16_15 [2] */
5963                 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
5964                 /* IP7_14_13 [2] */
5965                 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
5966                 /* IP7_12_11 [2] */
5967                 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
5968                 /* IP7_10_9 [2] */
5969                 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
5970                 /* IP7_8_6 [3] */
5971                 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
5972                 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
5973                 0, 0,
5974                 /* IP7_5_3 [3] */
5975                 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
5976                 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
5977                 0, 0,
5978                 /* IP7_2_0 [3] */
5979                 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
5980                 FN_SCIF_CLK_B, FN_GPS_MAG_D,
5981                 0, 0, }
5982         },
5983         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5984                              1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
5985                 /* IP8_31 [1] */
5986                 0, 0,
5987                 /* IP8_30_28 [3] */
5988                 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
5989                 0, 0, 0,
5990                 /* IP8_27_26 [2] */
5991                 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
5992                 /* IP8_25_24 [2] */
5993                 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
5994                 /* IP8_23_21 [3] */
5995                 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
5996                 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
5997                 0, 0,
5998                 /* IP8_20_18 [3] */
5999                 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
6000                 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
6001                 0, 0,
6002                 /* IP8_17_15 [3] */
6003                 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
6004                 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
6005                 0, 0,
6006                 /* IP8_14_12 [3] */
6007                 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
6008                 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
6009                 0, 0, 0,
6010                 /* IP8_11_9 [3] */
6011                 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
6012                 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
6013                 0, 0, 0,
6014                 /* IP8_8_6 [3] */
6015                 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
6016                 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
6017                 0, 0,
6018                 /* IP8_5_3 [3] */
6019                 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
6020                 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
6021                 0, 0,
6022                 /* IP8_2_0 [3] */
6023                 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6024                 0, 0, 0, }
6025         },
6026         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6027                              3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
6028                 /* IP9_31_29 [3] */
6029                 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
6030                 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
6031                 /* IP9_28_27 [2] */
6032                 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
6033                 /* IP9_26_25 [2] */
6034                 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
6035                 /* IP9_24_23 [2] */
6036                 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
6037                 /* IP9_22_21 [2] */
6038                 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
6039                 /* IP9_20_19 [2] */
6040                 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
6041                 /* IP9_18_17 [2] */
6042                 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6043                 /* IP9_16 [1] */
6044                 FN_DU1_DISP, FN_QPOLA,
6045                 /* IP9_15_13 [3] */
6046                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
6047                 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
6048                 0, 0, 0,
6049                 /* IP9_12 [1] */
6050                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
6051                 /* IP9_11 [1] */
6052                 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
6053                 /* IP9_10_8 [3] */
6054                 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
6055                 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
6056                 0, 0,
6057                 /* IP9_7 [1] */
6058                 FN_DU1_DOTCLKOUT0, FN_QCLK,
6059                 /* IP9_6 [1] */
6060                 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
6061                 /* IP9_5_3 [3] */
6062                 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
6063                 FN_SCIF3_SCK, FN_SCIFA3_SCK,
6064                 0, 0, 0,
6065                 /* IP9_2_0 [3] */
6066                 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
6067                 0, 0, 0, }
6068         },
6069         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6070                              3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
6071                 /* IP10_31_29 [3] */
6072                 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
6073                 0, 0, 0,
6074                 /* IP10_28_27 [2] */
6075                 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
6076                 /* IP10_26_25 [2] */
6077                 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
6078                 /* IP10_24_22 [3] */
6079                 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
6080                 0, 0, 0,
6081                 /* IP10_21_19 [3] */
6082                 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
6083                 FN_TS_SDATA0_C, FN_ATACS11_N,
6084                 0, 0, 0,
6085                 /* IP10_18_17 [2] */
6086                 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6087                 /* IP10_16_15 [2] */
6088                 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6089                 /* IP10_14_12 [3] */
6090                 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
6091                 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6092                 /* IP10_11_9 [3] */
6093                 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
6094                 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
6095                 0, 0,
6096                 /* IP10_8_6 [3] */
6097                 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
6098                 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6099                 /* IP10_5_3 [3] */
6100                 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
6101                 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6102                 /* IP10_2_0 [3] */
6103                 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
6104                 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
6105         },
6106         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6107                              2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
6108                              3, 3, 3, 3, 3) {
6109                 /* IP11_31_30 [2] */
6110                 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6111                 /* IP11_29_28 [2] */
6112                 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
6113                 /* IP11_27 [1] */
6114                 FN_VI1_DATA7, FN_AVB_MDC,
6115                 /* IP11_26 [1] */
6116                 FN_VI1_DATA6, FN_AVB_MAGIC,
6117                 /* IP11_25 [1] */
6118                 FN_VI1_DATA5, FN_AVB_RX_DV,
6119                 /* IP11_24 [1] */
6120                 FN_VI1_DATA4, FN_AVB_MDIO,
6121                 /* IP11_23 [1] */
6122                 FN_VI1_DATA3, FN_AVB_RX_ER,
6123                 /* IP11_22 [1] */
6124                 FN_VI1_DATA2, FN_AVB_RXD7,
6125                 /* IP11_21 [1] */
6126                 FN_VI1_DATA1, FN_AVB_RXD6,
6127                 /* IP11_20 [1] */
6128                 FN_VI1_DATA0, FN_AVB_RXD5,
6129                 /* IP11_19 [1] */
6130                 FN_VI1_CLK, FN_AVB_RXD4,
6131                 /* IP11_18_17 [2] */
6132                 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6133                 /* IP11_16_15 [2] */
6134                 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6135                 /* IP11_14_12 [3] */
6136                 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6137                 FN_RX4_B, FN_SCIFA4_RXD_B,
6138                 0, 0, 0,
6139                 /* IP11_11_9 [3] */
6140                 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6141                 FN_TX4_B, FN_SCIFA4_TXD_B,
6142                 0, 0, 0,
6143                 /* IP11_8_6 [3] */
6144                 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6145                 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6146                 /* IP11_5_3 [3] */
6147                 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
6148                 0, 0, 0,
6149                 /* IP11_2_0 [3] */
6150                 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
6151                 FN_I2C1_SDA_D, 0, 0, 0, }
6152         },
6153         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6154                              2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
6155                 /* IP12_31_30 [2] */
6156                 0, 0, 0, 0,
6157                 /* IP12_29_27 [3] */
6158                 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6159                 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6160                 0, 0, 0,
6161                 /* IP12_26_24 [3] */
6162                 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6163                 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6164                 0, 0, 0,
6165                 /* IP12_23_22 [2] */
6166                 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6167                 /* IP12_21_20 [2] */
6168                 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6169                 /* IP12_19_18 [2] */
6170                 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6171                 /* IP12_17_16 [2] */
6172                 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6173                 /* IP12_15_13 [3] */
6174                 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6175                 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6176                 0, 0, 0,
6177                 /* IP12_12_10 [3] */
6178                 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6179                 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6180                 0, 0, 0,
6181                 /* IP12_9_7 [3] */
6182                 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6183                 FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
6184                 0, 0, 0,
6185                 /* IP12_6_4 [3] */
6186                 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6187                 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
6188                 0, 0, 0,
6189                 /* IP12_3_2 [2] */
6190                 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
6191                 /* IP12_1_0 [2] */
6192                 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, }
6193         },
6194         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6195                              1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
6196                              3, 2, 2, 3) {
6197                 /* IP13_31 [1] */
6198                 0, 0,
6199                 /* IP13_30_28 [3] */
6200                 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
6201                 0, 0, 0, 0,
6202                 /* IP13_27 [1] */
6203                 FN_SD1_DATA3, FN_IERX_B,
6204                 /* IP13_26 [1] */
6205                 FN_SD1_DATA2, FN_IECLK_B,
6206                 /* IP13_25 [1] */
6207                 FN_SD1_DATA1, FN_IETX_B,
6208                 /* IP13_24_23 [2] */
6209                 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6210                 /* IP13_22 [1] */
6211                 FN_SD1_CMD, FN_REMOCON_B,
6212                 /* IP13_21_19 [3] */
6213                 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6214                 FN_SCIFA5_RXD_B, FN_RX3_C,
6215                 0, 0,
6216                 /* IP13_18_16 [3] */
6217                 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6218                 FN_SCIFA5_TXD_B, FN_TX3_C,
6219                 0, 0,
6220                 /* IP13_15 [1] */
6221                 FN_SD0_DATA3, FN_SSL_B,
6222                 /* IP13_14 [1] */
6223                 FN_SD0_DATA2, FN_IO3_B,
6224                 /* IP13_13 [1] */
6225                 FN_SD0_DATA1, FN_IO2_B,
6226                 /* IP13_12 [1] */
6227                 FN_SD0_DATA0, FN_MISO_IO1_B,
6228                 /* IP13_11 [1] */
6229                 FN_SD0_CMD, FN_MOSI_IO0_B,
6230                 /* IP13_10 [1] */
6231                 FN_SD0_CLK, FN_SPCLK_B,
6232                 /* IP13_9_7 [3] */
6233                 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6234                 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6235                 0, 0, 0,
6236                 /* IP13_6_5 [2] */
6237                 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6238                 /* IP13_4_3 [2] */
6239                 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6240                 /* IP13_2_0 [3] */
6241                 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6242                 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6243                 0, 0, 0, }
6244         },
6245         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6246                              3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
6247                 /* IP14_31_29 [3] */
6248                 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6249                 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
6250                 /* IP14_28_26 [3] */
6251                 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6252                 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
6253                 /* IP14_25_23 [3] */
6254                 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6255                 0, 0, 0,
6256                 /* IP14_22_20 [3] */
6257                 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6258                 0, 0, 0,
6259                 /* IP14_19_17 [3] */
6260                 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6261                 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6262                 0, 0,
6263                 /* IP14_16_14 [3] */
6264                 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6265                 FN_VI1_CLK_C, FN_VI1_G0_B,
6266                 0, 0,
6267                 /* IP14_13_11 [3] */
6268                 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6269                 0, 0, 0,
6270                 /* IP14_10_8 [3] */
6271                 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6272                 0, 0, 0,
6273                 /* IP14_7 [1] */
6274                 FN_SD2_DATA3, FN_MMC_D3,
6275                 /* IP14_6 [1] */
6276                 FN_SD2_DATA2, FN_MMC_D2,
6277                 /* IP14_5 [1] */
6278                 FN_SD2_DATA1, FN_MMC_D1,
6279                 /* IP14_4 [1] */
6280                 FN_SD2_DATA0, FN_MMC_D0,
6281                 /* IP14_3 [1] */
6282                 FN_SD2_CMD, FN_MMC_CMD,
6283                 /* IP14_2 [1] */
6284                 FN_SD2_CLK, FN_MMC_CLK,
6285                 /* IP14_1_0 [2] */
6286                 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, }
6287         },
6288         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6289                              2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
6290                 /* IP15_31_30 [2] */
6291                 0, 0, 0, 0,
6292                 /* IP15_29_27 [3] */
6293                 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6294                 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6295                 0, 0,
6296                 /* IP15_26_24 [3] */
6297                 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6298                 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6299                 0, 0,
6300                 /* IP15_23_21 [3] */
6301                 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6302                 FN_TCLK2, FN_VI1_DATA3_C, 0,
6303                 /* IP15_20_18 [3] */
6304                 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6305                 0, 0, 0,
6306                 /* IP15_17_15 [3] */
6307                 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6308                 FN_TCLK1, FN_VI1_DATA1_C,
6309                 0, 0,
6310                 /* IP15_14_12 [3] */
6311                 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6312                 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6313                 0, 0,
6314                 /* IP15_11_9 [3] */
6315                 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6316                 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6317                 0, 0,
6318                 /* IP15_8_6 [3] */
6319                 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6320                 FN_PWM5_B, FN_SCIFA3_TXD_C,
6321                 0, 0, 0,
6322                 /* IP15_5_4 [2] */
6323                 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6324                 /* IP15_3_2 [2] */
6325                 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6326                 /* IP15_1_0 [2] */
6327                 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
6328         },
6329         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6330                              4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
6331                 /* IP16_31_28 [4] */
6332                 0, 0, 0, 0, 0, 0, 0, 0,
6333                 0, 0, 0, 0, 0, 0, 0, 0,
6334                 /* IP16_27_24 [4] */
6335                 0, 0, 0, 0, 0, 0, 0, 0,
6336                 0, 0, 0, 0, 0, 0, 0, 0,
6337                 /* IP16_23_20 [4] */
6338                 0, 0, 0, 0, 0, 0, 0, 0,
6339                 0, 0, 0, 0, 0, 0, 0, 0,
6340                 /* IP16_19_16 [4] */
6341                 0, 0, 0, 0, 0, 0, 0, 0,
6342                 0, 0, 0, 0, 0, 0, 0, 0,
6343                 /* IP16_15_12 [4] */
6344                 0, 0, 0, 0, 0, 0, 0, 0,
6345                 0, 0, 0, 0, 0, 0, 0, 0,
6346                 /* IP16_11_10 [2] */
6347                 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6348                 /* IP16_9_8 [2] */
6349                 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6350                 /* IP16_7_6 [2] */
6351                 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6352                 /* IP16_5_3 [3] */
6353                 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6354                 FN_GLO_SS_C, FN_VI1_DATA7_C,
6355                 0, 0, 0,
6356                 /* IP16_2_0 [3] */
6357                 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6358                 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6359                 0, 0, 0, }
6360         },
6361         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6362                              1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
6363                              3, 2, 2, 2, 1, 2, 2, 2) {
6364                 /* RESERVED [1] */
6365                 0, 0,
6366                 /* SEL_SCIF1 [2] */
6367                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6368                 /* SEL_SCIFB [2] */
6369                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6370                 /* SEL_SCIFB2 [2] */
6371                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6372                 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6373                 /* SEL_SCIFB1 [3] */
6374                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6375                 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6376                 0, 0, 0, 0,
6377                 /* SEL_SCIFA1 [2] */
6378                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6379                 /* SEL_SSI9 [1] */
6380                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6381                 /* SEL_SCFA [1] */
6382                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6383                 /* SEL_QSP [1] */
6384                 FN_SEL_QSP_0, FN_SEL_QSP_1,
6385                 /* SEL_SSI7 [1] */
6386                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6387                 /* SEL_HSCIF1 [3] */
6388                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6389                 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6390                 0, 0, 0,
6391                 /* RESERVED [2] */
6392                 0, 0, 0, 0,
6393                 /* SEL_VI1 [2] */
6394                 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6395                 /* RESERVED [2] */
6396                 0, 0, 0, 0,
6397                 /* SEL_TMU [1] */
6398                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6399                 /* SEL_LBS [2] */
6400                 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6401                 /* SEL_TSIF0 [2] */
6402                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6403                 /* SEL_SOF0 [2] */
6404                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
6405         },
6406         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6407                              3, 1, 1, 3, 2, 1, 1, 2, 2,
6408                              1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
6409                 /* SEL_SCIF0 [3] */
6410                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6411                 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6412                 0, 0, 0,
6413                 /* RESERVED [1] */
6414                 0, 0,
6415                 /* SEL_SCIF [1] */
6416                 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6417                 /* SEL_CAN0 [3] */
6418                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6419                 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6420                 0, 0,
6421                 /* SEL_CAN1 [2] */
6422                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6423                 /* RESERVED [1] */
6424                 0, 0,
6425                 /* SEL_SCIFA2 [1] */
6426                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6427                 /* SEL_SCIF4 [2] */
6428                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6429                 /* RESERVED [2] */
6430                 0, 0, 0, 0,
6431                 /* SEL_ADG [1] */
6432                 FN_SEL_ADG_0, FN_SEL_ADG_1,
6433                 /* SEL_FM [3] */
6434                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6435                 FN_SEL_FM_3, FN_SEL_FM_4,
6436                 0, 0, 0,
6437                 /* SEL_SCIFA5 [2] */
6438                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6439                 /* RESERVED [1] */
6440                 0, 0,
6441                 /* SEL_GPS [2] */
6442                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6443                 /* SEL_SCIFA4 [2] */
6444                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6445                 /* SEL_SCIFA3 [2] */
6446                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6447                 /* SEL_SIM [1] */
6448                 FN_SEL_SIM_0, FN_SEL_SIM_1,
6449                 /* RESERVED [1] */
6450                 0, 0,
6451                 /* SEL_SSI8 [1] */
6452                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
6453         },
6454         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6455                              2, 2, 2, 2, 2, 2, 2, 2,
6456                              1, 1, 2, 2, 3, 2, 2, 2, 1) {
6457                 /* SEL_HSCIF2 [2] */
6458                 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6459                 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6460                 /* SEL_CANCLK [2] */
6461                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6462                 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6463                 /* SEL_IIC1 [2] */
6464                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
6465                 /* SEL_IIC0 [2] */
6466                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6467                 /* SEL_I2C4 [2] */
6468                 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
6469                 /* SEL_I2C3 [2] */
6470                 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
6471                 /* SEL_SCIF3 [2] */
6472                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6473                 /* SEL_IEB [2] */
6474                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6475                 /* SEL_MMC [1] */
6476                 FN_SEL_MMC_0, FN_SEL_MMC_1,
6477                 /* SEL_SCIF5 [1] */
6478                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6479                 /* RESERVED [2] */
6480                 0, 0, 0, 0,
6481                 /* SEL_I2C2 [2] */
6482                 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
6483                 /* SEL_I2C1 [3] */
6484                 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
6485                 FN_SEL_I2C1_4,
6486                 0, 0, 0,
6487                 /* SEL_I2C0 [2] */
6488                 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
6489                 /* RESERVED [2] */
6490                 0, 0, 0, 0,
6491                 /* RESERVED [2] */
6492                 0, 0, 0, 0,
6493                 /* RESERVED [1] */
6494                 0, 0, }
6495         },
6496         { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6497                              3, 2, 2, 1, 1, 1, 1, 3, 2,
6498                              2, 3, 1, 1, 1, 2, 2, 2, 2) {
6499                 /* SEL_SOF1 [3] */
6500                 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6501                 FN_SEL_SOF1_4,
6502                 0, 0, 0,
6503                 /* SEL_HSCIF0 [2] */
6504                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6505                 /* SEL_DIS [2] */
6506                 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6507                 /* RESERVED [1] */
6508                 0, 0,
6509                 /* SEL_RAD [1] */
6510                 FN_SEL_RAD_0, FN_SEL_RAD_1,
6511                 /* SEL_RCN [1] */
6512                 FN_SEL_RCN_0, FN_SEL_RCN_1,
6513                 /* SEL_RSP [1] */
6514                 FN_SEL_RSP_0, FN_SEL_RSP_1,
6515                 /* SEL_SCIF2 [3] */
6516                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6517                 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6518                 0, 0, 0,
6519                 /* RESERVED [2] */
6520                 0, 0, 0, 0,
6521                 /* RESERVED [2] */
6522                 0, 0, 0, 0,
6523                 /* SEL_SOF2 [3] */
6524                 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6525                 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6526                 0, 0, 0,
6527                 /* RESERVED [1] */
6528                 0, 0,
6529                 /* SEL_SSI1 [1] */
6530                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6531                 /* SEL_SSI0 [1] */
6532                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6533                 /* SEL_SSP [2] */
6534                 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6535                 /* RESERVED [2] */
6536                 0, 0, 0, 0,
6537                 /* RESERVED [2] */
6538                 0, 0, 0, 0,
6539                 /* RESERVED [2] */
6540                 0, 0, 0, 0, }
6541         },
6542         { },
6543 };
6544
6545 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6546 {
6547         if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
6548                 return -EINVAL;
6549
6550         *pocctrl = 0xe606008c;
6551
6552         return 31 - (pin & 0x1f);
6553 }
6554
6555 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
6556         .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
6557 };
6558
6559 #ifdef CONFIG_PINCTRL_PFC_R8A7791
6560 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6561         .name = "r8a77910_pfc",
6562         .ops = &r8a7791_pinmux_ops,
6563         .unlock_reg = 0xe6060000, /* PMMR */
6564
6565         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6566
6567         .pins = pinmux_pins,
6568         .nr_pins = ARRAY_SIZE(pinmux_pins),
6569         .groups = pinmux_groups.common,
6570         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6571                      ARRAY_SIZE(pinmux_groups.r8a779x),
6572         .functions = pinmux_functions.common,
6573         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6574                         ARRAY_SIZE(pinmux_functions.r8a779x),
6575
6576         .cfg_regs = pinmux_config_regs,
6577
6578         .pinmux_data = pinmux_data,
6579         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6580 };
6581 #endif
6582
6583 #ifdef CONFIG_PINCTRL_PFC_R8A7793
6584 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6585         .name = "r8a77930_pfc",
6586         .ops = &r8a7791_pinmux_ops,
6587         .unlock_reg = 0xe6060000, /* PMMR */
6588
6589         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6590
6591         .pins = pinmux_pins,
6592         .nr_pins = ARRAY_SIZE(pinmux_pins),
6593         .groups = pinmux_groups.common,
6594         .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6595                      ARRAY_SIZE(pinmux_groups.r8a779x),
6596         .functions = pinmux_functions.common,
6597         .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6598                         ARRAY_SIZE(pinmux_functions.r8a779x),
6599
6600         .cfg_regs = pinmux_config_regs,
6601
6602         .pinmux_data = pinmux_data,
6603         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6604 };
6605 #endif