1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
6 #include <linux/gpio/driver.h>
7 #include <linux/interrupt.h>
8 #include <linux/module.h>
10 #include <linux/of_irq.h>
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinconf.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/types.h>
19 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
22 #include "../pinctrl-utils.h"
24 #define PMIC_GPIO_ADDRESS_RANGE 0x100
26 /* type and subtype registers base address offsets */
27 #define PMIC_GPIO_REG_TYPE 0x4
28 #define PMIC_GPIO_REG_SUBTYPE 0x5
30 /* GPIO peripheral type and subtype out_values */
31 #define PMIC_GPIO_TYPE 0x10
32 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
33 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
34 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
35 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
36 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
37 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
39 #define PMIC_MPP_REG_RT_STS 0x10
40 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
42 /* control register base address offsets */
43 #define PMIC_GPIO_REG_MODE_CTL 0x40
44 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
45 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
46 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
47 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
48 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
49 #define PMIC_GPIO_REG_EN_CTL 0x46
50 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
52 /* PMIC_GPIO_REG_MODE_CTL */
53 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
54 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
55 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
56 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
57 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
59 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
60 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
61 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
62 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
63 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
65 /* PMIC_GPIO_REG_DIG_VIN_CTL */
66 #define PMIC_GPIO_REG_VIN_SHIFT 0
67 #define PMIC_GPIO_REG_VIN_MASK 0x7
69 /* PMIC_GPIO_REG_DIG_PULL_CTL */
70 #define PMIC_GPIO_REG_PULL_SHIFT 0
71 #define PMIC_GPIO_REG_PULL_MASK 0x7
73 #define PMIC_GPIO_PULL_DOWN 4
74 #define PMIC_GPIO_PULL_DISABLE 5
76 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
77 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
78 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
79 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
81 /* PMIC_GPIO_REG_DIG_IN_CTL */
82 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
83 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
84 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
86 /* PMIC_GPIO_REG_DIG_OUT_CTL */
87 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
88 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
89 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
90 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
93 * Output type - indicates pin should be configured as push-pull,
94 * open drain or open source.
96 #define PMIC_GPIO_OUT_BUF_CMOS 0
97 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
98 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
100 /* PMIC_GPIO_REG_EN_CTL */
101 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
103 #define PMIC_GPIO_PHYSICAL_OFFSET 1
105 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
106 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
108 /* Qualcomm specific pin configurations */
109 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
110 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
111 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
112 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
113 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
115 /* The index of each function in pmic_gpio_functions[] array */
116 enum pmic_gpio_func_index {
117 PMIC_GPIO_FUNC_INDEX_NORMAL,
118 PMIC_GPIO_FUNC_INDEX_PAIRED,
119 PMIC_GPIO_FUNC_INDEX_FUNC1,
120 PMIC_GPIO_FUNC_INDEX_FUNC2,
121 PMIC_GPIO_FUNC_INDEX_FUNC3,
122 PMIC_GPIO_FUNC_INDEX_FUNC4,
123 PMIC_GPIO_FUNC_INDEX_DTEST1,
124 PMIC_GPIO_FUNC_INDEX_DTEST2,
125 PMIC_GPIO_FUNC_INDEX_DTEST3,
126 PMIC_GPIO_FUNC_INDEX_DTEST4,
130 * struct pmic_gpio_pad - keep current GPIO settings
131 * @base: Address base in SPMI device.
132 * @is_enabled: Set to false when GPIO should be put in high Z state.
133 * @out_value: Cached pin output value
134 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
135 * open-drain or open-source mode.
136 * @output_enabled: Set to true if GPIO output logic is enabled.
137 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
138 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
139 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
140 * @num_sources: Number of power-sources supported by this GPIO.
141 * @power_source: Current power-source used.
142 * @buffer_type: Push-pull, open-drain or open-source.
143 * @pullup: Constant current which flow trough GPIO output buffer.
144 * @strength: No, Low, Medium, High
145 * @function: See pmic_gpio_functions[]
146 * @atest: the ATEST selection for GPIO analog-pass-through mode
147 * @dtest_buffer: the DTEST buffer selection for digital input mode.
149 struct pmic_gpio_pad {
158 unsigned int num_sources;
159 unsigned int power_source;
160 unsigned int buffer_type;
162 unsigned int strength;
163 unsigned int function;
165 unsigned int dtest_buffer;
168 struct pmic_gpio_state {
171 struct pinctrl_dev *ctrl;
172 struct gpio_chip chip;
173 struct fwnode_handle *fwnode;
174 struct irq_domain *domain;
177 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
178 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
179 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
180 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
181 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
182 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
185 #ifdef CONFIG_DEBUG_FS
186 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
187 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
188 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
189 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
190 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
191 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
195 static const char *const pmic_gpio_groups[] = {
196 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
197 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
198 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
199 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
200 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
203 static const char *const pmic_gpio_functions[] = {
204 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
205 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
206 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
207 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
208 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
209 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
210 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
211 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
212 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
213 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
216 static int pmic_gpio_read(struct pmic_gpio_state *state,
217 struct pmic_gpio_pad *pad, unsigned int addr)
222 ret = regmap_read(state->map, pad->base + addr, &val);
224 dev_err(state->dev, "read 0x%x failed\n", addr);
231 static int pmic_gpio_write(struct pmic_gpio_state *state,
232 struct pmic_gpio_pad *pad, unsigned int addr,
237 ret = regmap_write(state->map, pad->base + addr, val);
239 dev_err(state->dev, "write 0x%x failed\n", addr);
244 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
246 /* Every PIN is a group */
247 return pctldev->desc->npins;
250 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
253 return pctldev->desc->pins[pin].name;
256 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
257 const unsigned **pins, unsigned *num_pins)
259 *pins = &pctldev->desc->pins[pin].number;
264 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
265 .get_groups_count = pmic_gpio_get_groups_count,
266 .get_group_name = pmic_gpio_get_group_name,
267 .get_group_pins = pmic_gpio_get_group_pins,
268 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
269 .dt_free_map = pinctrl_utils_free_map,
272 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
274 return ARRAY_SIZE(pmic_gpio_functions);
277 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
280 return pmic_gpio_functions[function];
283 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
285 const char *const **groups,
286 unsigned *const num_qgroups)
288 *groups = pmic_gpio_groups;
289 *num_qgroups = pctldev->desc->npins;
293 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
296 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
297 struct pmic_gpio_pad *pad;
301 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
302 pr_err("function: %d is not defined\n", function);
306 pad = pctldev->desc->pins[pin].drv_data;
308 * Non-LV/MV subtypes only support 2 special functions,
309 * offsetting the dtestx function values by 2
311 if (!pad->lv_mv_type) {
312 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
313 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
314 pr_err("LV/MV subtype doesn't have func3/func4\n");
317 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
318 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
319 PMIC_GPIO_FUNC_INDEX_FUNC3);
322 pad->function = function;
324 if (pad->analog_pass)
325 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
326 else if (pad->output_enabled && pad->input_enabled)
327 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
328 else if (pad->output_enabled)
329 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
331 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
333 if (pad->lv_mv_type) {
334 ret = pmic_gpio_write(state, pad,
335 PMIC_GPIO_REG_MODE_CTL, val);
339 val = pad->atest - 1;
340 ret = pmic_gpio_write(state, pad,
341 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
346 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
348 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
349 ret = pmic_gpio_write(state, pad,
350 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
354 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
355 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
356 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
358 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
363 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
365 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
368 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
369 .get_functions_count = pmic_gpio_get_functions_count,
370 .get_function_name = pmic_gpio_get_function_name,
371 .get_function_groups = pmic_gpio_get_function_groups,
372 .set_mux = pmic_gpio_set_mux,
375 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
376 unsigned int pin, unsigned long *config)
378 unsigned param = pinconf_to_config_param(*config);
379 struct pmic_gpio_pad *pad;
382 pad = pctldev->desc->pins[pin].drv_data;
385 case PIN_CONFIG_DRIVE_PUSH_PULL:
386 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
390 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
391 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
395 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
396 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
400 case PIN_CONFIG_BIAS_PULL_DOWN:
401 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
405 case PIN_CONFIG_BIAS_DISABLE:
406 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
410 case PIN_CONFIG_BIAS_PULL_UP:
411 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
415 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
420 case PIN_CONFIG_POWER_SOURCE:
421 arg = pad->power_source;
423 case PIN_CONFIG_INPUT_ENABLE:
424 if (!pad->input_enabled)
428 case PIN_CONFIG_OUTPUT:
429 arg = pad->out_value;
431 case PMIC_GPIO_CONF_PULL_UP:
434 case PMIC_GPIO_CONF_STRENGTH:
437 case PMIC_GPIO_CONF_ATEST:
440 case PMIC_GPIO_CONF_ANALOG_PASS:
441 arg = pad->analog_pass;
443 case PMIC_GPIO_CONF_DTEST_BUFFER:
444 arg = pad->dtest_buffer;
450 *config = pinconf_to_config_packed(param, arg);
454 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
455 unsigned long *configs, unsigned nconfs)
457 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
458 struct pmic_gpio_pad *pad;
463 pad = pctldev->desc->pins[pin].drv_data;
465 pad->is_enabled = true;
466 for (i = 0; i < nconfs; i++) {
467 param = pinconf_to_config_param(configs[i]);
468 arg = pinconf_to_config_argument(configs[i]);
471 case PIN_CONFIG_DRIVE_PUSH_PULL:
472 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
474 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
475 if (!pad->have_buffer)
477 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
479 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
480 if (!pad->have_buffer)
482 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
484 case PIN_CONFIG_BIAS_DISABLE:
485 pad->pullup = PMIC_GPIO_PULL_DISABLE;
487 case PIN_CONFIG_BIAS_PULL_UP:
488 pad->pullup = PMIC_GPIO_PULL_UP_30;
490 case PIN_CONFIG_BIAS_PULL_DOWN:
492 pad->pullup = PMIC_GPIO_PULL_DOWN;
494 pad->pullup = PMIC_GPIO_PULL_DISABLE;
496 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
497 pad->is_enabled = false;
499 case PIN_CONFIG_POWER_SOURCE:
500 if (arg >= pad->num_sources)
502 pad->power_source = arg;
504 case PIN_CONFIG_INPUT_ENABLE:
505 pad->input_enabled = arg ? true : false;
507 case PIN_CONFIG_OUTPUT:
508 pad->output_enabled = true;
509 pad->out_value = arg;
511 case PMIC_GPIO_CONF_PULL_UP:
512 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
516 case PMIC_GPIO_CONF_STRENGTH:
517 if (arg > PMIC_GPIO_STRENGTH_LOW)
521 case PMIC_GPIO_CONF_ATEST:
522 if (!pad->lv_mv_type || arg > 4)
526 case PMIC_GPIO_CONF_ANALOG_PASS:
527 if (!pad->lv_mv_type)
529 pad->analog_pass = true;
531 case PMIC_GPIO_CONF_DTEST_BUFFER:
534 pad->dtest_buffer = arg;
541 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
543 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
547 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
549 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
553 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
554 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
556 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
560 if (pad->dtest_buffer == 0) {
563 if (pad->lv_mv_type) {
564 val = pad->dtest_buffer - 1;
565 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
567 val = BIT(pad->dtest_buffer - 1);
570 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
574 if (pad->analog_pass)
575 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
576 else if (pad->output_enabled && pad->input_enabled)
577 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
578 else if (pad->output_enabled)
579 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
581 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
583 if (pad->lv_mv_type) {
584 ret = pmic_gpio_write(state, pad,
585 PMIC_GPIO_REG_MODE_CTL, val);
589 val = pad->atest - 1;
590 ret = pmic_gpio_write(state, pad,
591 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
596 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
598 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
599 ret = pmic_gpio_write(state, pad,
600 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
604 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
605 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
606 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
608 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
613 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
615 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
620 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
621 struct seq_file *s, unsigned pin)
623 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
624 struct pmic_gpio_pad *pad;
625 int ret, val, function;
627 static const char *const biases[] = {
628 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
629 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
631 static const char *const buffer_types[] = {
632 "push-pull", "open-drain", "open-source"
634 static const char *const strengths[] = {
635 "no", "high", "medium", "low"
638 pad = pctldev->desc->pins[pin].drv_data;
640 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
642 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
644 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
647 if (pad->input_enabled) {
648 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
652 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
653 pad->out_value = ret;
656 * For the non-LV/MV subtypes only 2 special functions are
657 * available, offsetting the dtest function values by 2.
659 function = pad->function;
660 if (!pad->lv_mv_type &&
661 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
662 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
663 PMIC_GPIO_FUNC_INDEX_FUNC3;
665 if (pad->analog_pass)
666 seq_puts(s, " analog-pass");
668 seq_printf(s, " %-4s",
669 pad->output_enabled ? "out" : "in");
670 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
671 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
672 seq_printf(s, " vin-%d", pad->power_source);
673 seq_printf(s, " %-27s", biases[pad->pullup]);
674 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
675 seq_printf(s, " %-7s", strengths[pad->strength]);
676 seq_printf(s, " atest-%d", pad->atest);
677 seq_printf(s, " dtest-%d", pad->dtest_buffer);
681 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
683 .pin_config_group_get = pmic_gpio_config_get,
684 .pin_config_group_set = pmic_gpio_config_set,
685 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
688 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
690 struct pmic_gpio_state *state = gpiochip_get_data(chip);
691 unsigned long config;
693 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
695 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
698 static int pmic_gpio_direction_output(struct gpio_chip *chip,
699 unsigned pin, int val)
701 struct pmic_gpio_state *state = gpiochip_get_data(chip);
702 unsigned long config;
704 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
706 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
709 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
711 struct pmic_gpio_state *state = gpiochip_get_data(chip);
712 struct pmic_gpio_pad *pad;
715 pad = state->ctrl->desc->pins[pin].drv_data;
717 if (!pad->is_enabled)
720 if (pad->input_enabled) {
721 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
725 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
728 return !!pad->out_value;
731 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
733 struct pmic_gpio_state *state = gpiochip_get_data(chip);
734 unsigned long config;
736 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
738 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
741 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
742 const struct of_phandle_args *gpio_desc,
745 if (chip->of_gpio_n_cells < 2)
749 *flags = gpio_desc->args[1];
751 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
754 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
756 struct pmic_gpio_state *state = gpiochip_get_data(chip);
757 struct irq_fwspec fwspec;
759 fwspec.fwnode = state->fwnode;
760 fwspec.param_count = 2;
761 fwspec.param[0] = pin + PMIC_GPIO_PHYSICAL_OFFSET;
763 * Set the type to a safe value temporarily. This will be overwritten
764 * later with the proper value by irq_set_type.
766 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
768 return irq_create_fwspec_mapping(&fwspec);
771 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
773 struct pmic_gpio_state *state = gpiochip_get_data(chip);
776 for (i = 0; i < chip->ngpio; i++) {
777 pmic_gpio_config_dbg_show(state->ctrl, s, i);
782 static const struct gpio_chip pmic_gpio_gpio_template = {
783 .direction_input = pmic_gpio_direction_input,
784 .direction_output = pmic_gpio_direction_output,
785 .get = pmic_gpio_get,
786 .set = pmic_gpio_set,
787 .request = gpiochip_generic_request,
788 .free = gpiochip_generic_free,
789 .of_xlate = pmic_gpio_of_xlate,
790 .to_irq = pmic_gpio_to_irq,
791 .dbg_show = pmic_gpio_dbg_show,
794 static int pmic_gpio_populate(struct pmic_gpio_state *state,
795 struct pmic_gpio_pad *pad)
797 int type, subtype, val, dir;
799 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
803 if (type != PMIC_GPIO_TYPE) {
804 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
809 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
814 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
815 pad->have_buffer = true;
816 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
817 pad->num_sources = 4;
819 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
820 pad->have_buffer = true;
821 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
822 pad->num_sources = 8;
824 case PMIC_GPIO_SUBTYPE_GPIO_LV:
825 pad->num_sources = 1;
826 pad->have_buffer = true;
827 pad->lv_mv_type = true;
829 case PMIC_GPIO_SUBTYPE_GPIO_MV:
830 pad->num_sources = 2;
831 pad->have_buffer = true;
832 pad->lv_mv_type = true;
835 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
839 if (pad->lv_mv_type) {
840 val = pmic_gpio_read(state, pad,
841 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
845 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
846 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
848 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
852 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
854 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
858 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
860 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
861 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
862 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
863 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
867 case PMIC_GPIO_MODE_DIGITAL_INPUT:
868 pad->input_enabled = true;
869 pad->output_enabled = false;
871 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
872 pad->input_enabled = false;
873 pad->output_enabled = true;
875 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
876 pad->input_enabled = true;
877 pad->output_enabled = true;
879 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
880 if (!pad->lv_mv_type)
882 pad->analog_pass = true;
885 dev_err(state->dev, "unknown GPIO direction\n");
889 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
893 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
894 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
896 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
900 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
901 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
903 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
907 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
909 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
910 else if (!pad->lv_mv_type)
911 pad->dtest_buffer = ffs(val);
913 pad->dtest_buffer = 0;
915 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
919 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
920 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
922 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
923 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
925 if (pad->lv_mv_type) {
926 val = pmic_gpio_read(state, pad,
927 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
930 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
933 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
934 pad->is_enabled = true;
938 static struct irq_chip pmic_gpio_irq_chip = {
940 .irq_ack = irq_chip_ack_parent,
941 .irq_mask = irq_chip_mask_parent,
942 .irq_unmask = irq_chip_unmask_parent,
943 .irq_set_type = irq_chip_set_type_parent,
944 .irq_set_wake = irq_chip_set_wake_parent,
945 .flags = IRQCHIP_MASK_ON_SUSPEND,
948 static int pmic_gpio_domain_translate(struct irq_domain *domain,
949 struct irq_fwspec *fwspec,
950 unsigned long *hwirq,
953 struct pmic_gpio_state *state = container_of(domain->host_data,
954 struct pmic_gpio_state,
957 if (fwspec->param_count != 2 ||
958 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
961 *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
962 *type = fwspec->param[1];
967 static int pmic_gpio_domain_alloc(struct irq_domain *domain, unsigned int virq,
968 unsigned int nr_irqs, void *data)
970 struct pmic_gpio_state *state = container_of(domain->host_data,
971 struct pmic_gpio_state,
973 struct irq_fwspec *fwspec = data;
974 struct irq_fwspec parent_fwspec;
975 irq_hw_number_t hwirq;
979 ret = pmic_gpio_domain_translate(domain, fwspec, &hwirq, &type);
983 for (i = 0; i < nr_irqs; i++)
984 irq_domain_set_info(domain, virq + i, hwirq + i,
985 &pmic_gpio_irq_chip, state,
986 handle_level_irq, NULL, NULL);
988 parent_fwspec.fwnode = domain->parent->fwnode;
989 parent_fwspec.param_count = 4;
990 parent_fwspec.param[0] = 0;
991 parent_fwspec.param[1] = hwirq + 0xc0;
992 parent_fwspec.param[2] = 0;
993 parent_fwspec.param[3] = fwspec->param[1];
995 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
999 static const struct irq_domain_ops pmic_gpio_domain_ops = {
1000 .activate = gpiochip_irq_domain_activate,
1001 .alloc = pmic_gpio_domain_alloc,
1002 .deactivate = gpiochip_irq_domain_deactivate,
1003 .free = irq_domain_free_irqs_common,
1004 .translate = pmic_gpio_domain_translate,
1007 static int pmic_gpio_probe(struct platform_device *pdev)
1009 struct irq_domain *parent_domain;
1010 struct device_node *parent_node;
1011 struct device *dev = &pdev->dev;
1012 struct pinctrl_pin_desc *pindesc;
1013 struct pinctrl_desc *pctrldesc;
1014 struct pmic_gpio_pad *pad, *pads;
1015 struct pmic_gpio_state *state;
1019 ret = of_property_read_u32(dev->of_node, "reg", ®);
1021 dev_err(dev, "missing base address");
1025 npins = (uintptr_t) device_get_match_data(&pdev->dev);
1027 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1031 platform_set_drvdata(pdev, state);
1033 state->dev = &pdev->dev;
1034 state->map = dev_get_regmap(dev->parent, NULL);
1036 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1040 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1044 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1048 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1049 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1050 pctrldesc->confops = &pmic_gpio_pinconf_ops;
1051 pctrldesc->owner = THIS_MODULE;
1052 pctrldesc->name = dev_name(dev);
1053 pctrldesc->pins = pindesc;
1054 pctrldesc->npins = npins;
1055 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1056 pctrldesc->custom_params = pmic_gpio_bindings;
1057 #ifdef CONFIG_DEBUG_FS
1058 pctrldesc->custom_conf_items = pmic_conf_items;
1061 for (i = 0; i < npins; i++, pindesc++) {
1063 pindesc->drv_data = pad;
1064 pindesc->number = i;
1065 pindesc->name = pmic_gpio_groups[i];
1067 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1069 ret = pmic_gpio_populate(state, pad);
1074 state->chip = pmic_gpio_gpio_template;
1075 state->chip.parent = dev;
1076 state->chip.base = -1;
1077 state->chip.ngpio = npins;
1078 state->chip.label = dev_name(dev);
1079 state->chip.of_gpio_n_cells = 2;
1080 state->chip.can_sleep = false;
1082 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1083 if (IS_ERR(state->ctrl))
1084 return PTR_ERR(state->ctrl);
1086 parent_node = of_irq_find_parent(state->dev->of_node);
1090 parent_domain = irq_find_host(parent_node);
1091 of_node_put(parent_node);
1095 state->fwnode = of_node_to_fwnode(state->dev->of_node);
1096 state->domain = irq_domain_create_hierarchy(parent_domain, 0,
1099 &pmic_gpio_domain_ops,
1104 ret = gpiochip_add_data(&state->chip, state);
1106 dev_err(state->dev, "can't add gpio chip\n");
1107 goto err_chip_add_data;
1111 * For DeviceTree-supported systems, the gpio core checks the
1112 * pinctrl's device node for the "gpio-ranges" property.
1113 * If it is present, it takes care of adding the pin ranges
1114 * for the driver. In this case the driver can skip ahead.
1116 * In order to remain compatible with older, existing DeviceTree
1117 * files which don't set the "gpio-ranges" property or systems that
1118 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1120 if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1121 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1124 dev_err(dev, "failed to add pin range\n");
1132 gpiochip_remove(&state->chip);
1134 irq_domain_remove(state->domain);
1138 static int pmic_gpio_remove(struct platform_device *pdev)
1140 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1142 gpiochip_remove(&state->chip);
1143 irq_domain_remove(state->domain);
1147 static const struct of_device_id pmic_gpio_of_match[] = {
1148 { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1149 { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1150 { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1151 { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1152 { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1153 { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1154 { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1155 { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1156 /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1157 { .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1161 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1163 static struct platform_driver pmic_gpio_driver = {
1165 .name = "qcom-spmi-gpio",
1166 .of_match_table = pmic_gpio_of_match,
1168 .probe = pmic_gpio_probe,
1169 .remove = pmic_gpio_remove,
1172 module_platform_driver(pmic_gpio_driver);
1174 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1175 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1176 MODULE_ALIAS("platform:qcom-spmi-gpio");
1177 MODULE_LICENSE("GPL v2");