3 #include <hwspinlock.h>
6 #include <asm/arch/gpio.h>
9 #include <dm/device_compat.h>
11 #include <dm/pinctrl.h>
12 #include <linux/err.h>
13 #include <linux/libfdt.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define MAX_PINS_ONE_IP 70
18 #define MODE_BITS_MASK 3
24 struct stm32_pinctrl_priv {
25 struct hwspinlock hws;
27 struct list_head gpio_dev;
30 struct stm32_gpio_bank {
31 struct udevice *gpio_dev;
32 struct list_head list;
35 #ifndef CONFIG_SPL_BUILD
37 static char pin_name[PINNAME_SIZE];
38 #define PINMUX_MODE_COUNT 5
39 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
47 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
49 struct stm32_gpio_priv *priv = dev_get_priv(dev);
50 struct stm32_gpio_regs *regs = priv->regs;
52 u32 alt_shift = (offset % 8) * 4;
53 u32 alt_index = offset / 8;
55 af = (readl(®s->afr[alt_index]) &
56 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
61 static int stm32_populate_gpio_dev_list(struct udevice *dev)
63 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
64 struct udevice *gpio_dev;
65 struct udevice *child;
66 struct stm32_gpio_bank *gpio_bank;
70 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
71 * a list with all gpio device reference which belongs to the
72 * current pin-controller. This list is used to find pin_name and
75 list_for_each_entry(child, &dev->child_head, sibling_node) {
76 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
81 gpio_bank = malloc(sizeof(*gpio_bank));
83 dev_err(dev, "Not enough memory\n");
87 gpio_bank->gpio_dev = gpio_dev;
88 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
94 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
96 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
97 struct gpio_dev_priv *uc_priv;
98 struct stm32_gpio_bank *gpio_bank;
101 * if get_pins_count has already been executed once on this
102 * pin-controller, no need to run it again
104 if (priv->pinctrl_ngpios)
105 return priv->pinctrl_ngpios;
107 if (list_empty(&priv->gpio_dev))
108 stm32_populate_gpio_dev_list(dev);
110 * walk through all banks to retrieve the pin-controller
113 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
114 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
116 priv->pinctrl_ngpios += uc_priv->gpio_count;
119 return priv->pinctrl_ngpios;
122 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
123 unsigned int selector,
126 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
127 struct stm32_gpio_bank *gpio_bank;
128 struct gpio_dev_priv *uc_priv;
131 if (list_empty(&priv->gpio_dev))
132 stm32_populate_gpio_dev_list(dev);
134 /* look up for the bank which owns the requested pin */
135 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
136 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
138 if (selector < (pin_count + uc_priv->gpio_count)) {
140 * we found the bank, convert pin selector to
143 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
144 selector - pin_count);
145 if (IS_ERR_VALUE(*idx))
148 return gpio_bank->gpio_dev;
150 pin_count += uc_priv->gpio_count;
156 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
157 unsigned int selector)
159 struct gpio_dev_priv *uc_priv;
160 struct udevice *gpio_dev;
161 unsigned int gpio_idx;
163 /* look up for the bank which owns the requested pin */
164 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
166 snprintf(pin_name, PINNAME_SIZE, "Error");
168 uc_priv = dev_get_uclass_priv(gpio_dev);
170 snprintf(pin_name, PINNAME_SIZE, "%s%d",
178 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
179 unsigned int selector,
183 struct udevice *gpio_dev;
187 unsigned int gpio_idx;
189 /* look up for the bank which owns the requested pin */
190 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
195 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
197 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
198 selector, gpio_idx, mode);
203 /* should never happen */
206 snprintf(buf, size, "%s", pinmux_mode[mode]);
209 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
210 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
214 snprintf(buf, size, "%s %s",
215 pinmux_mode[mode], label ? label : "");
224 static int stm32_pinctrl_probe(struct udevice *dev)
226 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
229 INIT_LIST_HEAD(&priv->gpio_dev);
231 /* hwspinlock property is optional, just log the error */
232 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
234 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
240 static int stm32_gpio_config(struct gpio_desc *desc,
241 const struct stm32_gpio_ctl *ctl)
243 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
244 struct stm32_gpio_regs *regs = priv->regs;
245 struct stm32_pinctrl_priv *ctrl_priv;
249 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
250 ctl->pupd > 2 || ctl->speed > 3)
253 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
254 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
256 dev_err(desc->dev, "HWSpinlock timeout\n");
260 index = (desc->offset & 0x07) * 4;
261 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
264 index = desc->offset * 2;
265 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
267 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
268 ctl->speed << index);
269 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
271 index = desc->offset;
272 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
274 hwspinlock_unlock(&ctrl_priv->hws);
279 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
281 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
282 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
283 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
289 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
296 gpio_ctl->mode = STM32_GPIO_MODE_IN;
299 gpio_ctl->mode = STM32_GPIO_MODE_AF;
300 gpio_ctl->af = gpio_fn - 1;
303 gpio_ctl->mode = STM32_GPIO_MODE_AN;
306 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
310 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
312 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
313 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
315 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
317 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
318 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
319 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
320 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
322 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
324 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
325 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
331 static int stm32_pinctrl_config(int offset)
333 u32 pin_mux[MAX_PINS_ONE_IP];
337 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
338 * usart1) of pin controller phandle "pinctrl-0"
340 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
341 struct stm32_gpio_dsc gpio_dsc;
342 struct stm32_gpio_ctl gpio_ctl;
345 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
347 ARRAY_SIZE(pin_mux));
348 debug("%s: no of pinmux entries= %d\n", __func__, len);
351 for (i = 0; i < len; i++) {
352 struct gpio_desc desc;
354 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
355 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
356 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
357 rv = uclass_get_device_by_seq(UCLASS_GPIO,
362 desc.offset = gpio_dsc.pin;
363 rv = stm32_gpio_config(&desc, &gpio_ctl);
364 debug("%s: rv = %d\n\n", __func__, rv);
373 static int stm32_pinctrl_bind(struct udevice *dev)
379 dev_for_each_subnode(node, dev) {
380 debug("%s: bind %s\n", __func__, ofnode_get_name(node));
382 ofnode_get_property(node, "gpio-controller", &ret);
385 /* Get the name of each gpio node */
386 name = ofnode_get_name(node);
390 /* Bind each gpio node */
391 ret = device_bind_driver_to_node(dev, "gpio_stm32",
396 debug("%s: bind %s\n", __func__, name);
402 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
403 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
405 return stm32_pinctrl_config(dev_of_offset(config));
407 #else /* PINCTRL_FULL */
408 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
409 struct udevice *periph)
411 const void *fdt = gd->fdt_blob;
417 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
421 debug("%s: periph->name = %s\n", __func__, periph->name);
423 size /= sizeof(*list);
424 for (i = 0; i < size; i++) {
425 phandle = fdt32_to_cpu(*list++);
427 config_node = fdt_node_offset_by_phandle(fdt, phandle);
428 if (config_node < 0) {
429 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
433 ret = stm32_pinctrl_config(config_node);
440 #endif /* PINCTRL_FULL */
442 static struct pinctrl_ops stm32_pinctrl_ops = {
443 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
444 .set_state = stm32_pinctrl_set_state,
445 #else /* PINCTRL_FULL */
446 .set_state_simple = stm32_pinctrl_set_state_simple,
447 #endif /* PINCTRL_FULL */
448 #ifndef CONFIG_SPL_BUILD
449 .get_pin_name = stm32_pinctrl_get_pin_name,
450 .get_pins_count = stm32_pinctrl_get_pins_count,
451 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
455 static const struct udevice_id stm32_pinctrl_ids[] = {
456 { .compatible = "st,stm32f429-pinctrl" },
457 { .compatible = "st,stm32f469-pinctrl" },
458 { .compatible = "st,stm32f746-pinctrl" },
459 { .compatible = "st,stm32f769-pinctrl" },
460 { .compatible = "st,stm32h743-pinctrl" },
461 { .compatible = "st,stm32mp157-pinctrl" },
462 { .compatible = "st,stm32mp157-z-pinctrl" },
466 U_BOOT_DRIVER(pinctrl_stm32) = {
467 .name = "pinctrl_stm32",
468 .id = UCLASS_PINCTRL,
469 .of_match = stm32_pinctrl_ids,
470 .ops = &stm32_pinctrl_ops,
471 .bind = stm32_pinctrl_bind,
472 .probe = stm32_pinctrl_probe,
473 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),