3 #include <dm/pinctrl.h>
4 #include <asm/arch/gpio.h>
8 DECLARE_GLOBAL_DATA_PTR;
10 #define MAX_PINS_ONE_IP 70
11 #define MODE_BITS_MASK 3
17 #ifndef CONFIG_SPL_BUILD
18 struct stm32_pinctrl_priv {
20 struct list_head gpio_dev;
23 struct stm32_gpio_bank {
24 struct udevice *gpio_dev;
25 struct list_head list;
28 #define MAX_PIN_PER_BANK 16
30 static char pin_name[PINNAME_SIZE];
31 #define PINMUX_MODE_COUNT 5
32 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
40 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
42 struct stm32_gpio_priv *priv = dev_get_priv(dev);
43 struct stm32_gpio_regs *regs = priv->regs;
45 u32 alt_shift = (offset % 8) * 4;
46 u32 alt_index = offset / 8;
48 af = (readl(®s->afr[alt_index]) &
49 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
54 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
56 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
57 struct gpio_dev_priv *uc_priv;
58 struct stm32_gpio_bank *gpio_bank;
61 * if get_pins_count has already been executed once on this
62 * pin-controller, no need to run it again
64 if (priv->pinctrl_ngpios)
65 return priv->pinctrl_ngpios;
68 * walk through all banks to retrieve the pin-controller
71 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
72 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
74 priv->pinctrl_ngpios += uc_priv->gpio_count;
77 return priv->pinctrl_ngpios;
80 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
81 unsigned int selector)
83 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
84 struct stm32_gpio_bank *gpio_bank;
85 struct gpio_dev_priv *uc_priv;
88 /* look up for the bank which owns the requested pin */
89 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
90 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
92 if (selector < (first_pin + uc_priv->gpio_count))
93 /* we found the bank */
94 return gpio_bank->gpio_dev;
96 first_pin += uc_priv->gpio_count;
102 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
103 unsigned int selector)
105 struct gpio_dev_priv *uc_priv;
106 struct udevice *gpio_dev;
108 /* look up for the bank which owns the requested pin */
109 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
111 snprintf(pin_name, PINNAME_SIZE, "Error");
113 uc_priv = dev_get_uclass_priv(gpio_dev);
115 snprintf(pin_name, PINNAME_SIZE, "%s%d",
117 selector % MAX_PIN_PER_BANK);
123 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
124 unsigned int selector,
128 struct udevice *gpio_dev;
134 /* look up for the bank which owns the requested pin */
135 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
140 /* translate pin-controller pin number to gpio pin number */
141 gpio_pin = selector % MAX_PIN_PER_BANK;
143 mode = gpio_get_raw_function(gpio_dev, gpio_pin, &label);
145 dev_dbg(dev, "selector = %d gpio_pin = %d mode = %d\n",
146 selector, gpio_pin, mode);
150 /* should never happen */
153 snprintf(buf, size, "%s", pinmux_mode[mode]);
156 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_pin);
157 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
161 snprintf(buf, size, "%s %s",
162 pinmux_mode[mode], label ? label : "");
169 int stm32_pinctrl_probe(struct udevice *dev)
171 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
172 struct udevice *gpio_dev;
173 struct udevice *child;
174 struct stm32_gpio_bank *gpio_bank;
177 INIT_LIST_HEAD(&priv->gpio_dev);
180 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
181 * a list with all gpio device reference which belongs to the
182 * current pin-controller. This list is used to find pin_name and
185 list_for_each_entry(child, &dev->child_head, sibling_node) {
186 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
191 gpio_bank = malloc(sizeof(*gpio_bank));
193 dev_err(dev, "Not enough memory\n");
197 gpio_bank->gpio_dev = gpio_dev;
198 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
205 static int stm32_gpio_config(struct gpio_desc *desc,
206 const struct stm32_gpio_ctl *ctl)
208 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
209 struct stm32_gpio_regs *regs = priv->regs;
212 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
213 ctl->pupd > 2 || ctl->speed > 3)
216 index = (desc->offset & 0x07) * 4;
217 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
220 index = desc->offset * 2;
221 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
223 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
224 ctl->speed << index);
225 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
227 index = desc->offset;
228 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
233 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
235 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
236 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
237 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
243 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
250 gpio_ctl->mode = STM32_GPIO_MODE_IN;
253 gpio_ctl->mode = STM32_GPIO_MODE_AF;
254 gpio_ctl->af = gpio_fn - 1;
257 gpio_ctl->mode = STM32_GPIO_MODE_AN;
260 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
264 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
266 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
267 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
269 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
271 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
272 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
273 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
274 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
276 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
278 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
279 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
285 static int stm32_pinctrl_config(int offset)
287 u32 pin_mux[MAX_PINS_ONE_IP];
291 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
292 * usart1) of pin controller phandle "pinctrl-0"
294 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
295 struct stm32_gpio_dsc gpio_dsc;
296 struct stm32_gpio_ctl gpio_ctl;
299 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
301 ARRAY_SIZE(pin_mux));
302 debug("%s: no of pinmux entries= %d\n", __func__, len);
305 for (i = 0; i < len; i++) {
306 struct gpio_desc desc;
308 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
309 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
310 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
311 rv = uclass_get_device_by_seq(UCLASS_GPIO,
316 desc.offset = gpio_dsc.pin;
317 rv = stm32_gpio_config(&desc, &gpio_ctl);
318 debug("%s: rv = %d\n\n", __func__, rv);
327 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
328 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
330 return stm32_pinctrl_config(dev_of_offset(config));
332 #else /* PINCTRL_FULL */
333 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
334 struct udevice *periph)
336 const void *fdt = gd->fdt_blob;
342 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
346 debug("%s: periph->name = %s\n", __func__, periph->name);
348 size /= sizeof(*list);
349 for (i = 0; i < size; i++) {
350 phandle = fdt32_to_cpu(*list++);
352 config_node = fdt_node_offset_by_phandle(fdt, phandle);
353 if (config_node < 0) {
354 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
358 ret = stm32_pinctrl_config(config_node);
365 #endif /* PINCTRL_FULL */
367 static struct pinctrl_ops stm32_pinctrl_ops = {
368 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
369 .set_state = stm32_pinctrl_set_state,
370 #else /* PINCTRL_FULL */
371 .set_state_simple = stm32_pinctrl_set_state_simple,
372 #endif /* PINCTRL_FULL */
373 #ifndef CONFIG_SPL_BUILD
374 .get_pin_name = stm32_pinctrl_get_pin_name,
375 .get_pins_count = stm32_pinctrl_get_pins_count,
376 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
380 static const struct udevice_id stm32_pinctrl_ids[] = {
381 { .compatible = "st,stm32f429-pinctrl" },
382 { .compatible = "st,stm32f469-pinctrl" },
383 { .compatible = "st,stm32f746-pinctrl" },
384 { .compatible = "st,stm32h743-pinctrl" },
385 { .compatible = "st,stm32mp157-pinctrl" },
386 { .compatible = "st,stm32mp157-z-pinctrl" },
390 U_BOOT_DRIVER(pinctrl_stm32) = {
391 .name = "pinctrl_stm32",
392 .id = UCLASS_PINCTRL,
393 .of_match = stm32_pinctrl_ids,
394 .ops = &stm32_pinctrl_ops,
395 .bind = dm_scan_fdt_dev,
396 #ifndef CONFIG_SPL_BUILD
397 .probe = stm32_pinctrl_probe,
398 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),