3 #include <dm/pinctrl.h>
4 #include <hwspinlock.h>
5 #include <asm/arch/gpio.h>
9 DECLARE_GLOBAL_DATA_PTR;
11 #define MAX_PINS_ONE_IP 70
12 #define MODE_BITS_MASK 3
18 struct stm32_pinctrl_priv {
19 struct hwspinlock hws;
21 struct list_head gpio_dev;
24 struct stm32_gpio_bank {
25 struct udevice *gpio_dev;
26 struct list_head list;
29 #ifndef CONFIG_SPL_BUILD
31 #define MAX_PIN_PER_BANK 16
33 static char pin_name[PINNAME_SIZE];
34 #define PINMUX_MODE_COUNT 5
35 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
43 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
45 struct stm32_gpio_priv *priv = dev_get_priv(dev);
46 struct stm32_gpio_regs *regs = priv->regs;
48 u32 alt_shift = (offset % 8) * 4;
49 u32 alt_index = offset / 8;
51 af = (readl(®s->afr[alt_index]) &
52 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
57 static int stm32_populate_gpio_dev_list(struct udevice *dev)
59 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
60 struct udevice *gpio_dev;
61 struct udevice *child;
62 struct stm32_gpio_bank *gpio_bank;
66 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
67 * a list with all gpio device reference which belongs to the
68 * current pin-controller. This list is used to find pin_name and
71 list_for_each_entry(child, &dev->child_head, sibling_node) {
72 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
77 gpio_bank = malloc(sizeof(*gpio_bank));
79 dev_err(dev, "Not enough memory\n");
83 gpio_bank->gpio_dev = gpio_dev;
84 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
90 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
92 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
93 struct gpio_dev_priv *uc_priv;
94 struct stm32_gpio_bank *gpio_bank;
97 * if get_pins_count has already been executed once on this
98 * pin-controller, no need to run it again
100 if (priv->pinctrl_ngpios)
101 return priv->pinctrl_ngpios;
103 if (list_empty(&priv->gpio_dev))
104 stm32_populate_gpio_dev_list(dev);
106 * walk through all banks to retrieve the pin-controller
109 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
110 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
112 priv->pinctrl_ngpios += uc_priv->gpio_count;
115 return priv->pinctrl_ngpios;
118 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
119 unsigned int selector)
121 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
122 struct stm32_gpio_bank *gpio_bank;
123 struct gpio_dev_priv *uc_priv;
126 if (list_empty(&priv->gpio_dev))
127 stm32_populate_gpio_dev_list(dev);
129 /* look up for the bank which owns the requested pin */
130 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
131 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
133 if (selector < (first_pin + uc_priv->gpio_count))
134 /* we found the bank */
135 return gpio_bank->gpio_dev;
137 first_pin += uc_priv->gpio_count;
143 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
144 unsigned int selector)
146 struct gpio_dev_priv *uc_priv;
147 struct udevice *gpio_dev;
149 /* look up for the bank which owns the requested pin */
150 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
152 snprintf(pin_name, PINNAME_SIZE, "Error");
154 uc_priv = dev_get_uclass_priv(gpio_dev);
156 snprintf(pin_name, PINNAME_SIZE, "%s%d",
158 selector % MAX_PIN_PER_BANK);
164 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
165 unsigned int selector,
169 struct udevice *gpio_dev;
175 /* look up for the bank which owns the requested pin */
176 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
181 /* translate pin-controller pin number to gpio pin number */
182 gpio_pin = selector % MAX_PIN_PER_BANK;
184 mode = gpio_get_raw_function(gpio_dev, gpio_pin, &label);
186 dev_dbg(dev, "selector = %d gpio_pin = %d mode = %d\n",
187 selector, gpio_pin, mode);
191 /* should never happen */
194 snprintf(buf, size, "%s", pinmux_mode[mode]);
197 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_pin);
198 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
202 snprintf(buf, size, "%s %s",
203 pinmux_mode[mode], label ? label : "");
212 int stm32_pinctrl_probe(struct udevice *dev)
214 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
217 INIT_LIST_HEAD(&priv->gpio_dev);
219 /* hwspinlock property is optional, just log the error */
220 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
222 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
228 static int stm32_gpio_config(struct gpio_desc *desc,
229 const struct stm32_gpio_ctl *ctl)
231 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
232 struct stm32_gpio_regs *regs = priv->regs;
233 struct stm32_pinctrl_priv *ctrl_priv;
237 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
238 ctl->pupd > 2 || ctl->speed > 3)
241 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
242 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
244 dev_err(desc->dev, "HWSpinlock timeout\n");
248 index = (desc->offset & 0x07) * 4;
249 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
252 index = desc->offset * 2;
253 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
255 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
256 ctl->speed << index);
257 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
259 index = desc->offset;
260 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
262 hwspinlock_unlock(&ctrl_priv->hws);
267 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
269 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
270 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
271 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
277 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
284 gpio_ctl->mode = STM32_GPIO_MODE_IN;
287 gpio_ctl->mode = STM32_GPIO_MODE_AF;
288 gpio_ctl->af = gpio_fn - 1;
291 gpio_ctl->mode = STM32_GPIO_MODE_AN;
294 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
298 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
300 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
301 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
303 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
305 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
306 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
307 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
308 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
310 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
312 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
313 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
319 static int stm32_pinctrl_config(int offset)
321 u32 pin_mux[MAX_PINS_ONE_IP];
325 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
326 * usart1) of pin controller phandle "pinctrl-0"
328 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
329 struct stm32_gpio_dsc gpio_dsc;
330 struct stm32_gpio_ctl gpio_ctl;
333 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
335 ARRAY_SIZE(pin_mux));
336 debug("%s: no of pinmux entries= %d\n", __func__, len);
339 for (i = 0; i < len; i++) {
340 struct gpio_desc desc;
342 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
343 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
344 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
345 rv = uclass_get_device_by_seq(UCLASS_GPIO,
350 desc.offset = gpio_dsc.pin;
351 rv = stm32_gpio_config(&desc, &gpio_ctl);
352 debug("%s: rv = %d\n\n", __func__, rv);
361 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
362 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
364 return stm32_pinctrl_config(dev_of_offset(config));
366 #else /* PINCTRL_FULL */
367 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
368 struct udevice *periph)
370 const void *fdt = gd->fdt_blob;
376 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
380 debug("%s: periph->name = %s\n", __func__, periph->name);
382 size /= sizeof(*list);
383 for (i = 0; i < size; i++) {
384 phandle = fdt32_to_cpu(*list++);
386 config_node = fdt_node_offset_by_phandle(fdt, phandle);
387 if (config_node < 0) {
388 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
392 ret = stm32_pinctrl_config(config_node);
399 #endif /* PINCTRL_FULL */
401 static struct pinctrl_ops stm32_pinctrl_ops = {
402 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
403 .set_state = stm32_pinctrl_set_state,
404 #else /* PINCTRL_FULL */
405 .set_state_simple = stm32_pinctrl_set_state_simple,
406 #endif /* PINCTRL_FULL */
407 #ifndef CONFIG_SPL_BUILD
408 .get_pin_name = stm32_pinctrl_get_pin_name,
409 .get_pins_count = stm32_pinctrl_get_pins_count,
410 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
414 static const struct udevice_id stm32_pinctrl_ids[] = {
415 { .compatible = "st,stm32f429-pinctrl" },
416 { .compatible = "st,stm32f469-pinctrl" },
417 { .compatible = "st,stm32f746-pinctrl" },
418 { .compatible = "st,stm32h743-pinctrl" },
419 { .compatible = "st,stm32mp157-pinctrl" },
420 { .compatible = "st,stm32mp157-z-pinctrl" },
424 U_BOOT_DRIVER(pinctrl_stm32) = {
425 .name = "pinctrl_stm32",
426 .id = UCLASS_PINCTRL,
427 .of_match = stm32_pinctrl_ids,
428 .ops = &stm32_pinctrl_ops,
429 .bind = dm_scan_fdt_dev,
430 .probe = stm32_pinctrl_probe,
431 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),