3 #include <hwspinlock.h>
4 #include <asm/arch/gpio.h>
8 #include <dm/pinctrl.h>
11 DECLARE_GLOBAL_DATA_PTR;
13 #define MAX_PINS_ONE_IP 70
14 #define MODE_BITS_MASK 3
20 struct stm32_pinctrl_priv {
21 struct hwspinlock hws;
23 struct list_head gpio_dev;
26 struct stm32_gpio_bank {
27 struct udevice *gpio_dev;
28 struct list_head list;
31 #ifndef CONFIG_SPL_BUILD
33 static char pin_name[PINNAME_SIZE];
34 #define PINMUX_MODE_COUNT 5
35 static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
43 static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
45 struct stm32_gpio_priv *priv = dev_get_priv(dev);
46 struct stm32_gpio_regs *regs = priv->regs;
48 u32 alt_shift = (offset % 8) * 4;
49 u32 alt_index = offset / 8;
51 af = (readl(®s->afr[alt_index]) &
52 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
57 static int stm32_populate_gpio_dev_list(struct udevice *dev)
59 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
60 struct udevice *gpio_dev;
61 struct udevice *child;
62 struct stm32_gpio_bank *gpio_bank;
66 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
67 * a list with all gpio device reference which belongs to the
68 * current pin-controller. This list is used to find pin_name and
71 list_for_each_entry(child, &dev->child_head, sibling_node) {
72 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
77 gpio_bank = malloc(sizeof(*gpio_bank));
79 dev_err(dev, "Not enough memory\n");
83 gpio_bank->gpio_dev = gpio_dev;
84 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
90 static int stm32_pinctrl_get_pins_count(struct udevice *dev)
92 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
93 struct gpio_dev_priv *uc_priv;
94 struct stm32_gpio_bank *gpio_bank;
97 * if get_pins_count has already been executed once on this
98 * pin-controller, no need to run it again
100 if (priv->pinctrl_ngpios)
101 return priv->pinctrl_ngpios;
103 if (list_empty(&priv->gpio_dev))
104 stm32_populate_gpio_dev_list(dev);
106 * walk through all banks to retrieve the pin-controller
109 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
110 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
112 priv->pinctrl_ngpios += uc_priv->gpio_count;
115 return priv->pinctrl_ngpios;
118 static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
119 unsigned int selector,
122 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
123 struct stm32_gpio_bank *gpio_bank;
124 struct gpio_dev_priv *uc_priv;
127 if (list_empty(&priv->gpio_dev))
128 stm32_populate_gpio_dev_list(dev);
130 /* look up for the bank which owns the requested pin */
131 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
132 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
134 if (selector < (pin_count + uc_priv->gpio_count)) {
136 * we found the bank, convert pin selector to
139 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
140 selector - pin_count);
141 if (IS_ERR_VALUE(*idx))
144 return gpio_bank->gpio_dev;
146 pin_count += uc_priv->gpio_count;
152 static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
153 unsigned int selector)
155 struct gpio_dev_priv *uc_priv;
156 struct udevice *gpio_dev;
157 unsigned int gpio_idx;
159 /* look up for the bank which owns the requested pin */
160 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
162 snprintf(pin_name, PINNAME_SIZE, "Error");
164 uc_priv = dev_get_uclass_priv(gpio_dev);
166 snprintf(pin_name, PINNAME_SIZE, "%s%d",
174 static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
175 unsigned int selector,
179 struct udevice *gpio_dev;
183 unsigned int gpio_idx;
185 /* look up for the bank which owns the requested pin */
186 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
191 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
193 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
194 selector, gpio_idx, mode);
199 /* should never happen */
202 snprintf(buf, size, "%s", pinmux_mode[mode]);
205 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
206 snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
210 snprintf(buf, size, "%s %s",
211 pinmux_mode[mode], label ? label : "");
220 static int stm32_pinctrl_probe(struct udevice *dev)
222 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
225 INIT_LIST_HEAD(&priv->gpio_dev);
227 /* hwspinlock property is optional, just log the error */
228 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
230 debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
236 static int stm32_gpio_config(struct gpio_desc *desc,
237 const struct stm32_gpio_ctl *ctl)
239 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
240 struct stm32_gpio_regs *regs = priv->regs;
241 struct stm32_pinctrl_priv *ctrl_priv;
245 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
246 ctl->pupd > 2 || ctl->speed > 3)
249 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
250 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
252 dev_err(desc->dev, "HWSpinlock timeout\n");
256 index = (desc->offset & 0x07) * 4;
257 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index,
260 index = desc->offset * 2;
261 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index,
263 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index,
264 ctl->speed << index);
265 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index);
267 index = desc->offset;
268 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index);
270 hwspinlock_unlock(&ctrl_priv->hws);
275 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
277 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
278 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
279 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
285 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
292 gpio_ctl->mode = STM32_GPIO_MODE_IN;
295 gpio_ctl->mode = STM32_GPIO_MODE_AF;
296 gpio_ctl->af = gpio_fn - 1;
299 gpio_ctl->mode = STM32_GPIO_MODE_AN;
302 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
306 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
308 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
309 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
311 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
313 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
314 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
315 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
316 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
318 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
320 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
321 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
327 static int stm32_pinctrl_config(int offset)
329 u32 pin_mux[MAX_PINS_ONE_IP];
333 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
334 * usart1) of pin controller phandle "pinctrl-0"
336 fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
337 struct stm32_gpio_dsc gpio_dsc;
338 struct stm32_gpio_ctl gpio_ctl;
341 len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
343 ARRAY_SIZE(pin_mux));
344 debug("%s: no of pinmux entries= %d\n", __func__, len);
347 for (i = 0; i < len; i++) {
348 struct gpio_desc desc;
350 debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
351 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
352 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
353 rv = uclass_get_device_by_seq(UCLASS_GPIO,
358 desc.offset = gpio_dsc.pin;
359 rv = stm32_gpio_config(&desc, &gpio_ctl);
360 debug("%s: rv = %d\n\n", __func__, rv);
369 static int stm32_pinctrl_bind(struct udevice *dev)
375 dev_for_each_subnode(node, dev) {
376 debug("%s: bind %s\n", __func__, ofnode_get_name(node));
378 ofnode_get_property(node, "gpio-controller", &ret);
381 /* Get the name of each gpio node */
382 name = ofnode_get_name(node);
386 /* Bind each gpio node */
387 ret = device_bind_driver_to_node(dev, "gpio_stm32",
392 debug("%s: bind %s\n", __func__, name);
398 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
399 static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
401 return stm32_pinctrl_config(dev_of_offset(config));
403 #else /* PINCTRL_FULL */
404 static int stm32_pinctrl_set_state_simple(struct udevice *dev,
405 struct udevice *periph)
407 const void *fdt = gd->fdt_blob;
413 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
417 debug("%s: periph->name = %s\n", __func__, periph->name);
419 size /= sizeof(*list);
420 for (i = 0; i < size; i++) {
421 phandle = fdt32_to_cpu(*list++);
423 config_node = fdt_node_offset_by_phandle(fdt, phandle);
424 if (config_node < 0) {
425 pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
429 ret = stm32_pinctrl_config(config_node);
436 #endif /* PINCTRL_FULL */
438 static struct pinctrl_ops stm32_pinctrl_ops = {
439 #if CONFIG_IS_ENABLED(PINCTRL_FULL)
440 .set_state = stm32_pinctrl_set_state,
441 #else /* PINCTRL_FULL */
442 .set_state_simple = stm32_pinctrl_set_state_simple,
443 #endif /* PINCTRL_FULL */
444 #ifndef CONFIG_SPL_BUILD
445 .get_pin_name = stm32_pinctrl_get_pin_name,
446 .get_pins_count = stm32_pinctrl_get_pins_count,
447 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
451 static const struct udevice_id stm32_pinctrl_ids[] = {
452 { .compatible = "st,stm32f429-pinctrl" },
453 { .compatible = "st,stm32f469-pinctrl" },
454 { .compatible = "st,stm32f746-pinctrl" },
455 { .compatible = "st,stm32f769-pinctrl" },
456 { .compatible = "st,stm32h743-pinctrl" },
457 { .compatible = "st,stm32mp157-pinctrl" },
458 { .compatible = "st,stm32mp157-z-pinctrl" },
462 U_BOOT_DRIVER(pinctrl_stm32) = {
463 .name = "pinctrl_stm32",
464 .id = UCLASS_PINCTRL,
465 .of_match = stm32_pinctrl_ids,
466 .ops = &stm32_pinctrl_ops,
467 .bind = stm32_pinctrl_bind,
468 .probe = stm32_pinctrl_probe,
469 .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),