drivers/pinctrl/pinctrl-single.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/pinctrl.h>
   9 #include <linux/libfdt.h>
  10 #include <asm/io.h>
  11
  12 DECLARE_GLOBAL_DATA_PTR;
  13
  14 struct single_pdata {
  15         fdt_addr_t base;        /* first configuration register */
  16         int offset;             /* index of last configuration register */
  17         u32 mask;               /* configuration-value mask bits */
  18         int width;              /* configuration register bit width */
  19 };
  20
  21 struct single_fdt_pin_cfg {
  22         fdt32_t reg;            /* configuration register offset */
  23         fdt32_t val;            /* configuration register value */
  24 };
  25
  26 /**
  27  * single_configure_pins() - Configure pins based on FDT data
  28  *
  29  * @dev: Pointer to single pin configuration device which is the parent of
  30  *       the pins node holding the pin configuration data.
  31  * @pins: Pointer to the first element of an array of register/value pairs
  32  *        of type 'struct single_fdt_pin_cfg'. Each such pair describes the
  33  *        the pin to be configured and the value to be used for configuration.
  34  *        This pointer points to a 'pinctrl-single,pins' property in the
  35  *        device-tree.
  36  * @size: Size of the 'pins' array in bytes.
  37  *        The number of register/value pairs in the 'pins' array therefore
  38  *        equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
  39  */
  40 static int single_configure_pins(struct udevice *dev,
  41                                  const struct single_fdt_pin_cfg *pins,
  42                                  int size)
  43 {
  44         struct single_pdata *pdata = dev->platdata;
  45         int count = size / sizeof(struct single_fdt_pin_cfg);
  46         phys_addr_t n, reg;
  47         u32 val;
  48
  49         for (n = 0; n < count; n++, pins++) {
  50                 reg = fdt32_to_cpu(pins->reg);
  51                 if ((reg < 0) || (reg > pdata->offset)) {
  52                         dev_dbg(dev, "  invalid register offset 0x%pa\n", &reg);
  53                         continue;
  54                 }
  55                 reg += pdata->base;
  56                 val = fdt32_to_cpu(pins->val) & pdata->mask;
  57                 switch (pdata->width) {
  58                 case 16:
  59                         writew((readw(reg) & ~pdata->mask) | val, reg);
  60                         break;
  61                 case 32:
  62                         writel((readl(reg) & ~pdata->mask) | val, reg);
  63                         break;
  64                 default:
  65                         dev_warn(dev, "unsupported register width %i\n",
  66                                  pdata->width);
  67                         continue;
  68                 }
  69                 dev_dbg(dev, "  reg/val 0x%pa/0x%08x\n", &reg, val);
  70         }
  71         return 0;
  72 }
  73
  74 static int single_set_state(struct udevice *dev,
  75                             struct udevice *config)
  76 {
  77         const void *fdt = gd->fdt_blob;
  78         const struct single_fdt_pin_cfg *prop;
  79         int len;
  80
  81         prop = fdt_getprop(fdt, dev_of_offset(config), "pinctrl-single,pins",
  82                            &len);
  83         if (prop) {
  84                 dev_dbg(dev, "configuring pins for %s\n", config->name);
  85                 if (len % sizeof(struct single_fdt_pin_cfg)) {
  86                         dev_dbg(dev, "  invalid pin configuration in fdt\n");
  87                         return -FDT_ERR_BADSTRUCTURE;
  88                 }
  89                 single_configure_pins(dev, prop, len);
  90                 len = 0;
  91         }
  92
  93         return len;
  94 }
  95
  96 static int single_ofdata_to_platdata(struct udevice *dev)
  97 {
  98         fdt_addr_t addr;
  99         u32 of_reg[2];
 100         int res;
 101         struct single_pdata *pdata = dev->platdata;
 102
 103         pdata->width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 104                                       "pinctrl-single,register-width", 0);
 105
 106         res = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
 107                                    "reg", of_reg, 2);
 108         if (res)
 109                 return res;
 110         pdata->offset = of_reg[1] - pdata->width / 8;
 111
 112         addr = devfdt_get_addr(dev);
 113         if (addr == FDT_ADDR_T_NONE) {
 114                 dev_dbg(dev, "no valid base register address\n");
 115                 return -EINVAL;
 116         }
 117         pdata->base = addr;
 118
 119         pdata->mask = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 120                                      "pinctrl-single,function-mask",
 121                                      0xffffffff);
 122         return 0;
 123 }
 124
 125 const struct pinctrl_ops single_pinctrl_ops = {
 126         .set_state = single_set_state,
 127 };
 128
 129 static const struct udevice_id single_pinctrl_match[] = {
 130         { .compatible = "pinctrl-single" },
 131         { /* sentinel */ }
 132 };
 133
 134 U_BOOT_DRIVER(single_pinctrl) = {
 135         .name = "single-pinctrl",
 136         .id = UCLASS_PINCTRL,
 137         .of_match = single_pinctrl_match,
 138         .ops = &single_pinctrl_ops,
 139         .platdata_auto_alloc_size = sizeof(struct single_pdata),
 140         .ofdata_to_platdata = single_ofdata_to_platdata,
 141 };