drivers/pinctrl/pinctrl-rza2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
   4  *
   5  * Copyright (C) 2018 Chris Brandt
   6  */
   7
   8 /*
   9  * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
  10  * family.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/gpio.h>
  15 #include <linux/module.h>
  16 #include <linux/of_device.h>
  17 #include <linux/pinctrl/pinmux.h>
  18
  19 #include "core.h"
  20 #include "pinmux.h"
  21
  22 #define DRIVER_NAME             "pinctrl-rza2"
  23
  24 #define RZA2_PINS_PER_PORT      8
  25 #define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
  26 #define RZA2_PIN_ID_TO_PIN(id)  ((id) % RZA2_PINS_PER_PORT)
  27
  28 /*
  29  * Use 16 lower bits [15:0] for pin identifier
  30  * Use 16 higher bits [31:16] for pin mux function
  31  */
  32 #define MUX_PIN_ID_MASK         GENMASK(15, 0)
  33 #define MUX_FUNC_MASK           GENMASK(31, 16)
  34 #define MUX_FUNC_OFFS           16
  35 #define MUX_FUNC(pinconf)       ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
  36
  37 static const char port_names[] = "0123456789ABCDEFGHJKLM";
  38
  39 struct rza2_pinctrl_priv {
  40         struct device *dev;
  41         void __iomem *base;
  42
  43         struct pinctrl_pin_desc *pins;
  44         struct pinctrl_desc desc;
  45         struct pinctrl_dev *pctl;
  46         struct pinctrl_gpio_range gpio_range;
  47         int npins;
  48 };
  49
  50 #define RZA2_PDR(port)          (0x0000 + (port) * 2)   /* Direction 16-bit */
  51 #define RZA2_PODR(port)         (0x0040 + (port))       /* Output Data 8-bit */
  52 #define RZA2_PIDR(port)         (0x0060 + (port))       /* Input Data 8-bit */
  53 #define RZA2_PMR(port)          (0x0080 + (port))       /* Mode 8-bit */
  54 #define RZA2_DSCR(port)         (0x0140 + (port) * 2)   /* Drive 16-bit */
  55 #define RZA2_PFS(port, pin)     (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
  56
  57 #define RZA2_PWPR               0x02ff  /* Write Protect 8-bit */
  58 #define RZA2_PFENET             0x0820  /* Ethernet Pins 8-bit */
  59 #define RZA2_PPOC               0x0900  /* Dedicated Pins 32-bit */
  60 #define RZA2_PHMOMO             0x0980  /* Peripheral Pins 32-bit */
  61 #define RZA2_PCKIO              0x09d0  /* CKIO Drive 8-bit */
  62
  63 #define RZA2_PDR_INPUT          0x02
  64 #define RZA2_PDR_OUTPUT         0x03
  65 #define RZA2_PDR_MASK           0x03
  66
  67 #define PWPR_B0WI               BIT(7)  /* Bit Write Disable */
  68 #define PWPR_PFSWE              BIT(6)  /* PFS Register Write Enable */
  69 #define PFS_ISEL                BIT(6)  /* Interrupt Select */
  70
  71 static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
  72                                   u8 func)
  73 {
  74         u16 mask16;
  75         u16 reg16;
  76         u8 reg8;
  77
  78         /* Set pin to 'Non-use (Hi-z input protection)'  */
  79         reg16 = readw(pfc_base + RZA2_PDR(port));
  80         mask16 = RZA2_PDR_MASK << (pin * 2);
  81         reg16 &= ~mask16;
  82         writew(reg16, pfc_base + RZA2_PDR(port));
  83
  84         /* Temporarily switch to GPIO */
  85         reg8 = readb(pfc_base + RZA2_PMR(port));
  86         reg8 &= ~BIT(pin);
  87         writeb(reg8, pfc_base + RZA2_PMR(port));
  88
  89         /* PFS Register Write Protect : OFF */
  90         writeb(0x00, pfc_base + RZA2_PWPR);             /* B0WI=0, PFSWE=0 */
  91         writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR);       /* B0WI=0, PFSWE=1 */
  92
  93         /* Set Pin function (interrupt disabled, ISEL=0) */
  94         writeb(func, pfc_base + RZA2_PFS(port, pin));
  95
  96         /* PFS Register Write Protect : ON */
  97         writeb(0x00, pfc_base + RZA2_PWPR);     /* B0WI=0, PFSWE=0 */
  98         writeb(0x80, pfc_base + RZA2_PWPR);     /* B0WI=1, PFSWE=0 */
  99
 100         /* Port Mode  : Peripheral module pin functions */
 101         reg8 = readb(pfc_base + RZA2_PMR(port));
 102         reg8 |= BIT(pin);
 103         writeb(reg8, pfc_base + RZA2_PMR(port));
 104 }
 105
 106 static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
 107                              u8 dir)
 108 {
 109         u8 port = RZA2_PIN_ID_TO_PORT(offset);
 110         u8 pin = RZA2_PIN_ID_TO_PIN(offset);
 111         u16 mask16;
 112         u16 reg16;
 113
 114         reg16 = readw(pfc_base + RZA2_PDR(port));
 115         mask16 = RZA2_PDR_MASK << (pin * 2);
 116         reg16 &= ~mask16;
 117
 118         if (dir == GPIOF_DIR_IN)
 119                 reg16 |= RZA2_PDR_INPUT << (pin * 2);   /* pin as input */
 120         else
 121                 reg16 |= RZA2_PDR_OUTPUT << (pin * 2);  /* pin as output */
 122
 123         writew(reg16, pfc_base + RZA2_PDR(port));
 124 }
 125
 126 static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
 127 {
 128         struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
 129         u8 port = RZA2_PIN_ID_TO_PORT(offset);
 130         u8 pin = RZA2_PIN_ID_TO_PIN(offset);
 131         u16 reg16;
 132
 133         reg16 = readw(priv->base + RZA2_PDR(port));
 134         reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
 135
 136         if (reg16 == RZA2_PDR_OUTPUT)
 137                 return GPIOF_DIR_OUT;
 138
 139         if (reg16 == RZA2_PDR_INPUT)
 140                 return GPIOF_DIR_IN;
 141
 142         /*
 143          * This GPIO controller has a default Hi-Z state that is not input or
 144          * output, so force the pin to input now.
 145          */
 146         rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
 147
 148         return GPIOF_DIR_IN;
 149 }
 150
 151 static int rza2_chip_direction_input(struct gpio_chip *chip,
 152                                      unsigned int offset)
 153 {
 154         struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
 155
 156         rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
 157
 158         return 0;
 159 }
 160
 161 static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
 162 {
 163         struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
 164         u8 port = RZA2_PIN_ID_TO_PORT(offset);
 165         u8 pin = RZA2_PIN_ID_TO_PIN(offset);
 166
 167         return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
 168 }
 169
 170 static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
 171                           int value)
 172 {
 173         struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
 174         u8 port = RZA2_PIN_ID_TO_PORT(offset);
 175         u8 pin = RZA2_PIN_ID_TO_PIN(offset);
 176         u8 new_value;
 177
 178         new_value = readb(priv->base + RZA2_PODR(port));
 179
 180         if (value)
 181                 new_value |= BIT(pin);
 182         else
 183                 new_value &= ~BIT(pin);
 184
 185         writeb(new_value, priv->base + RZA2_PODR(port));
 186 }
 187
 188 static int rza2_chip_direction_output(struct gpio_chip *chip,
 189                                       unsigned int offset, int val)
 190 {
 191         struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
 192
 193         rza2_chip_set(chip, offset, val);
 194         rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_OUT);
 195
 196         return 0;
 197 }
 198
 199 static const char * const rza2_gpio_names[] = {
 200         "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
 201         "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
 202         "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
 203         "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
 204         "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
 205         "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
 206         "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
 207         "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
 208         "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
 209         "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
 210         "PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
 211         "PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
 212         "PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
 213         "PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
 214         "PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
 215         "PF_0", "PF_1", "PF_2", "PF_3", "P0_4", "PF_5", "PF_6", "PF_7",
 216         "PG_0", "PG_1", "PG_2", "P0_3", "PG_4", "PG_5", "PG_6", "PG_7",
 217         "PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
 218         /* port I does not exist */
 219         "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
 220         "PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
 221         "PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
 222         "PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
 223 };
 224
 225 static struct gpio_chip chip = {
 226         .names = rza2_gpio_names,
 227         .base = -1,
 228         .get_direction = rza2_chip_get_direction,
 229         .direction_input = rza2_chip_direction_input,
 230         .direction_output = rza2_chip_direction_output,
 231         .get = rza2_chip_get,
 232         .set = rza2_chip_set,
 233 };
 234
 235 static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
 236 {
 237         struct device_node *np = priv->dev->of_node;
 238         struct of_phandle_args of_args;
 239         int ret;
 240
 241         chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
 242         chip.of_node = np;
 243         chip.parent = priv->dev;
 244         chip.ngpio = priv->npins;
 245
 246         ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
 247                                                &of_args);
 248         if (ret) {
 249                 dev_err(priv->dev, "Unable to parse gpio-ranges\n");
 250                 return ret;
 251         }
 252
 253         if ((of_args.args[0] != 0) ||
 254             (of_args.args[1] != 0) ||
 255             (of_args.args[2] != priv->npins)) {
 256                 dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
 257                 return -EINVAL;
 258         }
 259         priv->gpio_range.id = 0;
 260         priv->gpio_range.pin_base = priv->gpio_range.base = 0;
 261         priv->gpio_range.npins = priv->npins;
 262         priv->gpio_range.name = chip.label;
 263         priv->gpio_range.gc = &chip;
 264
 265         /* Register our gpio chip with gpiolib */
 266         ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
 267         if (ret)
 268                 return ret;
 269
 270         /* Register pin range with pinctrl core */
 271         pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
 272
 273         dev_dbg(priv->dev, "Registered gpio controller\n");
 274
 275         return 0;
 276 }
 277
 278 static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
 279 {
 280         struct pinctrl_pin_desc *pins;
 281         unsigned int i;
 282         int ret;
 283
 284         pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
 285         if (!pins)
 286                 return -ENOMEM;
 287
 288         priv->pins = pins;
 289         priv->desc.pins = pins;
 290         priv->desc.npins = priv->npins;
 291
 292         for (i = 0; i < priv->npins; i++) {
 293                 pins[i].number = i;
 294                 pins[i].name = rza2_gpio_names[i];
 295         }
 296
 297         ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
 298                                              &priv->pctl);
 299         if (ret) {
 300                 dev_err(priv->dev, "pinctrl registration failed\n");
 301                 return ret;
 302         }
 303
 304         ret = pinctrl_enable(priv->pctl);
 305         if (ret) {
 306                 dev_err(priv->dev, "pinctrl enable failed\n");
 307                 return ret;
 308         }
 309
 310         ret = rza2_gpio_register(priv);
 311         if (ret) {
 312                 dev_err(priv->dev, "GPIO registration failed\n");
 313                 return ret;
 314         }
 315
 316         return 0;
 317 }
 318
 319 /*
 320  * For each DT node, create a single pin mapping. That pin mapping will only
 321  * contain a single group of pins, and that group of pins will only have a
 322  * single function that can be selected.
 323  */
 324 static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
 325                                struct device_node *np,
 326                                struct pinctrl_map **map,
 327                                unsigned int *num_maps)
 328 {
 329         struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 330         unsigned int *pins, *psel_val;
 331         int i, ret, npins, gsel, fsel;
 332         struct property *of_pins;
 333         const char **pin_fn;
 334
 335         /* Find out how many pins to map */
 336         of_pins = of_find_property(np, "pinmux", NULL);
 337         if (!of_pins) {
 338                 dev_info(priv->dev, "Missing pinmux property\n");
 339                 return -ENOENT;
 340         }
 341         npins = of_pins->length / sizeof(u32);
 342
 343         pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
 344         psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
 345                                 GFP_KERNEL);
 346         pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
 347         if (!pins || !psel_val || !pin_fn)
 348                 return -ENOMEM;
 349
 350         /* Collect pin locations and mux settings from DT properties */
 351         for (i = 0; i < npins; ++i) {
 352                 u32 value;
 353
 354                 ret = of_property_read_u32_index(np, "pinmux", i, &value);
 355                 if (ret)
 356                         return ret;
 357                 pins[i] = value & MUX_PIN_ID_MASK;
 358                 psel_val[i] = MUX_FUNC(value);
 359         }
 360
 361         /* Register a single pin group listing all the pins we read from DT */
 362         gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
 363         if (gsel < 0)
 364                 return gsel;
 365
 366         /*
 367          * Register a single group function where the 'data' is an array PSEL
 368          * register values read from DT.
 369          */
 370         pin_fn[0] = np->name;
 371         fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
 372                                            psel_val);
 373         if (fsel < 0) {
 374                 ret = fsel;
 375                 goto remove_group;
 376         }
 377
 378         dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
 379
 380         /* Create map where to retrieve function and mux settings from */
 381         *num_maps = 0;
 382         *map = kzalloc(sizeof(**map), GFP_KERNEL);
 383         if (!*map) {
 384                 ret = -ENOMEM;
 385                 goto remove_function;
 386         }
 387
 388         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
 389         (*map)->data.mux.group = np->name;
 390         (*map)->data.mux.function = np->name;
 391         *num_maps = 1;
 392
 393         return 0;
 394
 395 remove_function:
 396         pinmux_generic_remove_function(pctldev, fsel);
 397
 398 remove_group:
 399         pinctrl_generic_remove_group(pctldev, gsel);
 400
 401         dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
 402
 403         return ret;
 404 }
 405
 406 static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
 407                              struct pinctrl_map *map, unsigned int num_maps)
 408 {
 409         kfree(map);
 410 }
 411
 412 static const struct pinctrl_ops rza2_pinctrl_ops = {
 413         .get_groups_count       = pinctrl_generic_get_group_count,
 414         .get_group_name         = pinctrl_generic_get_group_name,
 415         .get_group_pins         = pinctrl_generic_get_group_pins,
 416         .dt_node_to_map         = rza2_dt_node_to_map,
 417         .dt_free_map            = rza2_dt_free_map,
 418 };
 419
 420 static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
 421                         unsigned int group)
 422 {
 423         struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 424         struct function_desc *func;
 425         unsigned int i, *psel_val;
 426         struct group_desc *grp;
 427
 428         grp = pinctrl_generic_get_group(pctldev, group);
 429         if (!grp)
 430                 return -EINVAL;
 431
 432         func = pinmux_generic_get_function(pctldev, selector);
 433         if (!func)
 434                 return -EINVAL;
 435
 436         psel_val = func->data;
 437
 438         for (i = 0; i < grp->num_pins; ++i) {
 439                 dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
 440                         port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
 441                         RZA2_PIN_ID_TO_PIN(grp->pins[i]),
 442                         psel_val[i]);
 443                 rza2_set_pin_function(
 444                         priv->base,
 445                         RZA2_PIN_ID_TO_PORT(grp->pins[i]),
 446                         RZA2_PIN_ID_TO_PIN(grp->pins[i]),
 447                         psel_val[i]);
 448         }
 449
 450         return 0;
 451 }
 452
 453 static const struct pinmux_ops rza2_pinmux_ops = {
 454         .get_functions_count    = pinmux_generic_get_function_count,
 455         .get_function_name      = pinmux_generic_get_function_name,
 456         .get_function_groups    = pinmux_generic_get_function_groups,
 457         .set_mux                = rza2_set_mux,
 458         .strict                 = true,
 459 };
 460
 461 static int rza2_pinctrl_probe(struct platform_device *pdev)
 462 {
 463         struct rza2_pinctrl_priv *priv;
 464         struct resource *res;
 465         int ret;
 466
 467         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 468         if (!priv)
 469                 return -ENOMEM;
 470
 471         priv->dev = &pdev->dev;
 472
 473         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 474         priv->base = devm_ioremap_resource(&pdev->dev, res);
 475         if (IS_ERR(priv->base))
 476                 return PTR_ERR(priv->base);
 477
 478         platform_set_drvdata(pdev, priv);
 479
 480         priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
 481                       RZA2_PINS_PER_PORT;
 482
 483         priv->desc.name         = DRIVER_NAME;
 484         priv->desc.pctlops      = &rza2_pinctrl_ops;
 485         priv->desc.pmxops       = &rza2_pinmux_ops;
 486         priv->desc.owner        = THIS_MODULE;
 487
 488         ret = rza2_pinctrl_register(priv);
 489         if (ret)
 490                 return ret;
 491
 492         dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
 493                  port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
 494
 495         return 0;
 496 }
 497
 498 static const struct of_device_id rza2_pinctrl_of_match[] = {
 499         { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
 500         { /* sentinel */ }
 501 };
 502
 503 static struct platform_driver rza2_pinctrl_driver = {
 504         .driver = {
 505                 .name = DRIVER_NAME,
 506                 .of_match_table = rza2_pinctrl_of_match,
 507         },
 508         .probe = rza2_pinctrl_probe,
 509 };
 510
 511 static int __init rza2_pinctrl_init(void)
 512 {
 513         return platform_driver_register(&rza2_pinctrl_driver);
 514 }
 515 core_initcall(rza2_pinctrl_init);
 516
 517 MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
 518 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
 519 MODULE_LICENSE("GPL v2");