drivers/pinctrl/pinctrl-oxnas.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Oxford Semiconductor OXNAS SoC Family pinctrl driver
   4  *
   5  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
   6  *
   7  * Based on pinctrl-pic32.c
   8  * Joshua Henderson, <joshua.henderson@microchip.com>
   9  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
  10  */
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/irq.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/pinctrl/pinconf.h>
  18 #include <linux/pinctrl/pinconf-generic.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23 #include <linux/regmap.h>
  24 #include <linux/mfd/syscon.h>
  25
  26 #include "pinctrl-utils.h"
  27
  28 #define PINS_PER_BANK           32
  29
  30 #define GPIO_BANK_START(bank)           ((bank) * PINS_PER_BANK)
  31
  32 /* OX810 Regmap Offsets */
  33 #define PINMUX_810_PRIMARY_SEL0         0x0c
  34 #define PINMUX_810_SECONDARY_SEL0       0x14
  35 #define PINMUX_810_TERTIARY_SEL0        0x8c
  36 #define PINMUX_810_PRIMARY_SEL1         0x10
  37 #define PINMUX_810_SECONDARY_SEL1       0x18
  38 #define PINMUX_810_TERTIARY_SEL1        0x90
  39 #define PINMUX_810_PULLUP_CTRL0         0xac
  40 #define PINMUX_810_PULLUP_CTRL1         0xb0
  41
  42 /* OX820 Regmap Offsets */
  43 #define PINMUX_820_BANK_OFFSET          0x100000
  44 #define PINMUX_820_SECONDARY_SEL        0x14
  45 #define PINMUX_820_TERTIARY_SEL         0x8c
  46 #define PINMUX_820_QUATERNARY_SEL       0x94
  47 #define PINMUX_820_DEBUG_SEL            0x9c
  48 #define PINMUX_820_ALTERNATIVE_SEL      0xa4
  49 #define PINMUX_820_PULLUP_CTRL          0xac
  50
  51 /* GPIO Registers */
  52 #define INPUT_VALUE     0x00
  53 #define OUTPUT_EN       0x04
  54 #define IRQ_PENDING     0x0c
  55 #define OUTPUT_SET      0x14
  56 #define OUTPUT_CLEAR    0x18
  57 #define OUTPUT_EN_SET   0x1c
  58 #define OUTPUT_EN_CLEAR 0x20
  59 #define RE_IRQ_ENABLE   0x28
  60 #define FE_IRQ_ENABLE   0x2c
  61
  62 struct oxnas_function {
  63         const char *name;
  64         const char * const *groups;
  65         unsigned int ngroups;
  66 };
  67
  68 struct oxnas_pin_group {
  69         const char *name;
  70         unsigned int pin;
  71         unsigned int bank;
  72         struct oxnas_desc_function *functions;
  73 };
  74
  75 struct oxnas_desc_function {
  76         const char *name;
  77         unsigned int fct;
  78 };
  79
  80 struct oxnas_gpio_bank {
  81         void __iomem *reg_base;
  82         struct gpio_chip gpio_chip;
  83         struct irq_chip irq_chip;
  84         unsigned int id;
  85 };
  86
  87 struct oxnas_pinctrl {
  88         struct regmap *regmap;
  89         struct device *dev;
  90         struct pinctrl_dev *pctldev;
  91         const struct oxnas_function *functions;
  92         unsigned int nfunctions;
  93         const struct oxnas_pin_group *groups;
  94         unsigned int ngroups;
  95         struct oxnas_gpio_bank *gpio_banks;
  96         unsigned int nbanks;
  97 };
  98
  99 struct oxnas_pinctrl_data {
 100         struct pinctrl_desc *desc;
 101         struct oxnas_pinctrl *pctl;
 102 };
 103
 104 static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = {
 105         PINCTRL_PIN(0, "gpio0"),
 106         PINCTRL_PIN(1, "gpio1"),
 107         PINCTRL_PIN(2, "gpio2"),
 108         PINCTRL_PIN(3, "gpio3"),
 109         PINCTRL_PIN(4, "gpio4"),
 110         PINCTRL_PIN(5, "gpio5"),
 111         PINCTRL_PIN(6, "gpio6"),
 112         PINCTRL_PIN(7, "gpio7"),
 113         PINCTRL_PIN(8, "gpio8"),
 114         PINCTRL_PIN(9, "gpio9"),
 115         PINCTRL_PIN(10, "gpio10"),
 116         PINCTRL_PIN(11, "gpio11"),
 117         PINCTRL_PIN(12, "gpio12"),
 118         PINCTRL_PIN(13, "gpio13"),
 119         PINCTRL_PIN(14, "gpio14"),
 120         PINCTRL_PIN(15, "gpio15"),
 121         PINCTRL_PIN(16, "gpio16"),
 122         PINCTRL_PIN(17, "gpio17"),
 123         PINCTRL_PIN(18, "gpio18"),
 124         PINCTRL_PIN(19, "gpio19"),
 125         PINCTRL_PIN(20, "gpio20"),
 126         PINCTRL_PIN(21, "gpio21"),
 127         PINCTRL_PIN(22, "gpio22"),
 128         PINCTRL_PIN(23, "gpio23"),
 129         PINCTRL_PIN(24, "gpio24"),
 130         PINCTRL_PIN(25, "gpio25"),
 131         PINCTRL_PIN(26, "gpio26"),
 132         PINCTRL_PIN(27, "gpio27"),
 133         PINCTRL_PIN(28, "gpio28"),
 134         PINCTRL_PIN(29, "gpio29"),
 135         PINCTRL_PIN(30, "gpio30"),
 136         PINCTRL_PIN(31, "gpio31"),
 137         PINCTRL_PIN(32, "gpio32"),
 138         PINCTRL_PIN(33, "gpio33"),
 139         PINCTRL_PIN(34, "gpio34"),
 140 };
 141
 142 static const struct pinctrl_pin_desc oxnas_ox820_pins[] = {
 143         PINCTRL_PIN(0, "gpio0"),
 144         PINCTRL_PIN(1, "gpio1"),
 145         PINCTRL_PIN(2, "gpio2"),
 146         PINCTRL_PIN(3, "gpio3"),
 147         PINCTRL_PIN(4, "gpio4"),
 148         PINCTRL_PIN(5, "gpio5"),
 149         PINCTRL_PIN(6, "gpio6"),
 150         PINCTRL_PIN(7, "gpio7"),
 151         PINCTRL_PIN(8, "gpio8"),
 152         PINCTRL_PIN(9, "gpio9"),
 153         PINCTRL_PIN(10, "gpio10"),
 154         PINCTRL_PIN(11, "gpio11"),
 155         PINCTRL_PIN(12, "gpio12"),
 156         PINCTRL_PIN(13, "gpio13"),
 157         PINCTRL_PIN(14, "gpio14"),
 158         PINCTRL_PIN(15, "gpio15"),
 159         PINCTRL_PIN(16, "gpio16"),
 160         PINCTRL_PIN(17, "gpio17"),
 161         PINCTRL_PIN(18, "gpio18"),
 162         PINCTRL_PIN(19, "gpio19"),
 163         PINCTRL_PIN(20, "gpio20"),
 164         PINCTRL_PIN(21, "gpio21"),
 165         PINCTRL_PIN(22, "gpio22"),
 166         PINCTRL_PIN(23, "gpio23"),
 167         PINCTRL_PIN(24, "gpio24"),
 168         PINCTRL_PIN(25, "gpio25"),
 169         PINCTRL_PIN(26, "gpio26"),
 170         PINCTRL_PIN(27, "gpio27"),
 171         PINCTRL_PIN(28, "gpio28"),
 172         PINCTRL_PIN(29, "gpio29"),
 173         PINCTRL_PIN(30, "gpio30"),
 174         PINCTRL_PIN(31, "gpio31"),
 175         PINCTRL_PIN(32, "gpio32"),
 176         PINCTRL_PIN(33, "gpio33"),
 177         PINCTRL_PIN(34, "gpio34"),
 178         PINCTRL_PIN(35, "gpio35"),
 179         PINCTRL_PIN(36, "gpio36"),
 180         PINCTRL_PIN(37, "gpio37"),
 181         PINCTRL_PIN(38, "gpio38"),
 182         PINCTRL_PIN(39, "gpio39"),
 183         PINCTRL_PIN(40, "gpio40"),
 184         PINCTRL_PIN(41, "gpio41"),
 185         PINCTRL_PIN(42, "gpio42"),
 186         PINCTRL_PIN(43, "gpio43"),
 187         PINCTRL_PIN(44, "gpio44"),
 188         PINCTRL_PIN(45, "gpio45"),
 189         PINCTRL_PIN(46, "gpio46"),
 190         PINCTRL_PIN(47, "gpio47"),
 191         PINCTRL_PIN(48, "gpio48"),
 192         PINCTRL_PIN(49, "gpio49"),
 193 };
 194
 195 static const char * const oxnas_ox810se_fct0_group[] = {
 196         "gpio0",  "gpio1",  "gpio2",  "gpio3",
 197         "gpio4",  "gpio5",  "gpio6",  "gpio7",
 198         "gpio8",  "gpio9",  "gpio10", "gpio11",
 199         "gpio12", "gpio13", "gpio14", "gpio15",
 200         "gpio16", "gpio17", "gpio18", "gpio19",
 201         "gpio20", "gpio21", "gpio22", "gpio23",
 202         "gpio24", "gpio25", "gpio26", "gpio27",
 203         "gpio28", "gpio29", "gpio30", "gpio31",
 204         "gpio32", "gpio33", "gpio34"
 205 };
 206
 207 static const char * const oxnas_ox810se_fct3_group[] = {
 208         "gpio0",  "gpio1",  "gpio2",  "gpio3",
 209         "gpio4",  "gpio5",  "gpio6",  "gpio7",
 210         "gpio8",  "gpio9",
 211         "gpio20",
 212         "gpio22", "gpio23", "gpio24", "gpio25",
 213         "gpio26", "gpio27", "gpio28", "gpio29",
 214         "gpio30", "gpio31", "gpio32", "gpio33",
 215         "gpio34"
 216 };
 217
 218 static const char * const oxnas_ox820_fct0_group[] = {
 219         "gpio0",  "gpio1",  "gpio2",  "gpio3",
 220         "gpio4",  "gpio5",  "gpio6",  "gpio7",
 221         "gpio8",  "gpio9",  "gpio10", "gpio11",
 222         "gpio12", "gpio13", "gpio14", "gpio15",
 223         "gpio16", "gpio17", "gpio18", "gpio19",
 224         "gpio20", "gpio21", "gpio22", "gpio23",
 225         "gpio24", "gpio25", "gpio26", "gpio27",
 226         "gpio28", "gpio29", "gpio30", "gpio31",
 227         "gpio32", "gpio33", "gpio34", "gpio35",
 228         "gpio36", "gpio37", "gpio38", "gpio39",
 229         "gpio40", "gpio41", "gpio42", "gpio43",
 230         "gpio44", "gpio45", "gpio46", "gpio47",
 231         "gpio48", "gpio49"
 232 };
 233
 234 static const char * const oxnas_ox820_fct1_group[] = {
 235         "gpio3", "gpio4",
 236         "gpio12", "gpio13", "gpio14", "gpio15",
 237         "gpio16", "gpio17", "gpio18", "gpio19",
 238         "gpio20", "gpio21", "gpio22", "gpio23",
 239         "gpio24"
 240 };
 241
 242 static const char * const oxnas_ox820_fct4_group[] = {
 243         "gpio5", "gpio6", "gpio7", "gpio8",
 244         "gpio24", "gpio25", "gpio26", "gpio27",
 245         "gpio40", "gpio41", "gpio42", "gpio43"
 246 };
 247
 248 static const char * const oxnas_ox820_fct5_group[] = {
 249         "gpio28", "gpio29", "gpio30", "gpio31"
 250 };
 251
 252 #define FUNCTION(_name, _gr)                                    \
 253         {                                                       \
 254                 .name = #_name,                                 \
 255                 .groups = oxnas_##_gr##_group,                  \
 256                 .ngroups = ARRAY_SIZE(oxnas_##_gr##_group),     \
 257         }
 258
 259 static const struct oxnas_function oxnas_ox810se_functions[] = {
 260         FUNCTION(gpio, ox810se_fct0),
 261         FUNCTION(fct3, ox810se_fct3),
 262 };
 263
 264 static const struct oxnas_function oxnas_ox820_functions[] = {
 265         FUNCTION(gpio, ox820_fct0),
 266         FUNCTION(fct1, ox820_fct1),
 267         FUNCTION(fct4, ox820_fct4),
 268         FUNCTION(fct5, ox820_fct5),
 269 };
 270
 271 #define OXNAS_PINCTRL_GROUP(_pin, _name, ...)                           \
 272         {                                                               \
 273                 .name = #_name,                                         \
 274                 .pin = _pin,                                            \
 275                 .bank = _pin / PINS_PER_BANK,                           \
 276                 .functions = (struct oxnas_desc_function[]){            \
 277                         __VA_ARGS__, { } },                             \
 278         }
 279
 280 #define OXNAS_PINCTRL_FUNCTION(_name, _fct)             \
 281         {                                               \
 282                 .name = #_name,                         \
 283                 .fct = _fct,                            \
 284         }
 285
 286 static const struct oxnas_pin_group oxnas_ox810se_groups[] = {
 287         OXNAS_PINCTRL_GROUP(0, gpio0,
 288                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 289                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 290         OXNAS_PINCTRL_GROUP(1, gpio1,
 291                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 292                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 293         OXNAS_PINCTRL_GROUP(2, gpio2,
 294                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 295                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 296         OXNAS_PINCTRL_GROUP(3, gpio3,
 297                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 298                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 299         OXNAS_PINCTRL_GROUP(4, gpio4,
 300                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 301                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 302         OXNAS_PINCTRL_GROUP(5, gpio5,
 303                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 304                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 305         OXNAS_PINCTRL_GROUP(6, gpio6,
 306                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 307                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 308         OXNAS_PINCTRL_GROUP(7, gpio7,
 309                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 310                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 311         OXNAS_PINCTRL_GROUP(8, gpio8,
 312                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 313                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 314         OXNAS_PINCTRL_GROUP(9, gpio9,
 315                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 316                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 317         OXNAS_PINCTRL_GROUP(10, gpio10,
 318                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 319         OXNAS_PINCTRL_GROUP(11, gpio11,
 320                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 321         OXNAS_PINCTRL_GROUP(12, gpio12,
 322                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 323         OXNAS_PINCTRL_GROUP(13, gpio13,
 324                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 325         OXNAS_PINCTRL_GROUP(14, gpio14,
 326                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 327         OXNAS_PINCTRL_GROUP(15, gpio15,
 328                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 329         OXNAS_PINCTRL_GROUP(16, gpio16,
 330                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 331         OXNAS_PINCTRL_GROUP(17, gpio17,
 332                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 333         OXNAS_PINCTRL_GROUP(18, gpio18,
 334                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 335         OXNAS_PINCTRL_GROUP(19, gpio19,
 336                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 337         OXNAS_PINCTRL_GROUP(20, gpio20,
 338                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 339                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 340         OXNAS_PINCTRL_GROUP(21, gpio21,
 341                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 342         OXNAS_PINCTRL_GROUP(22, gpio22,
 343                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 344                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 345         OXNAS_PINCTRL_GROUP(23, gpio23,
 346                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 347                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 348         OXNAS_PINCTRL_GROUP(24, gpio24,
 349                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 350                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 351         OXNAS_PINCTRL_GROUP(25, gpio25,
 352                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 353                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 354         OXNAS_PINCTRL_GROUP(26, gpio26,
 355                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 356                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 357         OXNAS_PINCTRL_GROUP(27, gpio27,
 358                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 359                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 360         OXNAS_PINCTRL_GROUP(28, gpio28,
 361                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 362                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 363         OXNAS_PINCTRL_GROUP(29, gpio29,
 364                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 365                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 366         OXNAS_PINCTRL_GROUP(30, gpio30,
 367                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 368                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 369         OXNAS_PINCTRL_GROUP(31, gpio31,
 370                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 371                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 372         OXNAS_PINCTRL_GROUP(32, gpio32,
 373                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 374                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 375         OXNAS_PINCTRL_GROUP(33, gpio33,
 376                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 377                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 378         OXNAS_PINCTRL_GROUP(34, gpio34,
 379                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 380                         OXNAS_PINCTRL_FUNCTION(fct3, 3)),
 381 };
 382
 383 static const struct oxnas_pin_group oxnas_ox820_groups[] = {
 384         OXNAS_PINCTRL_GROUP(0, gpio0,
 385                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 386         OXNAS_PINCTRL_GROUP(1, gpio1,
 387                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 388         OXNAS_PINCTRL_GROUP(2, gpio2,
 389                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 390         OXNAS_PINCTRL_GROUP(3, gpio3,
 391                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 392                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 393         OXNAS_PINCTRL_GROUP(4, gpio4,
 394                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 395                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 396         OXNAS_PINCTRL_GROUP(5, gpio5,
 397                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 398                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 399         OXNAS_PINCTRL_GROUP(6, gpio6,
 400                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 401                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 402         OXNAS_PINCTRL_GROUP(7, gpio7,
 403                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 404                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 405         OXNAS_PINCTRL_GROUP(8, gpio8,
 406                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 407                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 408         OXNAS_PINCTRL_GROUP(9, gpio9,
 409                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 410         OXNAS_PINCTRL_GROUP(10, gpio10,
 411                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 412         OXNAS_PINCTRL_GROUP(11, gpio11,
 413                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 414         OXNAS_PINCTRL_GROUP(12, gpio12,
 415                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 416                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 417         OXNAS_PINCTRL_GROUP(13, gpio13,
 418                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 419                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 420         OXNAS_PINCTRL_GROUP(14, gpio14,
 421                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 422                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 423         OXNAS_PINCTRL_GROUP(15, gpio15,
 424                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 425                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 426         OXNAS_PINCTRL_GROUP(16, gpio16,
 427                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 428                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 429         OXNAS_PINCTRL_GROUP(17, gpio17,
 430                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 431                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 432         OXNAS_PINCTRL_GROUP(18, gpio18,
 433                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 434                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 435         OXNAS_PINCTRL_GROUP(19, gpio19,
 436                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 437                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 438         OXNAS_PINCTRL_GROUP(20, gpio20,
 439                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 440                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 441         OXNAS_PINCTRL_GROUP(21, gpio21,
 442                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 443                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 444         OXNAS_PINCTRL_GROUP(22, gpio22,
 445                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 446                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 447         OXNAS_PINCTRL_GROUP(23, gpio23,
 448                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 449                         OXNAS_PINCTRL_FUNCTION(fct1, 1)),
 450         OXNAS_PINCTRL_GROUP(24, gpio24,
 451                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 452                         OXNAS_PINCTRL_FUNCTION(fct1, 1),
 453                         OXNAS_PINCTRL_FUNCTION(fct4, 5)),
 454         OXNAS_PINCTRL_GROUP(25, gpio25,
 455                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 456                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 457         OXNAS_PINCTRL_GROUP(26, gpio26,
 458                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 459                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 460         OXNAS_PINCTRL_GROUP(27, gpio27,
 461                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 462                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 463         OXNAS_PINCTRL_GROUP(28, gpio28,
 464                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 465                         OXNAS_PINCTRL_FUNCTION(fct5, 5)),
 466         OXNAS_PINCTRL_GROUP(29, gpio29,
 467                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 468                         OXNAS_PINCTRL_FUNCTION(fct5, 5)),
 469         OXNAS_PINCTRL_GROUP(30, gpio30,
 470                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 471                         OXNAS_PINCTRL_FUNCTION(fct5, 5)),
 472         OXNAS_PINCTRL_GROUP(31, gpio31,
 473                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 474                         OXNAS_PINCTRL_FUNCTION(fct5, 5)),
 475         OXNAS_PINCTRL_GROUP(32, gpio32,
 476                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 477         OXNAS_PINCTRL_GROUP(33, gpio33,
 478                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 479         OXNAS_PINCTRL_GROUP(34, gpio34,
 480                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 481         OXNAS_PINCTRL_GROUP(35, gpio35,
 482                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 483         OXNAS_PINCTRL_GROUP(36, gpio36,
 484                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 485         OXNAS_PINCTRL_GROUP(37, gpio37,
 486                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 487         OXNAS_PINCTRL_GROUP(38, gpio38,
 488                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 489         OXNAS_PINCTRL_GROUP(39, gpio39,
 490                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 491         OXNAS_PINCTRL_GROUP(40, gpio40,
 492                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 493                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 494         OXNAS_PINCTRL_GROUP(41, gpio41,
 495                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 496                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 497         OXNAS_PINCTRL_GROUP(42, gpio42,
 498                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 499                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 500         OXNAS_PINCTRL_GROUP(43, gpio43,
 501                         OXNAS_PINCTRL_FUNCTION(gpio, 0),
 502                         OXNAS_PINCTRL_FUNCTION(fct4, 4)),
 503         OXNAS_PINCTRL_GROUP(44, gpio44,
 504                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 505         OXNAS_PINCTRL_GROUP(45, gpio45,
 506                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 507         OXNAS_PINCTRL_GROUP(46, gpio46,
 508                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 509         OXNAS_PINCTRL_GROUP(47, gpio47,
 510                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 511         OXNAS_PINCTRL_GROUP(48, gpio48,
 512                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 513         OXNAS_PINCTRL_GROUP(49, gpio49,
 514                         OXNAS_PINCTRL_FUNCTION(gpio, 0)),
 515 };
 516
 517 static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl,
 518                                                    unsigned int pin)
 519 {
 520         return &pctl->gpio_banks[pin / PINS_PER_BANK];
 521 }
 522
 523 static int oxnas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 524 {
 525         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 526
 527         return pctl->ngroups;
 528 }
 529
 530 static const char *oxnas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 531                                                 unsigned int group)
 532 {
 533         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 534
 535         return pctl->groups[group].name;
 536 }
 537
 538 static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 539                                         unsigned int group,
 540                                         const unsigned int **pins,
 541                                         unsigned int *num_pins)
 542 {
 543         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 544
 545         *pins = &pctl->groups[group].pin;
 546         *num_pins = 1;
 547
 548         return 0;
 549 }
 550
 551 static const struct pinctrl_ops oxnas_pinctrl_ops = {
 552         .get_groups_count = oxnas_pinctrl_get_groups_count,
 553         .get_group_name = oxnas_pinctrl_get_group_name,
 554         .get_group_pins = oxnas_pinctrl_get_group_pins,
 555         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 556         .dt_free_map = pinctrl_utils_free_map,
 557 };
 558
 559 static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
 560 {
 561         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 562
 563         return pctl->nfunctions;
 564 }
 565
 566 static const char *
 567 oxnas_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func)
 568 {
 569         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 570
 571         return pctl->functions[func].name;
 572 }
 573
 574 static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
 575                                             unsigned int func,
 576                                             const char * const **groups,
 577                                             unsigned int * const num_groups)
 578 {
 579         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 580
 581         *groups = pctl->functions[func].groups;
 582         *num_groups = pctl->functions[func].ngroups;
 583
 584         return 0;
 585 }
 586
 587 static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev,
 588                                        unsigned int func, unsigned int group)
 589 {
 590         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 591         const struct oxnas_pin_group *pg = &pctl->groups[group];
 592         const struct oxnas_function *pf = &pctl->functions[func];
 593         const char *fname = pf->name;
 594         struct oxnas_desc_function *functions = pg->functions;
 595         u32 mask = BIT(pg->pin);
 596
 597         while (functions->name) {
 598                 if (!strcmp(functions->name, fname)) {
 599                         dev_dbg(pctl->dev,
 600                                 "setting function %s bank %d pin %d fct %d mask %x\n",
 601                                 fname, pg->bank, pg->pin,
 602                                 functions->fct, mask);
 603
 604                         regmap_write_bits(pctl->regmap,
 605                                           (pg->bank ?
 606                                                 PINMUX_810_PRIMARY_SEL1 :
 607                                                 PINMUX_810_PRIMARY_SEL0),
 608                                           mask,
 609                                           (functions->fct == 1 ?
 610                                                 mask : 0));
 611                         regmap_write_bits(pctl->regmap,
 612                                           (pg->bank ?
 613                                                 PINMUX_810_SECONDARY_SEL1 :
 614                                                 PINMUX_810_SECONDARY_SEL0),
 615                                           mask,
 616                                           (functions->fct == 2 ?
 617                                                 mask : 0));
 618                         regmap_write_bits(pctl->regmap,
 619                                           (pg->bank ?
 620                                                 PINMUX_810_TERTIARY_SEL1 :
 621                                                 PINMUX_810_TERTIARY_SEL0),
 622                                           mask,
 623                                           (functions->fct == 3 ?
 624                                                 mask : 0));
 625
 626                         return 0;
 627                 }
 628
 629                 functions++;
 630         }
 631
 632         dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
 633
 634         return -EINVAL;
 635 }
 636
 637 static int oxnas_ox820_pinmux_enable(struct pinctrl_dev *pctldev,
 638                                      unsigned int func, unsigned int group)
 639 {
 640         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 641         const struct oxnas_pin_group *pg = &pctl->groups[group];
 642         const struct oxnas_function *pf = &pctl->functions[func];
 643         const char *fname = pf->name;
 644         struct oxnas_desc_function *functions = pg->functions;
 645         unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0);
 646         u32 mask = BIT(pg->pin);
 647
 648         while (functions->name) {
 649                 if (!strcmp(functions->name, fname)) {
 650                         dev_dbg(pctl->dev,
 651                                 "setting function %s bank %d pin %d fct %d mask %x\n",
 652                                 fname, pg->bank, pg->pin,
 653                                 functions->fct, mask);
 654
 655                         regmap_write_bits(pctl->regmap,
 656                                           offset + PINMUX_820_SECONDARY_SEL,
 657                                           mask,
 658                                           (functions->fct == 1 ?
 659                                                 mask : 0));
 660                         regmap_write_bits(pctl->regmap,
 661                                           offset + PINMUX_820_TERTIARY_SEL,
 662                                           mask,
 663                                           (functions->fct == 2 ?
 664                                                 mask : 0));
 665                         regmap_write_bits(pctl->regmap,
 666                                           offset + PINMUX_820_QUATERNARY_SEL,
 667                                           mask,
 668                                           (functions->fct == 3 ?
 669                                                 mask : 0));
 670                         regmap_write_bits(pctl->regmap,
 671                                           offset + PINMUX_820_DEBUG_SEL,
 672                                           mask,
 673                                           (functions->fct == 4 ?
 674                                                 mask : 0));
 675                         regmap_write_bits(pctl->regmap,
 676                                           offset + PINMUX_820_ALTERNATIVE_SEL,
 677                                           mask,
 678                                           (functions->fct == 5 ?
 679                                                 mask : 0));
 680
 681                         return 0;
 682                 }
 683
 684                 functions++;
 685         }
 686
 687         dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
 688
 689         return -EINVAL;
 690 }
 691
 692 static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev,
 693                                              struct pinctrl_gpio_range *range,
 694                                              unsigned int offset)
 695 {
 696         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 697         struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
 698         u32 mask = BIT(offset - bank->gpio_chip.base);
 699
 700         dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
 701                 offset, bank->gpio_chip.base, bank->id, mask);
 702
 703         regmap_write_bits(pctl->regmap,
 704                           (bank->id ?
 705                                 PINMUX_810_PRIMARY_SEL1 :
 706                                 PINMUX_810_PRIMARY_SEL0),
 707                           mask, 0);
 708         regmap_write_bits(pctl->regmap,
 709                           (bank->id ?
 710                                 PINMUX_810_SECONDARY_SEL1 :
 711                                 PINMUX_810_SECONDARY_SEL0),
 712                           mask, 0);
 713         regmap_write_bits(pctl->regmap,
 714                           (bank->id ?
 715                                 PINMUX_810_TERTIARY_SEL1 :
 716                                 PINMUX_810_TERTIARY_SEL0),
 717                           mask, 0);
 718
 719         return 0;
 720 }
 721
 722 static int oxnas_ox820_gpio_request_enable(struct pinctrl_dev *pctldev,
 723                                            struct pinctrl_gpio_range *range,
 724                                            unsigned int offset)
 725 {
 726         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 727         struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
 728         unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
 729         u32 mask = BIT(offset - bank->gpio_chip.base);
 730
 731         dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
 732                 offset, bank->gpio_chip.base, bank->id, mask);
 733
 734         regmap_write_bits(pctl->regmap,
 735                           bank_offset + PINMUX_820_SECONDARY_SEL,
 736                           mask, 0);
 737         regmap_write_bits(pctl->regmap,
 738                           bank_offset + PINMUX_820_TERTIARY_SEL,
 739                           mask, 0);
 740         regmap_write_bits(pctl->regmap,
 741                           bank_offset + PINMUX_820_QUATERNARY_SEL,
 742                           mask, 0);
 743         regmap_write_bits(pctl->regmap,
 744                           bank_offset + PINMUX_820_DEBUG_SEL,
 745                           mask, 0);
 746         regmap_write_bits(pctl->regmap,
 747                           bank_offset + PINMUX_820_ALTERNATIVE_SEL,
 748                           mask, 0);
 749
 750         return 0;
 751 }
 752
 753 static int oxnas_gpio_get_direction(struct gpio_chip *chip,
 754                                       unsigned int offset)
 755 {
 756         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 757         u32 mask = BIT(offset);
 758
 759         return !(readl_relaxed(bank->reg_base + OUTPUT_EN) & mask);
 760 }
 761
 762 static int oxnas_gpio_direction_input(struct gpio_chip *chip,
 763                                       unsigned int offset)
 764 {
 765         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 766         u32 mask = BIT(offset);
 767
 768         writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR);
 769
 770         return 0;
 771 }
 772
 773 static int oxnas_gpio_get(struct gpio_chip *chip, unsigned int offset)
 774 {
 775         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 776         u32 mask = BIT(offset);
 777
 778         return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0;
 779 }
 780
 781 static void oxnas_gpio_set(struct gpio_chip *chip, unsigned int offset,
 782                                int value)
 783 {
 784         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 785         u32 mask = BIT(offset);
 786
 787         if (value)
 788                 writel_relaxed(mask, bank->reg_base + OUTPUT_SET);
 789         else
 790                 writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR);
 791 }
 792
 793 static int oxnas_gpio_direction_output(struct gpio_chip *chip,
 794                                        unsigned int offset, int value)
 795 {
 796         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 797         u32 mask = BIT(offset);
 798
 799         oxnas_gpio_set(chip, offset, value);
 800         writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET);
 801
 802         return 0;
 803 }
 804
 805 static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev,
 806                                     struct pinctrl_gpio_range *range,
 807                                     unsigned int offset, bool input)
 808 {
 809         struct gpio_chip *chip = range->gc;
 810
 811         if (input)
 812                 oxnas_gpio_direction_input(chip, offset);
 813         else
 814                 oxnas_gpio_direction_output(chip, offset, 0);
 815
 816         return 0;
 817 }
 818
 819 static const struct pinmux_ops oxnas_ox810se_pinmux_ops = {
 820         .get_functions_count = oxnas_pinmux_get_functions_count,
 821         .get_function_name = oxnas_pinmux_get_function_name,
 822         .get_function_groups = oxnas_pinmux_get_function_groups,
 823         .set_mux = oxnas_ox810se_pinmux_enable,
 824         .gpio_request_enable = oxnas_ox810se_gpio_request_enable,
 825         .gpio_set_direction = oxnas_gpio_set_direction,
 826 };
 827
 828 static const struct pinmux_ops oxnas_ox820_pinmux_ops = {
 829         .get_functions_count = oxnas_pinmux_get_functions_count,
 830         .get_function_name = oxnas_pinmux_get_function_name,
 831         .get_function_groups = oxnas_pinmux_get_function_groups,
 832         .set_mux = oxnas_ox820_pinmux_enable,
 833         .gpio_request_enable = oxnas_ox820_gpio_request_enable,
 834         .gpio_set_direction = oxnas_gpio_set_direction,
 835 };
 836
 837 static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev,
 838                                      unsigned int pin, unsigned long *config)
 839 {
 840         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 841         struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
 842         unsigned int param = pinconf_to_config_param(*config);
 843         u32 mask = BIT(pin - bank->gpio_chip.base);
 844         int ret;
 845         u32 arg;
 846
 847         switch (param) {
 848         case PIN_CONFIG_BIAS_PULL_UP:
 849                 ret = regmap_read(pctl->regmap,
 850                                   (bank->id ?
 851                                         PINMUX_810_PULLUP_CTRL1 :
 852                                         PINMUX_810_PULLUP_CTRL0),
 853                                   &arg);
 854                 if (ret)
 855                         return ret;
 856
 857                 arg = !!(arg & mask);
 858                 break;
 859         default:
 860                 return -ENOTSUPP;
 861         }
 862
 863         *config = pinconf_to_config_packed(param, arg);
 864
 865         return 0;
 866 }
 867
 868 static int oxnas_ox820_pinconf_get(struct pinctrl_dev *pctldev,
 869                                    unsigned int pin, unsigned long *config)
 870 {
 871         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 872         struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
 873         unsigned int param = pinconf_to_config_param(*config);
 874         unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
 875         u32 mask = BIT(pin - bank->gpio_chip.base);
 876         int ret;
 877         u32 arg;
 878
 879         switch (param) {
 880         case PIN_CONFIG_BIAS_PULL_UP:
 881                 ret = regmap_read(pctl->regmap,
 882                                   bank_offset + PINMUX_820_PULLUP_CTRL,
 883                                   &arg);
 884                 if (ret)
 885                         return ret;
 886
 887                 arg = !!(arg & mask);
 888                 break;
 889         default:
 890                 return -ENOTSUPP;
 891         }
 892
 893         *config = pinconf_to_config_packed(param, arg);
 894
 895         return 0;
 896 }
 897
 898 static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
 899                                      unsigned int pin, unsigned long *configs,
 900                                      unsigned int num_configs)
 901 {
 902         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 903         struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
 904         unsigned int param;
 905         u32 arg;
 906         unsigned int i;
 907         u32 offset = pin - bank->gpio_chip.base;
 908         u32 mask = BIT(offset);
 909
 910         dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
 911                 pin, bank->gpio_chip.base, mask);
 912
 913         for (i = 0; i < num_configs; i++) {
 914                 param = pinconf_to_config_param(configs[i]);
 915                 arg = pinconf_to_config_argument(configs[i]);
 916
 917                 switch (param) {
 918                 case PIN_CONFIG_BIAS_PULL_UP:
 919                         dev_dbg(pctl->dev, "   pullup\n");
 920                         regmap_write_bits(pctl->regmap,
 921                                           (bank->id ?
 922                                                 PINMUX_810_PULLUP_CTRL1 :
 923                                                 PINMUX_810_PULLUP_CTRL0),
 924                                           mask, mask);
 925                         break;
 926                 default:
 927                         dev_err(pctl->dev, "Property %u not supported\n",
 928                                 param);
 929                         return -ENOTSUPP;
 930                 }
 931         }
 932
 933         return 0;
 934 }
 935
 936 static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev,
 937                                    unsigned int pin, unsigned long *configs,
 938                                    unsigned int num_configs)
 939 {
 940         struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 941         struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
 942         unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
 943         unsigned int param;
 944         u32 arg;
 945         unsigned int i;
 946         u32 offset = pin - bank->gpio_chip.base;
 947         u32 mask = BIT(offset);
 948
 949         dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
 950                 pin, bank->gpio_chip.base, mask);
 951
 952         for (i = 0; i < num_configs; i++) {
 953                 param = pinconf_to_config_param(configs[i]);
 954                 arg = pinconf_to_config_argument(configs[i]);
 955
 956                 switch (param) {
 957                 case PIN_CONFIG_BIAS_PULL_UP:
 958                         dev_dbg(pctl->dev, "   pullup\n");
 959                         regmap_write_bits(pctl->regmap,
 960                                           bank_offset + PINMUX_820_PULLUP_CTRL,
 961                                           mask, mask);
 962                         break;
 963                 default:
 964                         dev_err(pctl->dev, "Property %u not supported\n",
 965                                 param);
 966                         return -ENOTSUPP;
 967                 }
 968         }
 969
 970         return 0;
 971 }
 972
 973 static const struct pinconf_ops oxnas_ox810se_pinconf_ops = {
 974         .pin_config_get = oxnas_ox810se_pinconf_get,
 975         .pin_config_set = oxnas_ox810se_pinconf_set,
 976         .is_generic = true,
 977 };
 978
 979 static const struct pinconf_ops oxnas_ox820_pinconf_ops = {
 980         .pin_config_get = oxnas_ox820_pinconf_get,
 981         .pin_config_set = oxnas_ox820_pinconf_set,
 982         .is_generic = true,
 983 };
 984
 985 static void oxnas_gpio_irq_ack(struct irq_data *data)
 986 {
 987         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 988         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 989         u32 mask = BIT(data->hwirq);
 990
 991         writel(mask, bank->reg_base + IRQ_PENDING);
 992 }
 993
 994 static void oxnas_gpio_irq_mask(struct irq_data *data)
 995 {
 996         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 997         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
 998         unsigned int type = irqd_get_trigger_type(data);
 999         u32 mask = BIT(data->hwirq);
1000
1001         if (type & IRQ_TYPE_EDGE_RISING)
1002                 writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask,
1003                        bank->reg_base + RE_IRQ_ENABLE);
1004
1005         if (type & IRQ_TYPE_EDGE_FALLING)
1006                 writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask,
1007                        bank->reg_base + FE_IRQ_ENABLE);
1008 }
1009
1010 static void oxnas_gpio_irq_unmask(struct irq_data *data)
1011 {
1012         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1013         struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
1014         unsigned int type = irqd_get_trigger_type(data);
1015         u32 mask = BIT(data->hwirq);
1016
1017         if (type & IRQ_TYPE_EDGE_RISING)
1018                 writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask,
1019                        bank->reg_base + RE_IRQ_ENABLE);
1020
1021         if (type & IRQ_TYPE_EDGE_FALLING)
1022                 writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask,
1023                        bank->reg_base + FE_IRQ_ENABLE);
1024 }
1025
1026 static unsigned int oxnas_gpio_irq_startup(struct irq_data *data)
1027 {
1028         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1029
1030         oxnas_gpio_direction_input(chip, data->hwirq);
1031         oxnas_gpio_irq_unmask(data);
1032
1033         return 0;
1034 }
1035
1036 static int oxnas_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1037 {
1038         if ((type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) == 0)
1039                 return -EINVAL;
1040
1041         irq_set_handler_locked(data, handle_edge_irq);
1042
1043         return 0;
1044 }
1045
1046 static void oxnas_gpio_irq_handler(struct irq_desc *desc)
1047 {
1048         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1049         struct oxnas_gpio_bank *bank = gpiochip_get_data(gc);
1050         struct irq_chip *chip = irq_desc_get_chip(desc);
1051         unsigned long stat;
1052         unsigned int pin;
1053
1054         chained_irq_enter(chip, desc);
1055
1056         stat = readl(bank->reg_base + IRQ_PENDING);
1057
1058         for_each_set_bit(pin, &stat, BITS_PER_LONG)
1059                 generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
1060
1061         chained_irq_exit(chip, desc);
1062 }
1063
1064 #define GPIO_BANK(_bank)                                                \
1065         {                                                               \
1066                 .gpio_chip = {                                          \
1067                         .label = "GPIO" #_bank,                         \
1068                         .request = gpiochip_generic_request,            \
1069                         .free = gpiochip_generic_free,                  \
1070                         .get_direction = oxnas_gpio_get_direction,      \
1071                         .direction_input = oxnas_gpio_direction_input,  \
1072                         .direction_output = oxnas_gpio_direction_output, \
1073                         .get = oxnas_gpio_get,                          \
1074                         .set = oxnas_gpio_set,                          \
1075                         .ngpio = PINS_PER_BANK,                         \
1076                         .base = GPIO_BANK_START(_bank),                 \
1077                         .owner = THIS_MODULE,                           \
1078                         .can_sleep = 0,                                 \
1079                 },                                                      \
1080                 .irq_chip = {                                           \
1081                         .name = "GPIO" #_bank,                          \
1082                         .irq_startup = oxnas_gpio_irq_startup,  \
1083                         .irq_ack = oxnas_gpio_irq_ack,          \
1084                         .irq_mask = oxnas_gpio_irq_mask,                \
1085                         .irq_unmask = oxnas_gpio_irq_unmask,            \
1086                         .irq_set_type = oxnas_gpio_irq_set_type,        \
1087                 },                                                      \
1088         }
1089
1090 static struct oxnas_gpio_bank oxnas_gpio_banks[] = {
1091         GPIO_BANK(0),
1092         GPIO_BANK(1),
1093 };
1094
1095 static struct oxnas_pinctrl ox810se_pinctrl = {
1096         .functions = oxnas_ox810se_functions,
1097         .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions),
1098         .groups = oxnas_ox810se_groups,
1099         .ngroups = ARRAY_SIZE(oxnas_ox810se_groups),
1100         .gpio_banks = oxnas_gpio_banks,
1101         .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
1102 };
1103
1104 static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = {
1105         .name = "oxnas-pinctrl",
1106         .pins = oxnas_ox810se_pins,
1107         .npins = ARRAY_SIZE(oxnas_ox810se_pins),
1108         .pctlops = &oxnas_pinctrl_ops,
1109         .pmxops = &oxnas_ox810se_pinmux_ops,
1110         .confops = &oxnas_ox810se_pinconf_ops,
1111         .owner = THIS_MODULE,
1112 };
1113
1114 static struct oxnas_pinctrl ox820_pinctrl = {
1115         .functions = oxnas_ox820_functions,
1116         .nfunctions = ARRAY_SIZE(oxnas_ox820_functions),
1117         .groups = oxnas_ox820_groups,
1118         .ngroups = ARRAY_SIZE(oxnas_ox820_groups),
1119         .gpio_banks = oxnas_gpio_banks,
1120         .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
1121 };
1122
1123 static struct pinctrl_desc oxnas_ox820_pinctrl_desc = {
1124         .name = "oxnas-pinctrl",
1125         .pins = oxnas_ox820_pins,
1126         .npins = ARRAY_SIZE(oxnas_ox820_pins),
1127         .pctlops = &oxnas_pinctrl_ops,
1128         .pmxops = &oxnas_ox820_pinmux_ops,
1129         .confops = &oxnas_ox820_pinconf_ops,
1130         .owner = THIS_MODULE,
1131 };
1132
1133 static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = {
1134         .desc = &oxnas_ox810se_pinctrl_desc,
1135         .pctl = &ox810se_pinctrl,
1136 };
1137
1138 static struct oxnas_pinctrl_data oxnas_ox820_pinctrl_data = {
1139         .desc = &oxnas_ox820_pinctrl_desc,
1140         .pctl = &ox820_pinctrl,
1141 };
1142
1143 static const struct of_device_id oxnas_pinctrl_of_match[] = {
1144         { .compatible = "oxsemi,ox810se-pinctrl",
1145           .data = &oxnas_ox810se_pinctrl_data
1146         },
1147         { .compatible = "oxsemi,ox820-pinctrl",
1148           .data = &oxnas_ox820_pinctrl_data,
1149         },
1150         { },
1151 };
1152
1153 static int oxnas_pinctrl_probe(struct platform_device *pdev)
1154 {
1155         const struct of_device_id *id;
1156         const struct oxnas_pinctrl_data *data;
1157         struct oxnas_pinctrl *pctl;
1158
1159         id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node);
1160         if (!id)
1161                 return -ENODEV;
1162
1163         data = id->data;
1164         if (!data || !data->pctl || !data->desc)
1165                 return -EINVAL;
1166
1167         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1168         if (!pctl)
1169                 return -ENOMEM;
1170         pctl->dev = &pdev->dev;
1171         dev_set_drvdata(&pdev->dev, pctl);
1172
1173         pctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1174                                                        "oxsemi,sys-ctrl");
1175         if (IS_ERR(pctl->regmap)) {
1176                 dev_err(&pdev->dev, "failed to get sys ctrl regmap\n");
1177                 return -ENODEV;
1178         }
1179
1180         pctl->functions = data->pctl->functions;
1181         pctl->nfunctions = data->pctl->nfunctions;
1182         pctl->groups = data->pctl->groups;
1183         pctl->ngroups = data->pctl->ngroups;
1184         pctl->gpio_banks = data->pctl->gpio_banks;
1185         pctl->nbanks = data->pctl->nbanks;
1186
1187         pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl);
1188         if (IS_ERR(pctl->pctldev)) {
1189                 dev_err(&pdev->dev, "Failed to register pinctrl device\n");
1190                 return PTR_ERR(pctl->pctldev);
1191         }
1192
1193         return 0;
1194 }
1195
1196 static int oxnas_gpio_probe(struct platform_device *pdev)
1197 {
1198         struct device_node *np = pdev->dev.of_node;
1199         struct of_phandle_args pinspec;
1200         struct oxnas_gpio_bank *bank;
1201         unsigned int id, ngpios;
1202         int irq, ret;
1203         struct resource *res;
1204
1205         if (of_parse_phandle_with_fixed_args(np, "gpio-ranges",
1206                                              3, 0, &pinspec)) {
1207                 dev_err(&pdev->dev, "gpio-ranges property not found\n");
1208                 return -EINVAL;
1209         }
1210
1211         id = pinspec.args[1] / PINS_PER_BANK;
1212         ngpios = pinspec.args[2];
1213
1214         if (id >= ARRAY_SIZE(oxnas_gpio_banks)) {
1215                 dev_err(&pdev->dev, "invalid gpio-ranges base arg\n");
1216                 return -EINVAL;
1217         }
1218
1219         if (ngpios > PINS_PER_BANK) {
1220                 dev_err(&pdev->dev, "invalid gpio-ranges count arg\n");
1221                 return -EINVAL;
1222         }
1223
1224         bank = &oxnas_gpio_banks[id];
1225
1226         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1227         bank->reg_base = devm_ioremap_resource(&pdev->dev, res);
1228         if (IS_ERR(bank->reg_base))
1229                 return PTR_ERR(bank->reg_base);
1230
1231         irq = platform_get_irq(pdev, 0);
1232         if (irq < 0) {
1233                 dev_err(&pdev->dev, "irq get failed\n");
1234                 return irq;
1235         }
1236
1237         bank->id = id;
1238         bank->gpio_chip.parent = &pdev->dev;
1239         bank->gpio_chip.of_node = np;
1240         bank->gpio_chip.ngpio = ngpios;
1241         ret = gpiochip_add_data(&bank->gpio_chip, bank);
1242         if (ret < 0) {
1243                 dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
1244                         id, ret);
1245                 return ret;
1246         }
1247
1248         ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
1249                                 0, handle_level_irq, IRQ_TYPE_NONE);
1250         if (ret < 0) {
1251                 dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n",
1252                         id, ret);
1253                 gpiochip_remove(&bank->gpio_chip);
1254                 return ret;
1255         }
1256
1257         gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
1258                                      irq, oxnas_gpio_irq_handler);
1259
1260         return 0;
1261 }
1262
1263 static struct platform_driver oxnas_pinctrl_driver = {
1264         .driver = {
1265                 .name = "oxnas-pinctrl",
1266                 .of_match_table = oxnas_pinctrl_of_match,
1267                 .suppress_bind_attrs = true,
1268         },
1269         .probe = oxnas_pinctrl_probe,
1270 };
1271
1272 static const struct of_device_id oxnas_gpio_of_match[] = {
1273         { .compatible = "oxsemi,ox810se-gpio", },
1274         { .compatible = "oxsemi,ox820-gpio", },
1275         { },
1276 };
1277
1278 static struct platform_driver oxnas_gpio_driver = {
1279         .driver = {
1280                 .name = "oxnas-gpio",
1281                 .of_match_table = oxnas_gpio_of_match,
1282                 .suppress_bind_attrs = true,
1283         },
1284         .probe = oxnas_gpio_probe,
1285 };
1286
1287 static int __init oxnas_gpio_register(void)
1288 {
1289         return platform_driver_register(&oxnas_gpio_driver);
1290 }
1291 arch_initcall(oxnas_gpio_register);
1292
1293 static int __init oxnas_pinctrl_register(void)
1294 {
1295         return platform_driver_register(&oxnas_pinctrl_driver);
1296 }
1297 arch_initcall(oxnas_pinctrl_register);