1 // SPDX-License-Identifier: GPL-2.0+
3 * Atmel PIO pinctrl driver
5 * Copyright (C) 2016 Atmel Corporation
6 * Wenyou.Yang <wenyou.yang@atmel.com>
12 #include <dm/pinctrl.h>
13 #include <asm/hardware.h>
15 #include <linux/err.h>
16 #include <mach/at91_pio.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #define MAX_GPIO_BANKS 5
21 #define MAX_NB_GPIO_PER_BANK 32
23 #define MAX_PINMUX_ENTRIES 200
25 struct at91_pinctrl_priv {
26 struct at91_port *reg_base[MAX_GPIO_BANKS];
30 #define PULL_UP BIT(0)
31 #define MULTI_DRIVE BIT(1)
32 #define DEGLITCH BIT(2)
33 #define PULL_DOWN BIT(3)
34 #define DIS_SCHMIT BIT(4)
35 #define DRIVE_STRENGTH_SHIFT 5
36 #define DRIVE_STRENGTH_MASK 0x3
37 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
39 #define OUTPUT_VAL_SHIFT 8
40 #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
41 #define SLEWRATE_SHIFT 9
42 #define SLEWRATE_MASK 0x1
43 #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
44 #define DEBOUNCE BIT(16)
45 #define DEBOUNCE_VAL_SHIFT 17
46 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
49 * These defines will translated the dt binding settings to our internal
50 * settings. They are not necessarily the same value as the register setting.
51 * The actual drive strength current of low, medium and high must be looked up
52 * from the corresponding device datasheet. This value is different for pins
53 * that are even in the same banks. It is also dependent on VCC.
54 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
55 * strength when there is no dt config for it.
57 enum drive_strength_bit {
58 DRIVE_STRENGTH_BIT_DEF,
59 DRIVE_STRENGTH_BIT_LOW,
60 DRIVE_STRENGTH_BIT_MED,
61 DRIVE_STRENGTH_BIT_HI,
64 #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
72 #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
76 AT91_MUX_PERIPH_A = 1,
77 AT91_MUX_PERIPH_B = 2,
78 AT91_MUX_PERIPH_C = 3,
79 AT91_MUX_PERIPH_D = 4,
83 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
84 * on new IP with support for periph C and D the way to mux in
85 * periph A and B has changed
86 * So provide the right callbacks
87 * if not present means the IP does not support it
88 * @mux_A_periph: assign the corresponding pin to the peripheral A function.
89 * @mux_B_periph: assign the corresponding pin to the peripheral B function.
90 * @mux_C_periph: assign the corresponding pin to the peripheral C function.
91 * @mux_D_periph: assign the corresponding pin to the peripheral D function.
92 * @set_deglitch: enable/disable the deglitch feature.
93 * @set_debounce: enable/disable the debounce feature.
94 * @set_pulldown: enable/disable the pulldown feature.
95 * @disable_schmitt_trig: disable schmitt trigger
97 struct at91_pinctrl_mux_ops {
98 void (*mux_A_periph)(struct at91_port *pio, u32 mask);
99 void (*mux_B_periph)(struct at91_port *pio, u32 mask);
100 void (*mux_C_periph)(struct at91_port *pio, u32 mask);
101 void (*mux_D_periph)(struct at91_port *pio, u32 mask);
102 void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on);
103 void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on,
105 void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on);
106 void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
107 void (*set_drivestrength)(struct at91_port *pio, u32 pin,
109 void (*set_slewrate)(struct at91_port *pio, u32 pin, u32 slewrate);
112 static u32 two_bit_pin_value_shift_amount(u32 pin)
114 /* return the shift value for a pin for "two bit" per pin registers,
115 * i.e. drive strength */
116 return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2)
117 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
120 static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask)
122 writel(mask, &pio->idr);
125 static void at91_mux_set_pullup(struct at91_port *pio, u32 mask, bool on)
128 writel(mask, &pio->mux.pio3.ppddr);
130 writel(mask, (on ? &pio->puer : &pio->pudr));
133 static void at91_mux_set_output(struct at91_port *pio, unsigned mask,
134 bool is_on, bool val)
136 writel(mask, (val ? &pio->sodr : &pio->codr));
137 writel(mask, (is_on ? &pio->oer : &pio->odr));
140 static void at91_mux_set_multidrive(struct at91_port *pio, u32 mask, bool on)
142 writel(mask, (on ? &pio->mder : &pio->mddr));
145 static void at91_mux_set_A_periph(struct at91_port *pio, u32 mask)
147 writel(mask, &pio->mux.pio2.asr);
150 static void at91_mux_set_B_periph(struct at91_port *pio, u32 mask)
152 writel(mask, &pio->mux.pio2.bsr);
155 static void at91_mux_pio3_set_A_periph(struct at91_port *pio, u32 mask)
157 writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
158 writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
161 static void at91_mux_pio3_set_B_periph(struct at91_port *pio, u32 mask)
163 writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
164 writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
167 static void at91_mux_pio3_set_C_periph(struct at91_port *pio, u32 mask)
169 writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
170 writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
173 static void at91_mux_pio3_set_D_periph(struct at91_port *pio, u32 mask)
175 writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
176 writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
179 static void at91_mux_set_deglitch(struct at91_port *pio, u32 mask, bool is_on)
181 writel(mask, (is_on ? &pio->ifer : &pio->ifdr));
184 static void at91_mux_pio3_set_deglitch(struct at91_port *pio,
185 u32 mask, bool is_on)
188 writel(mask, &pio->mux.pio3.ifscdr);
189 at91_mux_set_deglitch(pio, mask, is_on);
192 static void at91_mux_pio3_set_debounce(struct at91_port *pio, u32 mask,
196 writel(mask, &pio->mux.pio3.ifscer);
197 writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);
198 writel(mask, &pio->ifer);
200 writel(mask, &pio->mux.pio3.ifscdr);
204 static void at91_mux_pio3_set_pulldown(struct at91_port *pio,
205 u32 mask, bool is_on)
208 writel(mask, &pio->pudr);
210 writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));
213 static void at91_mux_pio3_disable_schmitt_trig(struct at91_port *pio,
216 writel(readl(&pio->schmitt) | mask, &pio->schmitt);
219 static void set_drive_strength(void *reg, u32 pin, u32 strength)
221 u32 shift = two_bit_pin_value_shift_amount(pin);
223 clrsetbits_le32(reg, DRIVE_STRENGTH_MASK << shift, strength << shift);
226 static void at91_mux_sama5d3_set_drivestrength(struct at91_port *pio,
227 u32 pin, u32 setting)
231 reg = &pio->driver12;
232 if (pin >= MAX_NB_GPIO_PER_BANK / 2)
235 /* do nothing if setting is zero */
239 /* strength is 1 to 1 with setting for SAMA5 */
240 set_drive_strength(reg, pin, setting);
243 static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
244 u32 pin, u32 setting)
249 if (pin >= MAX_NB_GPIO_PER_BANK / 2)
250 reg = &pio->driver12;
252 /* do nothing if setting is zero */
256 /* strength is inverse on SAM9x5s with our defines
257 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
258 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
260 set_drive_strength(reg, pin, setting);
263 static void at91_mux_sam9x60_set_drivestrength(struct at91_port *pio, u32 pin,
266 void *reg = &pio->driver12;
269 if (setting <= DRIVE_STRENGTH_BIT_DEF ||
270 setting == DRIVE_STRENGTH_BIT_MED ||
271 setting > DRIVE_STRENGTH_BIT_HI)
276 /* Strength is 0: low, 1: hi */
277 if (setting == DRIVE_STRENGTH_BIT_LOW)
285 static void at91_mux_sam9x60_set_slewrate(struct at91_port *pio, u32 pin,
288 void *reg = &pio->reserved12[3];
291 if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
296 if (setting == SLEWRATE_BIT_DIS)
304 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
305 .mux_A_periph = at91_mux_set_A_periph,
306 .mux_B_periph = at91_mux_set_B_periph,
307 .set_deglitch = at91_mux_set_deglitch,
310 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
311 .mux_A_periph = at91_mux_pio3_set_A_periph,
312 .mux_B_periph = at91_mux_pio3_set_B_periph,
313 .mux_C_periph = at91_mux_pio3_set_C_periph,
314 .mux_D_periph = at91_mux_pio3_set_D_periph,
315 .set_deglitch = at91_mux_pio3_set_deglitch,
316 .set_debounce = at91_mux_pio3_set_debounce,
317 .set_pulldown = at91_mux_pio3_set_pulldown,
318 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
319 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
322 static struct at91_pinctrl_mux_ops sama5d3_ops = {
323 .mux_A_periph = at91_mux_pio3_set_A_periph,
324 .mux_B_periph = at91_mux_pio3_set_B_periph,
325 .mux_C_periph = at91_mux_pio3_set_C_periph,
326 .mux_D_periph = at91_mux_pio3_set_D_periph,
327 .set_deglitch = at91_mux_pio3_set_deglitch,
328 .set_debounce = at91_mux_pio3_set_debounce,
329 .set_pulldown = at91_mux_pio3_set_pulldown,
330 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
331 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
334 static struct at91_pinctrl_mux_ops sam9x60_ops = {
335 .mux_A_periph = at91_mux_pio3_set_A_periph,
336 .mux_B_periph = at91_mux_pio3_set_B_periph,
337 .mux_C_periph = at91_mux_pio3_set_C_periph,
338 .mux_D_periph = at91_mux_pio3_set_D_periph,
339 .set_deglitch = at91_mux_pio3_set_deglitch,
340 .set_debounce = at91_mux_pio3_set_debounce,
341 .set_pulldown = at91_mux_pio3_set_pulldown,
342 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
343 .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
344 .set_slewrate = at91_mux_sam9x60_set_slewrate,
347 static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
349 writel(mask, &pio->pdr);
352 static void at91_mux_gpio_enable(struct at91_port *pio, u32 mask, bool input)
354 writel(mask, &pio->per);
355 writel(mask, (input ? &pio->odr : &pio->oer));
358 static int at91_pmx_set(struct at91_pinctrl_mux_ops *ops,
359 struct at91_port *pio, u32 mask, enum at91_mux mux)
361 at91_mux_disable_interrupt(pio, mask);
364 at91_mux_gpio_enable(pio, mask, 1);
366 case AT91_MUX_PERIPH_A:
367 ops->mux_A_periph(pio, mask);
369 case AT91_MUX_PERIPH_B:
370 ops->mux_B_periph(pio, mask);
372 case AT91_MUX_PERIPH_C:
373 if (!ops->mux_C_periph)
375 ops->mux_C_periph(pio, mask);
377 case AT91_MUX_PERIPH_D:
378 if (!ops->mux_D_periph)
380 ops->mux_D_periph(pio, mask);
384 at91_mux_gpio_disable(pio, mask);
389 static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
390 struct at91_port *pio, u32 pin, u32 config)
394 if ((config & PULL_UP) && (config & PULL_DOWN))
397 at91_mux_set_output(pio, mask, config & OUTPUT,
398 (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
399 at91_mux_set_pullup(pio, mask, config & PULL_UP);
400 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
401 if (ops->set_deglitch)
402 ops->set_deglitch(pio, mask, config & DEGLITCH);
403 if (ops->set_debounce)
404 ops->set_debounce(pio, mask, config & DEBOUNCE,
405 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
406 if (ops->set_pulldown)
407 ops->set_pulldown(pio, mask, config & PULL_DOWN);
408 if (ops->disable_schmitt_trig && config & DIS_SCHMIT)
409 ops->disable_schmitt_trig(pio, mask);
410 if (ops->set_drivestrength)
411 ops->set_drivestrength(pio, pin,
412 (config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
413 if (ops->set_slewrate)
414 ops->set_slewrate(pio, pin,
415 (config & SLEWRATE) >> SLEWRATE_SHIFT);
420 static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin)
422 struct at91_pinctrl_priv *priv = dev_get_priv(dev);
424 if (bank >= priv->nbanks) {
425 debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks);
429 if (pin >= MAX_NB_GPIO_PER_BANK) {
430 debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK);
437 static int at91_pinctrl_set_state(struct udevice *dev, struct udevice *config)
439 struct at91_pinctrl_priv *priv = dev_get_priv(dev);
440 const void *blob = gd->fdt_blob;
441 int node = dev_of_offset(config);
442 u32 cells[MAX_PINMUX_ENTRIES];
443 const u32 *list = cells;
445 u32 conf, mask, count, i;
449 struct at91_port *pio;
450 struct at91_pinctrl_mux_ops *ops =
451 (struct at91_pinctrl_mux_ops *)dev_get_driver_data(dev);
454 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
455 * do sanity check and calculate pins number
457 size = fdtdec_get_int_array_count(blob, node, "atmel,pins",
458 cells, ARRAY_SIZE(cells));
460 /* we do not check return since it's safe node passed down */
465 for (i = 0; i < count; i++) {
471 ret = at91_pin_check_config(dev, bank, pin);
475 pio = priv->reg_base[bank];
478 ret = at91_pmx_set(ops, pio, mask, mux);
482 ret = at91_pinconf_set(ops, pio, pin, conf);
490 const struct pinctrl_ops at91_pinctrl_ops = {
491 .set_state = at91_pinctrl_set_state,
494 static int at91_pinctrl_probe(struct udevice *dev)
496 struct at91_pinctrl_priv *priv = dev_get_priv(dev);
497 fdt_addr_t addr_base;
500 for (index = 0; index < MAX_GPIO_BANKS; index++) {
501 addr_base = devfdt_get_addr_index(dev, index);
502 if (addr_base == FDT_ADDR_T_NONE)
505 priv->reg_base[index] = (struct at91_port *)addr_base;
508 priv->nbanks = index;
513 static const struct udevice_id at91_pinctrl_match[] = {
514 { .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
515 { .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
516 { .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },
517 { .compatible = "microchip,sam9x60-pinctrl", .data = (ulong)&sam9x60_ops },
521 U_BOOT_DRIVER(at91_pinctrl) = {
522 .name = "pinctrl_at91",
523 .id = UCLASS_PINCTRL,
524 .of_match = at91_pinctrl_match,
525 .probe = at91_pinctrl_probe,
526 .priv_auto_alloc_size = sizeof(struct at91_pinctrl_priv),
527 .ops = &at91_pinctrl_ops,