1 // SPDX-License-Identifier: GPL-2.0+
3 * Atmel PIO pinctrl driver
5 * Copyright (C) 2016 Atmel Corporation
6 * Wenyou.Yang <wenyou.yang@atmel.com>
11 #include <dm/pinctrl.h>
12 #include <asm/hardware.h>
14 #include <linux/err.h>
15 #include <mach/at91_pio.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 #define MAX_GPIO_BANKS 5
20 #define MAX_NB_GPIO_PER_BANK 32
22 #define MAX_PINMUX_ENTRIES 200
24 struct at91_pinctrl_priv {
25 struct at91_port *reg_base[MAX_GPIO_BANKS];
29 #define PULL_UP BIT(0)
30 #define MULTI_DRIVE BIT(1)
31 #define DEGLITCH BIT(2)
32 #define PULL_DOWN BIT(3)
33 #define DIS_SCHMIT BIT(4)
34 #define DRIVE_STRENGTH_SHIFT 5
35 #define DRIVE_STRENGTH_MASK 0x3
36 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
38 #define OUTPUT_VAL_SHIFT 8
39 #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
40 #define SLEWRATE_SHIFT 9
41 #define SLEWRATE_MASK 0x1
42 #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
43 #define DEBOUNCE BIT(16)
44 #define DEBOUNCE_VAL_SHIFT 17
45 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
48 * These defines will translated the dt binding settings to our internal
49 * settings. They are not necessarily the same value as the register setting.
50 * The actual drive strength current of low, medium and high must be looked up
51 * from the corresponding device datasheet. This value is different for pins
52 * that are even in the same banks. It is also dependent on VCC.
53 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
54 * strength when there is no dt config for it.
56 enum drive_strength_bit {
57 DRIVE_STRENGTH_BIT_DEF,
58 DRIVE_STRENGTH_BIT_LOW,
59 DRIVE_STRENGTH_BIT_MED,
60 DRIVE_STRENGTH_BIT_HI,
63 #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
71 #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
75 AT91_MUX_PERIPH_A = 1,
76 AT91_MUX_PERIPH_B = 2,
77 AT91_MUX_PERIPH_C = 3,
78 AT91_MUX_PERIPH_D = 4,
82 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
83 * on new IP with support for periph C and D the way to mux in
84 * periph A and B has changed
85 * So provide the right callbacks
86 * if not present means the IP does not support it
87 * @mux_A_periph: assign the corresponding pin to the peripheral A function.
88 * @mux_B_periph: assign the corresponding pin to the peripheral B function.
89 * @mux_C_periph: assign the corresponding pin to the peripheral C function.
90 * @mux_D_periph: assign the corresponding pin to the peripheral D function.
91 * @set_deglitch: enable/disable the deglitch feature.
92 * @set_debounce: enable/disable the debounce feature.
93 * @set_pulldown: enable/disable the pulldown feature.
94 * @disable_schmitt_trig: disable schmitt trigger
96 struct at91_pinctrl_mux_ops {
97 void (*mux_A_periph)(struct at91_port *pio, u32 mask);
98 void (*mux_B_periph)(struct at91_port *pio, u32 mask);
99 void (*mux_C_periph)(struct at91_port *pio, u32 mask);
100 void (*mux_D_periph)(struct at91_port *pio, u32 mask);
101 void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on);
102 void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on,
104 void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on);
105 void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
106 void (*set_drivestrength)(struct at91_port *pio, u32 pin,
108 void (*set_slewrate)(struct at91_port *pio, u32 pin, u32 slewrate);
111 static u32 two_bit_pin_value_shift_amount(u32 pin)
113 /* return the shift value for a pin for "two bit" per pin registers,
114 * i.e. drive strength */
115 return 2 * ((pin >= MAX_NB_GPIO_PER_BANK/2)
116 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
119 static void at91_mux_disable_interrupt(struct at91_port *pio, u32 mask)
121 writel(mask, &pio->idr);
124 static void at91_mux_set_pullup(struct at91_port *pio, u32 mask, bool on)
127 writel(mask, &pio->mux.pio3.ppddr);
129 writel(mask, (on ? &pio->puer : &pio->pudr));
132 static void at91_mux_set_output(struct at91_port *pio, unsigned mask,
133 bool is_on, bool val)
135 writel(mask, (val ? &pio->sodr : &pio->codr));
136 writel(mask, (is_on ? &pio->oer : &pio->odr));
139 static void at91_mux_set_multidrive(struct at91_port *pio, u32 mask, bool on)
141 writel(mask, (on ? &pio->mder : &pio->mddr));
144 static void at91_mux_set_A_periph(struct at91_port *pio, u32 mask)
146 writel(mask, &pio->mux.pio2.asr);
149 static void at91_mux_set_B_periph(struct at91_port *pio, u32 mask)
151 writel(mask, &pio->mux.pio2.bsr);
154 static void at91_mux_pio3_set_A_periph(struct at91_port *pio, u32 mask)
156 writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
157 writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
160 static void at91_mux_pio3_set_B_periph(struct at91_port *pio, u32 mask)
162 writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
163 writel(readl(&pio->mux.pio3.abcdsr2) & ~mask, &pio->mux.pio3.abcdsr2);
166 static void at91_mux_pio3_set_C_periph(struct at91_port *pio, u32 mask)
168 writel(readl(&pio->mux.pio3.abcdsr1) & ~mask, &pio->mux.pio3.abcdsr1);
169 writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
172 static void at91_mux_pio3_set_D_periph(struct at91_port *pio, u32 mask)
174 writel(readl(&pio->mux.pio3.abcdsr1) | mask, &pio->mux.pio3.abcdsr1);
175 writel(readl(&pio->mux.pio3.abcdsr2) | mask, &pio->mux.pio3.abcdsr2);
178 static void at91_mux_set_deglitch(struct at91_port *pio, u32 mask, bool is_on)
180 writel(mask, (is_on ? &pio->ifer : &pio->ifdr));
183 static void at91_mux_pio3_set_deglitch(struct at91_port *pio,
184 u32 mask, bool is_on)
187 writel(mask, &pio->mux.pio3.ifscdr);
188 at91_mux_set_deglitch(pio, mask, is_on);
191 static void at91_mux_pio3_set_debounce(struct at91_port *pio, u32 mask,
195 writel(mask, &pio->mux.pio3.ifscer);
196 writel(div & PIO_SCDR_DIV, &pio->mux.pio3.scdr);
197 writel(mask, &pio->ifer);
199 writel(mask, &pio->mux.pio3.ifscdr);
203 static void at91_mux_pio3_set_pulldown(struct at91_port *pio,
204 u32 mask, bool is_on)
207 writel(mask, &pio->pudr);
209 writel(mask, (is_on ? &pio->mux.pio3.ppder : &pio->mux.pio3.ppddr));
212 static void at91_mux_pio3_disable_schmitt_trig(struct at91_port *pio,
215 writel(readl(&pio->schmitt) | mask, &pio->schmitt);
218 static void set_drive_strength(void *reg, u32 pin, u32 strength)
220 u32 shift = two_bit_pin_value_shift_amount(pin);
222 clrsetbits_le32(reg, DRIVE_STRENGTH_MASK << shift, strength << shift);
225 static void at91_mux_sama5d3_set_drivestrength(struct at91_port *pio,
226 u32 pin, u32 setting)
230 reg = &pio->driver12;
231 if (pin >= MAX_NB_GPIO_PER_BANK / 2)
234 /* do nothing if setting is zero */
238 /* strength is 1 to 1 with setting for SAMA5 */
239 set_drive_strength(reg, pin, setting);
242 static void at91_mux_sam9x5_set_drivestrength(struct at91_port *pio,
243 u32 pin, u32 setting)
248 if (pin >= MAX_NB_GPIO_PER_BANK / 2)
249 reg = &pio->driver12;
251 /* do nothing if setting is zero */
255 /* strength is inverse on SAM9x5s with our defines
256 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
257 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
259 set_drive_strength(reg, pin, setting);
262 static void at91_mux_sam9x60_set_drivestrength(struct at91_port *pio, u32 pin,
265 void *reg = &pio->driver12;
268 if (setting <= DRIVE_STRENGTH_BIT_DEF ||
269 setting == DRIVE_STRENGTH_BIT_MED ||
270 setting > DRIVE_STRENGTH_BIT_HI)
275 /* Strength is 0: low, 1: hi */
276 if (setting == DRIVE_STRENGTH_BIT_LOW)
284 static void at91_mux_sam9x60_set_slewrate(struct at91_port *pio, u32 pin,
287 void *reg = &pio->reserved12[3];
290 if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
295 if (setting == SLEWRATE_BIT_DIS)
303 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
304 .mux_A_periph = at91_mux_set_A_periph,
305 .mux_B_periph = at91_mux_set_B_periph,
306 .set_deglitch = at91_mux_set_deglitch,
309 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
310 .mux_A_periph = at91_mux_pio3_set_A_periph,
311 .mux_B_periph = at91_mux_pio3_set_B_periph,
312 .mux_C_periph = at91_mux_pio3_set_C_periph,
313 .mux_D_periph = at91_mux_pio3_set_D_periph,
314 .set_deglitch = at91_mux_pio3_set_deglitch,
315 .set_debounce = at91_mux_pio3_set_debounce,
316 .set_pulldown = at91_mux_pio3_set_pulldown,
317 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
318 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
321 static struct at91_pinctrl_mux_ops sama5d3_ops = {
322 .mux_A_periph = at91_mux_pio3_set_A_periph,
323 .mux_B_periph = at91_mux_pio3_set_B_periph,
324 .mux_C_periph = at91_mux_pio3_set_C_periph,
325 .mux_D_periph = at91_mux_pio3_set_D_periph,
326 .set_deglitch = at91_mux_pio3_set_deglitch,
327 .set_debounce = at91_mux_pio3_set_debounce,
328 .set_pulldown = at91_mux_pio3_set_pulldown,
329 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
330 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
333 static struct at91_pinctrl_mux_ops sam9x60_ops = {
334 .mux_A_periph = at91_mux_pio3_set_A_periph,
335 .mux_B_periph = at91_mux_pio3_set_B_periph,
336 .mux_C_periph = at91_mux_pio3_set_C_periph,
337 .mux_D_periph = at91_mux_pio3_set_D_periph,
338 .set_deglitch = at91_mux_pio3_set_deglitch,
339 .set_debounce = at91_mux_pio3_set_debounce,
340 .set_pulldown = at91_mux_pio3_set_pulldown,
341 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
342 .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
343 .set_slewrate = at91_mux_sam9x60_set_slewrate,
346 static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
348 writel(mask, &pio->pdr);
351 static void at91_mux_gpio_enable(struct at91_port *pio, u32 mask, bool input)
353 writel(mask, &pio->per);
354 writel(mask, (input ? &pio->odr : &pio->oer));
357 static int at91_pmx_set(struct at91_pinctrl_mux_ops *ops,
358 struct at91_port *pio, u32 mask, enum at91_mux mux)
360 at91_mux_disable_interrupt(pio, mask);
363 at91_mux_gpio_enable(pio, mask, 1);
365 case AT91_MUX_PERIPH_A:
366 ops->mux_A_periph(pio, mask);
368 case AT91_MUX_PERIPH_B:
369 ops->mux_B_periph(pio, mask);
371 case AT91_MUX_PERIPH_C:
372 if (!ops->mux_C_periph)
374 ops->mux_C_periph(pio, mask);
376 case AT91_MUX_PERIPH_D:
377 if (!ops->mux_D_periph)
379 ops->mux_D_periph(pio, mask);
383 at91_mux_gpio_disable(pio, mask);
388 static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
389 struct at91_port *pio, u32 pin, u32 config)
393 if ((config & PULL_UP) && (config & PULL_DOWN))
396 at91_mux_set_output(pio, mask, config & OUTPUT,
397 (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
398 at91_mux_set_pullup(pio, mask, config & PULL_UP);
399 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
400 if (ops->set_deglitch)
401 ops->set_deglitch(pio, mask, config & DEGLITCH);
402 if (ops->set_debounce)
403 ops->set_debounce(pio, mask, config & DEBOUNCE,
404 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
405 if (ops->set_pulldown)
406 ops->set_pulldown(pio, mask, config & PULL_DOWN);
407 if (ops->disable_schmitt_trig && config & DIS_SCHMIT)
408 ops->disable_schmitt_trig(pio, mask);
409 if (ops->set_drivestrength)
410 ops->set_drivestrength(pio, pin,
411 (config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
412 if (ops->set_slewrate)
413 ops->set_slewrate(pio, pin,
414 (config & SLEWRATE) >> SLEWRATE_SHIFT);
419 static int at91_pin_check_config(struct udevice *dev, u32 bank, u32 pin)
421 struct at91_pinctrl_priv *priv = dev_get_priv(dev);
423 if (bank >= priv->nbanks) {
424 debug("pin conf bank %d >= nbanks %d\n", bank, priv->nbanks);
428 if (pin >= MAX_NB_GPIO_PER_BANK) {
429 debug("pin conf pin %d >= %d\n", pin, MAX_NB_GPIO_PER_BANK);
436 static int at91_pinctrl_set_state(struct udevice *dev, struct udevice *config)
438 struct at91_pinctrl_priv *priv = dev_get_priv(dev);
439 const void *blob = gd->fdt_blob;
440 int node = dev_of_offset(config);
441 u32 cells[MAX_PINMUX_ENTRIES];
442 const u32 *list = cells;
444 u32 conf, mask, count, i;
448 struct at91_port *pio;
449 struct at91_pinctrl_mux_ops *ops =
450 (struct at91_pinctrl_mux_ops *)dev_get_driver_data(dev);
453 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
454 * do sanity check and calculate pins number
456 size = fdtdec_get_int_array_count(blob, node, "atmel,pins",
457 cells, ARRAY_SIZE(cells));
459 /* we do not check return since it's safe node passed down */
464 for (i = 0; i < count; i++) {
470 ret = at91_pin_check_config(dev, bank, pin);
474 pio = priv->reg_base[bank];
477 ret = at91_pmx_set(ops, pio, mask, mux);
481 ret = at91_pinconf_set(ops, pio, pin, conf);
489 const struct pinctrl_ops at91_pinctrl_ops = {
490 .set_state = at91_pinctrl_set_state,
493 static int at91_pinctrl_probe(struct udevice *dev)
495 struct at91_pinctrl_priv *priv = dev_get_priv(dev);
496 fdt_addr_t addr_base;
499 for (index = 0; index < MAX_GPIO_BANKS; index++) {
500 addr_base = devfdt_get_addr_index(dev, index);
501 if (addr_base == FDT_ADDR_T_NONE)
504 priv->reg_base[index] = (struct at91_port *)addr_base;
507 priv->nbanks = index;
512 static const struct udevice_id at91_pinctrl_match[] = {
513 { .compatible = "atmel,sama5d3-pinctrl", .data = (ulong)&sama5d3_ops },
514 { .compatible = "atmel,at91sam9x5-pinctrl", .data = (ulong)&at91sam9x5_ops },
515 { .compatible = "atmel,at91rm9200-pinctrl", .data = (ulong)&at91rm9200_ops },
516 { .compatible = "microchip,sam9x60-pinctrl", .data = (ulong)&sam9x60_ops },
520 U_BOOT_DRIVER(at91_pinctrl) = {
521 .name = "pinctrl_at91",
522 .id = UCLASS_PINCTRL,
523 .of_match = at91_pinctrl_match,
524 .probe = at91_pinctrl_probe,
525 .priv_auto_alloc_size = sizeof(struct at91_pinctrl_priv),
526 .ops = &at91_pinctrl_ops,