drivers/pinctrl/nxp/pinctrl-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <malloc.h>
   8 #include <mapmem.h>
   9 #include <dm/device_compat.h>
  10 #include <dm/devres.h>
  11 #include <linux/bitops.h>
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <dm.h>
  15 #include <dm/pinctrl.h>
  16
  17 #include "pinctrl-imx.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  22 {
  23         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
  24         struct imx_pinctrl_soc_info *info = priv->info;
  25         int node = dev_of_offset(config);
  26         const struct fdt_property *prop;
  27         u32 *pin_data;
  28         int npins, size, pin_size;
  29         int mux_reg, conf_reg, input_reg;
  30         u32 input_val, mux_mode, config_val;
  31         u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
  32         int i, j = 0;
  33
  34         dev_dbg(dev, "%s: %s\n", __func__, config->name);
  35
  36         if (info->flags & IMX8_USE_SCU)
  37                 pin_size = SHARE_IMX8_PIN_SIZE;
  38         else if (info->flags & SHARE_MUX_CONF_REG)
  39                 pin_size = SHARE_FSL_PIN_SIZE;
  40         else
  41                 pin_size = FSL_PIN_SIZE;
  42
  43         prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
  44         if (!prop) {
  45                 dev_err(dev, "No fsl,pins property in node %s\n", config->name);
  46                 return -EINVAL;
  47         }
  48
  49         if (!size || size % pin_size) {
  50                 dev_err(dev, "Invalid fsl,pins property in node %s\n",
  51                         config->name);
  52                 return -EINVAL;
  53         }
  54
  55         pin_data = devm_kzalloc(dev, size, 0);
  56         if (!pin_data)
  57                 return -ENOMEM;
  58
  59         if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
  60                                  pin_data, size >> 2)) {
  61                 dev_err(dev, "Error reading pin data.\n");
  62                 devm_kfree(dev, pin_data);
  63                 return -EINVAL;
  64         }
  65
  66         npins = size / pin_size;
  67
  68         if (info->flags & IMX8_USE_SCU) {
  69                 imx_pinctrl_scu_conf_pins(info, pin_data, npins);
  70         } else {
  71                 /*
  72                  * Refer to linux documentation for details:
  73                  * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
  74                  */
  75                 for (i = 0; i < npins; i++) {
  76                         mux_reg = pin_data[j++];
  77
  78                         if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
  79                                 mux_reg = -1;
  80
  81                         if (info->flags & SHARE_MUX_CONF_REG) {
  82                                 conf_reg = mux_reg;
  83                         } else {
  84                                 conf_reg = pin_data[j++];
  85                                 if (!(info->flags & ZERO_OFFSET_VALID) &&
  86                                     !conf_reg)
  87                                         conf_reg = -1;
  88                         }
  89
  90                         if ((mux_reg == -1) || (conf_reg == -1)) {
  91                                 dev_err(dev, "Error mux_reg or conf_reg\n");
  92                                 devm_kfree(dev, pin_data);
  93                                 return -EINVAL;
  94                         }
  95
  96                         input_reg = pin_data[j++];
  97                         mux_mode = pin_data[j++];
  98                         input_val = pin_data[j++];
  99                         config_val = pin_data[j++];
 100
 101                         dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, "
 102                                 "input_reg 0x%x, mux_mode 0x%x, "
 103                                 "input_val 0x%x, config_val 0x%x\n",
 104                                 mux_reg, conf_reg, input_reg, mux_mode,
 105                                 input_val, config_val);
 106
 107                         if (config_val & IMX_PAD_SION)
 108                                 mux_mode |= IOMUXC_CONFIG_SION;
 109
 110                         config_val &= ~IMX_PAD_SION;
 111
 112                         /* Set Mux */
 113                         if (info->flags & SHARE_MUX_CONF_REG) {
 114                                 clrsetbits_le32(info->base + mux_reg,
 115                                                 info->mux_mask,
 116                                                 mux_mode << mux_shift);
 117                         } else {
 118                                 writel(mux_mode, info->base + mux_reg);
 119                         }
 120
 121                         dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
 122                                 mux_reg, mux_mode);
 123
 124                         /*
 125                          * Set select input
 126                          *
 127                          * If the select input value begins with 0xff,
 128                          * it's a quirky select input and the value should
 129                          * be interpreted as below.
 130                          *     31     23      15      7        0
 131                          *     | 0xff | shift | width | select |
 132                          * It's used to work around the problem that the
 133                          * select input for some pin is not implemented in
 134                          * the select input register but in some general
 135                          * purpose register. We encode the select input
 136                          * value, width and shift of the bit field into
 137                          * input_val cell of pin function ID in device tree,
 138                          * and then decode them here for setting up the select
 139                          * input bits in general purpose register.
 140                          */
 141
 142                         if (input_val >> 24 == 0xff) {
 143                                 u32 val = input_val;
 144                                 u8 select = val & 0xff;
 145                                 u8 width = (val >> 8) & 0xff;
 146                                 u8 shift = (val >> 16) & 0xff;
 147                                 u32 mask = ((1 << width) - 1) << shift;
 148                                 /*
 149                                  * The input_reg[i] here is actually some
 150                                  * IOMUXC general purpose register, not
 151                                  * regular select input register.
 152                                  */
 153                                 val = readl(info->base + input_reg);
 154                                 val &= ~mask;
 155                                 val |= select << shift;
 156                                 writel(val, info->base + input_reg);
 157                         } else if (input_reg) {
 158                                 /*
 159                                  * Regular select input register can never be
 160                                  * at offset 0, and we only print register
 161                                  * value for regular case.
 162                                  */
 163                                 if (info->input_sel_base)
 164                                         writel(input_val,
 165                                                info->input_sel_base +
 166                                                input_reg);
 167                                 else
 168                                         writel(input_val,
 169                                                info->base + input_reg);
 170
 171                                 dev_dbg(dev, "select_input: offset 0x%x val "
 172                                         "0x%x\n", input_reg, input_val);
 173                         }
 174
 175                         /* Set config */
 176                         if (!(config_val & IMX_NO_PAD_CTL)) {
 177                                 if (info->flags & SHARE_MUX_CONF_REG) {
 178                                         clrsetbits_le32(info->base + conf_reg,
 179                                                         ~info->mux_mask,
 180                                                         config_val);
 181                                 } else {
 182                                         writel(config_val,
 183                                                info->base + conf_reg);
 184                                 }
 185
 186                                 dev_dbg(dev, "write config: offset 0x%x val "
 187                                         "0x%x\n", conf_reg, config_val);
 188                         }
 189                 }
 190         }
 191
 192         devm_kfree(dev, pin_data);
 193
 194         return 0;
 195 }
 196
 197 const struct pinctrl_ops imx_pinctrl_ops  = {
 198         .set_state = imx_pinctrl_set_state,
 199 };
 200
 201 int imx_pinctrl_probe(struct udevice *dev,
 202                       struct imx_pinctrl_soc_info *info)
 203 {
 204         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 205         int node = dev_of_offset(dev), ret;
 206         struct fdtdec_phandle_args arg;
 207         fdt_addr_t addr;
 208         fdt_size_t size;
 209
 210         if (!info) {
 211                 dev_err(dev, "wrong pinctrl info\n");
 212                 return -EINVAL;
 213         }
 214
 215         priv->dev = dev;
 216         priv->info = info;
 217
 218         if (info->flags & IMX8_USE_SCU)
 219                 return 0;
 220
 221         addr = devfdt_get_addr_size_index(dev, 0, &size);
 222         if (addr == FDT_ADDR_T_NONE)
 223                 return -EINVAL;
 224
 225         info->base = map_sysmem(addr, size);
 226         if (!info->base)
 227                 return -ENOMEM;
 228         priv->info = info;
 229
 230         info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
 231         /*
 232          * Refer to linux documentation for details:
 233          * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
 234          */
 235         if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
 236                 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
 237                                                      node, "fsl,input-sel",
 238                                                      NULL, 0, 0, &arg);
 239                 if (ret) {
 240                         dev_err(dev, "iomuxc fsl,input-sel property not found\n");
 241                         return -EINVAL;
 242                 }
 243
 244                 addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
 245                                             &size);
 246                 if (addr == FDT_ADDR_T_NONE)
 247                         return -EINVAL;
 248
 249                 info->input_sel_base = map_sysmem(addr, size);
 250                 if (!info->input_sel_base)
 251                         return -ENOMEM;
 252         }
 253
 254         dev_dbg(dev, "initialized IMX pinctrl driver\n");
 255
 256         return 0;
 257 }
 258
 259 int imx_pinctrl_remove(struct udevice *dev)
 260 {
 261         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 262         struct imx_pinctrl_soc_info *info = priv->info;
 263
 264         if (info->flags & IMX8_USE_SCU)
 265                 return 0;
 266
 267         if (info->input_sel_base)
 268                 unmap_sysmem(info->input_sel_base);
 269         if (info->base)
 270                 unmap_sysmem(info->base);
 271
 272         return 0;
 273 }